Make ExpandWhens delete 'is invalid' for attached Analog components

Also add tests for what should happen to 'is invalid' in ExpandWhens
Fixes #606

2 files changed, 49 insertions, 3 deletions

diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala
index 1f093dd1..181fb642 100644
--- a/src/main/scala/firrtl/passes/ExpandWhens.scala
+++ b/src/main/scala/firrtl/passes/ExpandWhens.scala
@@ -45,9 +45,10 @@ object ExpandWhens extends Pass {
       }
     }
   }
-  private def expandNetlist(netlist: Netlist) =
+  private def expandNetlist(netlist: Netlist, attached: Set[WrappedExpression]) =
     netlist map {
-      case (k, WInvalid) => IsInvalid(NoInfo, k.e1)
+      case (k, WInvalid) => // Remove IsInvalids on attached Analog types
+        if (attached.contains(k)) EmptyStmt else IsInvalid(NoInfo, k.e1)
       case (k, v) => Connect(NoInfo, k.e1, v)
     }
   /** Combines Attaches
@@ -186,7 +187,8 @@ object ExpandWhens extends Pass {
       case m: ExtModule => m
       case m: Module =>
       val (netlist, simlist, attaches, bodyx) = expandWhens(m)
-      val newBody = Block(Seq(squashEmpty(bodyx)) ++ expandNetlist(netlist) ++
+      val attachedAnalogs = attaches.flatMap(_.exprs.map(we)).toSet
+      val newBody = Block(Seq(squashEmpty(bodyx)) ++ expandNetlist(netlist, attachedAnalogs) ++
                               combineAttaches(attaches) ++ simlist)
       Module(m.info, m.name, m.ports, newBody)
     }
diff --git a/src/test/scala/firrtlTests/ExpandWhensSpec.scala b/src/test/scala/firrtlTests/ExpandWhensSpec.scala
index 4911f619..66f39a3d 100644
--- a/src/test/scala/firrtlTests/ExpandWhensSpec.scala
+++ b/src/test/scala/firrtlTests/ExpandWhensSpec.scala
@@ -78,6 +78,50 @@ class ExpandWhensSpec extends FirrtlFlatSpec {
     val check = "VOID"
     executeTest(input, check, true)
   }
+  it should "replace 'is invalid' with validif for wires that have a connection" in {
+    val input =
+      """|circuit Tester :
+         |  module Tester :
+         |    input p : UInt<1>
+         |    output out : UInt
+         |    wire w : UInt<32>
+         |    w is invalid
+         |    out <= w
+         |    when p :
+         |      w <= UInt(123)
+         """.stripMargin
+    val check = "validif(p"
+    executeTest(input, check, true)
+  }
+  it should "leave 'is invalid' for wires that don't have a connection" in {
+    val input =
+      """|circuit Tester :
+         |  module Tester :
+         |    input p : UInt<1>
+         |    output out : UInt
+         |    wire w : UInt<32>
+         |    w is invalid
+         |    out <= w
+         """.stripMargin
+    val check = "w is invalid"
+    executeTest(input, check, true)
+  }
+  it should "delete 'is invalid' for attached Analog wires" in {
+    val input =
+      """|circuit Tester :
+         |  extmodule Child :
+         |    input bus : Analog<32>
+         |  module Tester :
+         |    input bus : Analog<32>
+         |    inst c of Child
+         |    wire w : Analog<32>
+         |    attach (w, bus)
+         |    attach (w, c.bus)
+         |    w is invalid
+         """.stripMargin
+    val check = "w is invalid"
+    executeTest(input, check, false)
+  }
 }
 
 class ExpandWhensExecutionTest extends ExecutionTest("ExpandWhens", "/passes/ExpandWhens")