diff options
| author | Jack Koenig | 2017-05-25 15:42:51 -0700 |
|---|---|---|
| committer | Jack Koenig | 2017-05-30 13:12:34 -0700 |
| commit | 562806aa9e95c4095fcb38c5a34421b6ddc6d3fe (patch) | |
| tree | 4ab587a79eac938a97bc4dfa23441b915cadea35 | |
| parent | aadae6a2ff9daf0324efd9b82307b68ec67efdf9 (diff) | |
Change base of randomization values to _RAND instead of _GEN
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 39ed55af..d5b0eee6 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -357,6 +357,7 @@ class VerilogEmitter extends SeqTransform with Emitter { val netlist = mutable.LinkedHashMap[WrappedExpression, Expression]() val addrRegs = mutable.HashSet[WrappedExpression]() val namespace = Namespace(m) + namespace.newName("_RAND") // Start rand names at _RAND_0 def build_netlist(s: Statement): Statement = s map build_netlist match { case sx: Connect => netlist(sx.loc) = sx.expr @@ -469,7 +470,7 @@ class VerilogEmitter extends SeqTransform with Emitter { // Declares an intermediate wire to hold a large enough random number. // Then, return the correct number of bits selected from the random value def rand_string(t: Type) : Seq[Any] = { - val nx = namespace.newTemp + val nx = namespace.newName("_RAND") val rand = VRandom(bitWidth(t)) val tx = SIntType(IntWidth(rand.realWidth)) declare("reg",nx, tx) |