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AgeCommit message (Expand)Author
2017-06-28Promote ConstProp to a transformJack Koenig
2017-06-28[Testing] Clean up SimpleTransformSpec execute methodsJack Koenig
2017-06-28[Testing] Have SimpleTransformSpec mix in FirrtlMatchersJack Koenig
2017-06-28Merge pull request #615 from freechipsproject/remove-resetJack Koenig
2017-06-27Add RemoveReset transform to replace register reset with a MuxJack Koenig
2017-06-27Emitting reg update mux tree, only walk netlist for wires and nodesJack Koenig
2017-06-26Add support for wires in ConstPropJack Koenig
2017-06-26Speed up ConstProp by doing ConstProp before recording nodeJack Koenig
2017-06-21Add --no-dce command-line option to skip DCEJack Koenig
2017-06-13Replace IsInvalids on LowForm with connection to zeroJack Koenig
2017-06-13Canonicalize spacing in RemoveValidIfJack Koenig
2017-06-13Make ExpandWhens delete 'is invalid' for attached Analog componentsJack Koenig
2017-06-13Style changes to ExpandWhensSpecJack Koenig
2017-06-12Add option to disable combinational loop detectionJack Koenig
2017-06-12Move CheckCombLoops from passes/ to transforms/Jack Koenig
2017-06-12Change CheckCombLoops to a TransformJack Koenig
2017-06-12Fixes a typo in the verilog `elsif code generation (#603)Shreesha Srinath
2017-06-08Update travis button for new organization (#602)Colin Schmidt
2017-06-06Display the total time firrtl took to compile (#599)Colin Schmidt
2017-05-30Change base of randomization values to _RAND instead of _GENJack Koenig
2017-05-30Add some comments to `endifJack Koenig
2017-05-27Prep for Scala 2.12 (#557)Jim Lawson
2017-05-25Fix performance bug in DCE (#596)Jack Koenig
2017-05-25Fix performance bug in ZeroWidth (#594)Jack Koenig
2017-05-19Delete black_box_verilog_files.f if we aren't going to create it - fixes #504...Jim Lawson
2017-05-18Bump scopt for prettier option parsing (#546)Schuyler Eldridge
2017-05-18Upgrade Logging facility (#488)Chick Markley
2017-05-17Make sure not to DCE input-only extmodules unless specified (#590)Jack Koenig
2017-05-12Bugfix: renaming instance ports was broken. (#588)Adam Izraelevitz
2017-05-12Fix pad, second try (#465)Adam Izraelevitz
2017-05-11Improved Global Dead Code Elimination (#549)Jack Koenig
2017-05-11Refactor WIR WSub{Field,Index,Access} - rename exp -> expr #521 (#586)Jim Lawson
2017-05-10Fix typo in ExecutionOptionsManager comment (#520)Colin Schmidt
2017-05-10Update rename2 (#478)Adam Izraelevitz
2017-05-03Add checks on register clock and reset types (#33) (#553)Albert Magyar
2017-05-03Add test for source locators on multi-line reset registers (#554)Jack Koenig
2017-04-28Add info on reset block lines to ANTLR grammar (#468)Albert Magyar
2017-04-20move circuit dumping to trace so debug gives annos only (#524)Colin Schmidt
2017-04-18"Scope" test resource (top.cpp). (#398)Jim Lawson
2017-04-13Speed up CSE by doing CSE on node expression before recording the node (#543)Jack Koenig
2017-04-04DecorateMems should not delete annoations (#523)Colin Schmidt
2017-04-03Change implicit value classes to prefix with _ (#522)Adam Izraelevitz
2017-04-03Find a single cycle from potentially many in a combinational SCCAlbert Magyar
2017-03-30Make force-append-anno-file work. Fixes #515 (#516)Jack Koenig
2017-03-30Change findSCCs to iterative implementation (#513)Albert Magyar
2017-03-29Fix bug where zero width expressions in nodes wouldn't get zeroed (#514)Jack Koenig
2017-03-23Add pass to detect combinational loopsAlbert Magyar
2017-03-23Pass now subclasses Transform (#477)Adam Izraelevitz
2017-03-23Add TargetDirAnnotation to give transforms access (#503)Jack Koenig
2017-03-22Throw different error message for missing emitannoAdam Izraelevitz
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