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AgeCommit message (Expand)Author
2017-11-28Have DedupModules report renamingJack
2017-11-28Refactor RenameMap to rename Components if their Module is renamedJack
2017-11-16Move digraph exceptions out of digraph class (#688)Albert Magyar
2017-11-16Make Yosys equivalence check more robust (#686)Jack Koenig
2017-11-10Make digraph methods deterministic (#653)Albert Magyar
2017-11-08Add InfoSpec for checking Info propagationJack Koenig
2017-11-08Add FirrtlCheckers and scalatest helpers for testingJack Koenig
2017-11-08Emit source locators as comments in emitted VerilogJack Koenig
2017-10-31Fix bug emitting and reparsing ExtModule String parameters (#675)Jack Koenig
2017-10-03Merge pull request #670 from freechipsproject/add-formal-checkJack Koenig
2017-10-01Add script for formally comparing emitted VerilogJack Koenig
2017-10-01Add Yosys 0.7 installJack Koenig
2017-10-01Remove redundant tests from TravisJack
2017-09-30Make ReplaceAccesses optimize multi-dimensional accesses (#665)Albert Magyar
2017-09-30Update README.md to link tech report (#550)Adam Izraelevitz
2017-09-30Fixed zero width cat but (#651)Adam Izraelevitz
2017-09-29StringLit.verilogEscape should support all printable ASCII chars (#668)Jack Koenig
2017-09-29Namespace - only save suffix for temp names (#667)Jack Koenig
2017-09-22Fix string lit (#663)Jack Koenig
2017-09-21Some ScalaDoc warning fixesEdward Wang
2017-09-21Fix problem where wrong verilog file is used. (#661)Chick Markley
2017-09-19Provide mechanism so that programs can optionally (#660)Chick Markley
2017-09-19Create way of collecting program arguments in Driver (#659)Chick Markley
2017-09-14Update sbt to 0.13.16; add Scala 2.12 support. (#639)Jim Lawson
2017-09-12Make pathsInDAG walk all possible paths (#655)Schuyler Eldridge
2017-09-06Write tests on multi-rooted circuits for ConstPropEdward Wang
2017-09-05Add InstanceGraph testsEdward Wang
2017-09-05Make InstanceGraph track module hierarchies not contained in the top-level hi...Albert Magyar
2017-08-31Added option to emit final annotations (#649)Adam Izraelevitz
2017-08-23Reorder port and wire assignments in Verilog (#641)Adam Izraelevitz
2017-08-14Constant propagation across module boundaries (#633)Jack Koenig
2017-08-04bug fix for cases when we want to flatten a module in which a module is insta...Andrey Ayupov
2017-08-01DCE for IsInvalid (#629)Donggyu
2017-07-26Flatten transformation (#631)Andrey Ayupov
2017-07-18Merge pull request #626 from freechipsproject/fix-swap-bugJack Koenig
2017-07-17do not swap wire names with node namesDonggyu Kim
2017-07-17Fix ConstProp bug where multiple names would swap with oneJack Koenig
2017-07-14Fix bug in DiGraph.reverse on an graph with one vertex, no edges (#628)Jack Koenig
2017-07-06Fixed inability to disable combo loop check (#619)Chick Markley
2017-07-03Merge pull request #621 from freechipsproject/const-prop-regsJack Koenig
2017-06-29ConstProp registers that are only connected to or reset to a consantJack Koenig
2017-06-29Connect registers with no connections to zeroJack Koenig
2017-06-29Add test for padding constant connections to wires in ConstPropJack Koenig
2017-06-29Merge pull request #620 from freechipsproject/keep-namesJack Koenig
2017-06-29Preserve "better" names in Constant PropagationJack Koenig
2017-06-29Merge pull request #616 from freechipsproject/split-travisJack Koenig
2017-06-29[Travis] Explicitly limit chisel tests parallelism to 2Jack
2017-06-29[Travis] Use Build StagesJack
2017-06-29Merge pull request #617 from freechipsproject/const-prop-regsJack Koenig
2017-06-28Make Constant Propagation respect dontTouchJack Koenig
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