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AgeCommit message (Expand)Author
2018-02-27Refactor Annotations (#721)Jack Koenig
2018-02-27Add log-level debug message for modules that get deduped (#748)Jack Koenig
2018-02-26Rename loadAnnotations -> getAnnotations (#747)Jack Koenig
2018-02-23Add graph summation "+" to DiGraph (#744)Schuyler Eldridge
2018-02-22Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, bu...Adam Izraelevitz
2018-02-21Change primop arg type (#587)Adam Izraelevitz
2018-02-16Replacematcherror - catch exceptions and convert to internal error. (#424)Jim Lawson
2018-02-16Update spec for rhsSchuyler Eldridge
2018-02-12Bump sbt to 1.1.1 and bump plugins (#739)Jack Koenig
2018-02-08CheckHighForm should check that Bits MSB >= LSB (#738)Schuyler Eldridge
2018-02-07Fix EulerTour for circuits with one module (#736)Schuyler Eldridge
2018-02-06Updatefromrelease - Incorporate lessons learned from latest publishing. (#656)Jim Lawson
2018-02-05Added comments to ExpandWhens (#716)Adam Izraelevitz
2018-01-30Merge pull request #735 from freechipsproject/fix-const-propJack Koenig
2018-01-30Make Constant Propagation respect dontTouch on registersJack Koenig
2018-01-30Fix bug incorrectly propagating constants on submodule inputsJack Koenig
2018-01-17Add firrtl-mode to README.md (#730)Schuyler Eldridge
2018-01-15WiringTransform Refactor (#648)Schuyler Eldridge
2018-01-09Update README.mdAdam Izraelevitz
2018-01-08Typo: ExecutionOptionManager -> ExecutionOptionsManager.Leway Colin
2018-01-05Fix FirrtlExecutionOptions backward incompatible change (#704). (#720)Jim Lawson
2018-01-05Remove erroneous undef of RANDOMIZE in emitted VerilogJack Koenig
2017-12-29Add support for multiple annotation filesJack
2017-12-29Actually emit annotations as YAML instead of default toStringJack
2017-12-29Remove option --force-append-anno-file, make defaultJack Koenig
2017-12-29Add Driver.dramaticWarningJack
2017-12-29Add logger printing for declarations removed by DCEJack Koenig
2017-12-29Add NodeCount analysis for helping with performance debuggingJack Koenig
2017-12-27Removed top preamble (#640)Adam Izraelevitz
2017-12-26Adjust isVCSAvailable commentedwardcwang
2017-12-26Update ISSUE_TEMPLATE.mdAdam Izraelevitz
2017-12-26Update ISSUE_TEMPLATE.mdAdam Izraelevitz
2017-12-24Spec erroneously says mod instead of rem.Paul Rigge
2017-12-22API change: out-of-bounds vec accesses now invalid, not first element (#685)Adam Izraelevitz
2017-12-20Verify shl/shr amount is > 0 (#710)Jim Lawson
2017-12-20Fix bug in ConstProp where module dependency edges were dropped (#696)Jack Koenig
2017-12-20Make submodule inputs void in ExpandWhens (#706)Jack Koenig
2017-12-20Add "checker" to the set of Verilog keywords - fixes 455. (#711)Jim Lawson
2017-12-19support -X sverilog to output xxxx.sv file (#638)Wei Song (宋威)
2017-12-19Make toNamed invert serialize (#709)Schuyler Eldridge
2017-12-18Create ISSUE_TEMPLATE.md (#699)Adam Izraelevitz
2017-12-18Bump sbt (#703)Jack Koenig
2017-12-15getBuildDir now builds full pathAdam Izraelevitz
2017-12-12Merge pull request #684 from freechipsproject/remove-wiresJack Koenig
2017-12-12Refactor formal equivalence CI testJack Koenig
2017-12-12Add RemoveWires transformJack Koenig
2017-12-12Improve MultiInfo emission, add apply that squashes NoInfoJack Koenig
2017-12-12Make object ConstantPropagation utilsJack Koenig
2017-12-12Bump scala and plugins. (#694)Jim Lawson
2017-11-29Add alternative graph IR (#671)Wenyu Tang
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