diff options
| author | Jack Koenig | 2017-12-12 15:33:00 -0800 |
|---|---|---|
| committer | Jack Koenig | 2017-12-12 15:34:43 -0800 |
| commit | 0d794d57df7b388109d7a0834d3b5be8f79892be (patch) | |
| tree | f557811fb961a3125bbfef95815eb81f72ca8346 | |
| parent | e39609a2bfbbd108fa1e5044e9c270685d75a816 (diff) | |
Refactor formal equivalence CI test
Make the check script allow different designs
Add FPU, ICache, and RocketCore to regress and use instead of Rob for CI
equivalence check
| -rwxr-xr-x[-rw-r--r--] | .run_formal_checks.sh | 12 | ||||
| -rw-r--r-- | .travis.yml | 8 | ||||
| -rw-r--r-- | regress/FPU.fir | 6827 | ||||
| -rw-r--r-- | regress/ICache.fir | 569 | ||||
| -rw-r--r-- | regress/RocketCore.fir | 6154 | ||||
| -rwxr-xr-x[-rw-r--r--] | scripts/formal_equiv.sh | 24 |
6 files changed, 13585 insertions, 9 deletions
diff --git a/.run_formal_checks.sh b/.run_formal_checks.sh index f3b72a67..ace9e4b0 100644..100755 --- a/.run_formal_checks.sh +++ b/.run_formal_checks.sh @@ -1,4 +1,13 @@ +#!/usr/bin/env bash set -e + +if [ $# -ne 1 ]; then + echo "There must be exactly one argument!" + exit -1 +fi + +DUT=$1 + # Run formal check only for PRs if [ $TRAVIS_PULL_REQUEST = "false" ]; then echo "Not a pull request, no formal check" @@ -13,5 +22,6 @@ else git remote set-branches origin $TRAVIS_BRANCH && git fetch git checkout $TRAVIS_BRANCH git checkout - - bash ./scripts/formal_equiv.sh HEAD $TRAVIS_BRANCH + cp regress/$DUT.fir $DUT.fir + ./scripts/formal_equiv.sh HEAD $TRAVIS_BRANCH $DUT fi diff --git a/.travis.yml b/.travis.yml index 2964924d..97dbfd4e 100644 --- a/.travis.yml +++ b/.travis.yml @@ -34,4 +34,10 @@ jobs: - bash .run_chisel_tests.sh - stage: test script: - - travis_wait 90 bash .run_formal_checks.sh + - ./.run_formal_checks.sh RocketCore + - stage: test + script: + - ./.run_formal_checks.sh FPU + - stage: test + script: + - ./.run_formal_checks.sh ICache diff --git a/regress/FPU.fir b/regress/FPU.fir new file mode 100644 index 00000000..75045296 --- /dev/null +++ b/regress/FPU.fir @@ -0,0 +1,6827 @@ +circuit FPU : + module FPU : + input clock : Clock + input reset : UInt<1> + output io : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip cp_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} + + io is invalid + io is invalid + reg ex_reg_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[FPU.scala 509:25] + ex_reg_valid <= io.valid @[FPU.scala 509:25] + node req_valid = or(ex_reg_valid, io.cp_req.valid) @[FPU.scala 510:32] + reg ex_reg_inst : UInt<32>, clock @[Reg.scala 34:16] + when io.valid : @[Reg.scala 35:19] + ex_reg_inst <= io.inst @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node ex_cp_valid = and(io.cp_req.ready, io.cp_req.valid) @[Decoupled.scala 30:37] + node _T_215 = eq(io.killx, UInt<1>("h00")) @[FPU.scala 513:48] + node _T_216 = and(ex_reg_valid, _T_215) @[FPU.scala 513:45] + node _T_217 = or(_T_216, ex_cp_valid) @[FPU.scala 513:58] + reg mem_reg_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[FPU.scala 513:26] + mem_reg_valid <= _T_217 @[FPU.scala 513:26] + reg mem_reg_inst : UInt<32>, clock @[Reg.scala 34:16] + when ex_reg_valid : @[Reg.scala 35:19] + mem_reg_inst <= ex_reg_inst @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg mem_cp_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[FPU.scala 515:25] + mem_cp_valid <= ex_cp_valid @[FPU.scala 515:25] + node _T_221 = or(io.killm, io.nack_mem) @[FPU.scala 516:25] + node _T_223 = eq(mem_cp_valid, UInt<1>("h00")) @[FPU.scala 516:44] + node killm = and(_T_221, _T_223) @[FPU.scala 516:41] + node _T_225 = eq(killm, UInt<1>("h00")) @[FPU.scala 517:49] + node _T_226 = or(_T_225, mem_cp_valid) @[FPU.scala 517:56] + node _T_227 = and(mem_reg_valid, _T_226) @[FPU.scala 517:45] + reg wb_reg_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[FPU.scala 517:25] + wb_reg_valid <= _T_227 @[FPU.scala 517:25] + reg wb_cp_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[FPU.scala 518:24] + wb_cp_valid <= mem_cp_valid @[FPU.scala 518:24] + inst fp_decoder of FPUDecoder @[FPU.scala 520:26] + fp_decoder.io is invalid + fp_decoder.clock <= clock + fp_decoder.reset <= reset + fp_decoder.io.inst <= io.inst @[FPU.scala 521:22] + wire cp_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>} @[FPU.scala 523:21] + cp_ctrl is invalid @[FPU.scala 523:21] + cp_ctrl <- io.cp_req.bits @[FPU.scala 524:11] + io.cp_resp.valid <= UInt<1>("h00") @[FPU.scala 525:20] + io.cp_resp.bits.data <= UInt<1>("h00") @[FPU.scala 526:24] + reg _T_282 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>}, clock @[Reg.scala 34:16] + when io.valid : @[Reg.scala 35:19] + _T_282 <- fp_decoder.io.sigs @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node ex_ctrl = mux(ex_cp_valid, cp_ctrl, _T_282) @[FPU.scala 529:20] + reg mem_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>}, clock @[Reg.scala 34:16] + when req_valid : @[Reg.scala 35:19] + mem_ctrl <- ex_ctrl @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg wb_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>}, clock @[Reg.scala 34:16] + when mem_reg_valid : @[Reg.scala 35:19] + wb_ctrl <- mem_ctrl @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg load_wb : UInt<1>, clock @[FPU.scala 534:20] + load_wb <= io.dmem_resp_val @[FPU.scala 534:20] + node _T_381 = bits(io.dmem_resp_type, 0, 0) @[FPU.scala 535:52] + node _T_383 = eq(_T_381, UInt<1>("h00")) @[FPU.scala 535:34] + reg load_wb_single : UInt<1>, clock @[Reg.scala 34:16] + when io.dmem_resp_val : @[Reg.scala 35:19] + load_wb_single <= _T_383 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg load_wb_data : UInt<64>, clock @[Reg.scala 34:16] + when io.dmem_resp_val : @[Reg.scala 35:19] + load_wb_data <= io.dmem_resp_data @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg load_wb_tag : UInt<5>, clock @[Reg.scala 34:16] + when io.dmem_resp_val : @[Reg.scala 35:19] + load_wb_tag <= io.dmem_resp_tag @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_387 = bits(load_wb_data, 31, 31) @[recFNFromFN.scala 47:22] + node _T_388 = bits(load_wb_data, 30, 23) @[recFNFromFN.scala 48:23] + node _T_389 = bits(load_wb_data, 22, 0) @[recFNFromFN.scala 49:25] + node _T_391 = eq(_T_388, UInt<1>("h00")) @[recFNFromFN.scala 51:34] + node _T_393 = eq(_T_389, UInt<1>("h00")) @[recFNFromFN.scala 52:38] + node _T_394 = and(_T_391, _T_393) @[recFNFromFN.scala 53:34] + node _T_395 = shl(_T_389, 9) @[recFNFromFN.scala 56:26] + node _T_396 = bits(_T_395, 31, 16) @[CircuitMath.scala 35:17] + node _T_397 = bits(_T_395, 15, 0) @[CircuitMath.scala 36:17] + node _T_399 = neq(_T_396, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_400 = bits(_T_396, 15, 8) @[CircuitMath.scala 35:17] + node _T_401 = bits(_T_396, 7, 0) @[CircuitMath.scala 36:17] + node _T_403 = neq(_T_400, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_404 = bits(_T_400, 7, 4) @[CircuitMath.scala 35:17] + node _T_405 = bits(_T_400, 3, 0) @[CircuitMath.scala 36:17] + node _T_407 = neq(_T_404, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_408 = bits(_T_404, 3, 3) @[CircuitMath.scala 32:12] + node _T_410 = bits(_T_404, 2, 2) @[CircuitMath.scala 32:12] + node _T_412 = bits(_T_404, 1, 1) @[CircuitMath.scala 30:8] + node _T_413 = mux(_T_410, UInt<2>("h02"), _T_412) @[CircuitMath.scala 32:10] + node _T_414 = mux(_T_408, UInt<2>("h03"), _T_413) @[CircuitMath.scala 32:10] + node _T_415 = bits(_T_405, 3, 3) @[CircuitMath.scala 32:12] + node _T_417 = bits(_T_405, 2, 2) @[CircuitMath.scala 32:12] + node _T_419 = bits(_T_405, 1, 1) @[CircuitMath.scala 30:8] + node _T_420 = mux(_T_417, UInt<2>("h02"), _T_419) @[CircuitMath.scala 32:10] + node _T_421 = mux(_T_415, UInt<2>("h03"), _T_420) @[CircuitMath.scala 32:10] + node _T_422 = mux(_T_407, _T_414, _T_421) @[CircuitMath.scala 38:21] + node _T_423 = cat(_T_407, _T_422) @[Cat.scala 30:58] + node _T_424 = bits(_T_401, 7, 4) @[CircuitMath.scala 35:17] + node _T_425 = bits(_T_401, 3, 0) @[CircuitMath.scala 36:17] + node _T_427 = neq(_T_424, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_428 = bits(_T_424, 3, 3) @[CircuitMath.scala 32:12] + node _T_430 = bits(_T_424, 2, 2) @[CircuitMath.scala 32:12] + node _T_432 = bits(_T_424, 1, 1) @[CircuitMath.scala 30:8] + node _T_433 = mux(_T_430, UInt<2>("h02"), _T_432) @[CircuitMath.scala 32:10] + node _T_434 = mux(_T_428, UInt<2>("h03"), _T_433) @[CircuitMath.scala 32:10] + node _T_435 = bits(_T_425, 3, 3) @[CircuitMath.scala 32:12] + node _T_437 = bits(_T_425, 2, 2) @[CircuitMath.scala 32:12] + node _T_439 = bits(_T_425, 1, 1) @[CircuitMath.scala 30:8] + node _T_440 = mux(_T_437, UInt<2>("h02"), _T_439) @[CircuitMath.scala 32:10] + node _T_441 = mux(_T_435, UInt<2>("h03"), _T_440) @[CircuitMath.scala 32:10] + node _T_442 = mux(_T_427, _T_434, _T_441) @[CircuitMath.scala 38:21] + node _T_443 = cat(_T_427, _T_442) @[Cat.scala 30:58] + node _T_444 = mux(_T_403, _T_423, _T_443) @[CircuitMath.scala 38:21] + node _T_445 = cat(_T_403, _T_444) @[Cat.scala 30:58] + node _T_446 = bits(_T_397, 15, 8) @[CircuitMath.scala 35:17] + node _T_447 = bits(_T_397, 7, 0) @[CircuitMath.scala 36:17] + node _T_449 = neq(_T_446, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_450 = bits(_T_446, 7, 4) @[CircuitMath.scala 35:17] + node _T_451 = bits(_T_446, 3, 0) @[CircuitMath.scala 36:17] + node _T_453 = neq(_T_450, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_454 = bits(_T_450, 3, 3) @[CircuitMath.scala 32:12] + node _T_456 = bits(_T_450, 2, 2) @[CircuitMath.scala 32:12] + node _T_458 = bits(_T_450, 1, 1) @[CircuitMath.scala 30:8] + node _T_459 = mux(_T_456, UInt<2>("h02"), _T_458) @[CircuitMath.scala 32:10] + node _T_460 = mux(_T_454, UInt<2>("h03"), _T_459) @[CircuitMath.scala 32:10] + node _T_461 = bits(_T_451, 3, 3) @[CircuitMath.scala 32:12] + node _T_463 = bits(_T_451, 2, 2) @[CircuitMath.scala 32:12] + node _T_465 = bits(_T_451, 1, 1) @[CircuitMath.scala 30:8] + node _T_466 = mux(_T_463, UInt<2>("h02"), _T_465) @[CircuitMath.scala 32:10] + node _T_467 = mux(_T_461, UInt<2>("h03"), _T_466) @[CircuitMath.scala 32:10] + node _T_468 = mux(_T_453, _T_460, _T_467) @[CircuitMath.scala 38:21] + node _T_469 = cat(_T_453, _T_468) @[Cat.scala 30:58] + node _T_470 = bits(_T_447, 7, 4) @[CircuitMath.scala 35:17] + node _T_471 = bits(_T_447, 3, 0) @[CircuitMath.scala 36:17] + node _T_473 = neq(_T_470, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_474 = bits(_T_470, 3, 3) @[CircuitMath.scala 32:12] + node _T_476 = bits(_T_470, 2, 2) @[CircuitMath.scala 32:12] + node _T_478 = bits(_T_470, 1, 1) @[CircuitMath.scala 30:8] + node _T_479 = mux(_T_476, UInt<2>("h02"), _T_478) @[CircuitMath.scala 32:10] + node _T_480 = mux(_T_474, UInt<2>("h03"), _T_479) @[CircuitMath.scala 32:10] + node _T_481 = bits(_T_471, 3, 3) @[CircuitMath.scala 32:12] + node _T_483 = bits(_T_471, 2, 2) @[CircuitMath.scala 32:12] + node _T_485 = bits(_T_471, 1, 1) @[CircuitMath.scala 30:8] + node _T_486 = mux(_T_483, UInt<2>("h02"), _T_485) @[CircuitMath.scala 32:10] + node _T_487 = mux(_T_481, UInt<2>("h03"), _T_486) @[CircuitMath.scala 32:10] + node _T_488 = mux(_T_473, _T_480, _T_487) @[CircuitMath.scala 38:21] + node _T_489 = cat(_T_473, _T_488) @[Cat.scala 30:58] + node _T_490 = mux(_T_449, _T_469, _T_489) @[CircuitMath.scala 38:21] + node _T_491 = cat(_T_449, _T_490) @[Cat.scala 30:58] + node _T_492 = mux(_T_399, _T_445, _T_491) @[CircuitMath.scala 38:21] + node _T_493 = cat(_T_399, _T_492) @[Cat.scala 30:58] + node _T_494 = not(_T_493) @[recFNFromFN.scala 56:13] + node _T_495 = dshl(_T_389, _T_494) @[recFNFromFN.scala 58:25] + node _T_496 = bits(_T_495, 21, 0) @[recFNFromFN.scala 58:37] + node _T_498 = cat(_T_496, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_503 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 71:12] + node _T_504 = xor(_T_494, _T_503) @[recFNFromFN.scala 62:27] + node _T_505 = mux(_T_391, _T_504, _T_388) @[recFNFromFN.scala 61:16] + node _T_509 = mux(_T_391, UInt<2>("h02"), UInt<1>("h01")) @[recFNFromFN.scala 64:47] + node _T_510 = or(UInt<8>("h080"), _T_509) @[recFNFromFN.scala 64:42] + node _T_511 = add(_T_505, _T_510) @[recFNFromFN.scala 64:15] + node _T_512 = tail(_T_511, 1) @[recFNFromFN.scala 64:15] + node _T_513 = bits(_T_512, 8, 7) @[recFNFromFN.scala 67:25] + node _T_515 = eq(_T_513, UInt<2>("h03")) @[recFNFromFN.scala 67:50] + node _T_517 = eq(_T_393, UInt<1>("h00")) @[recFNFromFN.scala 68:17] + node _T_518 = and(_T_515, _T_517) @[recFNFromFN.scala 67:63] + node _T_519 = bits(_T_394, 0, 0) @[Bitwise.scala 71:15] + node _T_522 = mux(_T_519, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 71:12] + node _T_523 = shl(_T_522, 6) @[recFNFromFN.scala 71:45] + node _T_524 = not(_T_523) @[recFNFromFN.scala 71:28] + node _T_525 = and(_T_512, _T_524) @[recFNFromFN.scala 71:26] + node _T_526 = shl(_T_518, 6) @[recFNFromFN.scala 72:22] + node _T_527 = or(_T_525, _T_526) @[recFNFromFN.scala 71:64] + node _T_528 = mux(_T_391, _T_498, _T_389) @[recFNFromFN.scala 73:27] + node _T_529 = cat(_T_387, _T_527) @[Cat.scala 30:58] + node rec_s = cat(_T_529, _T_528) @[Cat.scala 30:58] + node _T_530 = bits(load_wb_data, 63, 63) @[recFNFromFN.scala 47:22] + node _T_531 = bits(load_wb_data, 62, 52) @[recFNFromFN.scala 48:23] + node _T_532 = bits(load_wb_data, 51, 0) @[recFNFromFN.scala 49:25] + node _T_534 = eq(_T_531, UInt<1>("h00")) @[recFNFromFN.scala 51:34] + node _T_536 = eq(_T_532, UInt<1>("h00")) @[recFNFromFN.scala 52:38] + node _T_537 = and(_T_534, _T_536) @[recFNFromFN.scala 53:34] + node _T_538 = shl(_T_532, 12) @[recFNFromFN.scala 56:26] + node _T_539 = bits(_T_538, 63, 32) @[CircuitMath.scala 35:17] + node _T_540 = bits(_T_538, 31, 0) @[CircuitMath.scala 36:17] + node _T_542 = neq(_T_539, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_543 = bits(_T_539, 31, 16) @[CircuitMath.scala 35:17] + node _T_544 = bits(_T_539, 15, 0) @[CircuitMath.scala 36:17] + node _T_546 = neq(_T_543, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_547 = bits(_T_543, 15, 8) @[CircuitMath.scala 35:17] + node _T_548 = bits(_T_543, 7, 0) @[CircuitMath.scala 36:17] + node _T_550 = neq(_T_547, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_551 = bits(_T_547, 7, 4) @[CircuitMath.scala 35:17] + node _T_552 = bits(_T_547, 3, 0) @[CircuitMath.scala 36:17] + node _T_554 = neq(_T_551, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_555 = bits(_T_551, 3, 3) @[CircuitMath.scala 32:12] + node _T_557 = bits(_T_551, 2, 2) @[CircuitMath.scala 32:12] + node _T_559 = bits(_T_551, 1, 1) @[CircuitMath.scala 30:8] + node _T_560 = mux(_T_557, UInt<2>("h02"), _T_559) @[CircuitMath.scala 32:10] + node _T_561 = mux(_T_555, UInt<2>("h03"), _T_560) @[CircuitMath.scala 32:10] + node _T_562 = bits(_T_552, 3, 3) @[CircuitMath.scala 32:12] + node _T_564 = bits(_T_552, 2, 2) @[CircuitMath.scala 32:12] + node _T_566 = bits(_T_552, 1, 1) @[CircuitMath.scala 30:8] + node _T_567 = mux(_T_564, UInt<2>("h02"), _T_566) @[CircuitMath.scala 32:10] + node _T_568 = mux(_T_562, UInt<2>("h03"), _T_567) @[CircuitMath.scala 32:10] + node _T_569 = mux(_T_554, _T_561, _T_568) @[CircuitMath.scala 38:21] + node _T_570 = cat(_T_554, _T_569) @[Cat.scala 30:58] + node _T_571 = bits(_T_548, 7, 4) @[CircuitMath.scala 35:17] + node _T_572 = bits(_T_548, 3, 0) @[CircuitMath.scala 36:17] + node _T_574 = neq(_T_571, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_575 = bits(_T_571, 3, 3) @[CircuitMath.scala 32:12] + node _T_577 = bits(_T_571, 2, 2) @[CircuitMath.scala 32:12] + node _T_579 = bits(_T_571, 1, 1) @[CircuitMath.scala 30:8] + node _T_580 = mux(_T_577, UInt<2>("h02"), _T_579) @[CircuitMath.scala 32:10] + node _T_581 = mux(_T_575, UInt<2>("h03"), _T_580) @[CircuitMath.scala 32:10] + node _T_582 = bits(_T_572, 3, 3) @[CircuitMath.scala 32:12] + node _T_584 = bits(_T_572, 2, 2) @[CircuitMath.scala 32:12] + node _T_586 = bits(_T_572, 1, 1) @[CircuitMath.scala 30:8] + node _T_587 = mux(_T_584, UInt<2>("h02"), _T_586) @[CircuitMath.scala 32:10] + node _T_588 = mux(_T_582, UInt<2>("h03"), _T_587) @[CircuitMath.scala 32:10] + node _T_589 = mux(_T_574, _T_581, _T_588) @[CircuitMath.scala 38:21] + node _T_590 = cat(_T_574, _T_589) @[Cat.scala 30:58] + node _T_591 = mux(_T_550, _T_570, _T_590) @[CircuitMath.scala 38:21] + node _T_592 = cat(_T_550, _T_591) @[Cat.scala 30:58] + node _T_593 = bits(_T_544, 15, 8) @[CircuitMath.scala 35:17] + node _T_594 = bits(_T_544, 7, 0) @[CircuitMath.scala 36:17] + node _T_596 = neq(_T_593, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_597 = bits(_T_593, 7, 4) @[CircuitMath.scala 35:17] + node _T_598 = bits(_T_593, 3, 0) @[CircuitMath.scala 36:17] + node _T_600 = neq(_T_597, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_601 = bits(_T_597, 3, 3) @[CircuitMath.scala 32:12] + node _T_603 = bits(_T_597, 2, 2) @[CircuitMath.scala 32:12] + node _T_605 = bits(_T_597, 1, 1) @[CircuitMath.scala 30:8] + node _T_606 = mux(_T_603, UInt<2>("h02"), _T_605) @[CircuitMath.scala 32:10] + node _T_607 = mux(_T_601, UInt<2>("h03"), _T_606) @[CircuitMath.scala 32:10] + node _T_608 = bits(_T_598, 3, 3) @[CircuitMath.scala 32:12] + node _T_610 = bits(_T_598, 2, 2) @[CircuitMath.scala 32:12] + node _T_612 = bits(_T_598, 1, 1) @[CircuitMath.scala 30:8] + node _T_613 = mux(_T_610, UInt<2>("h02"), _T_612) @[CircuitMath.scala 32:10] + node _T_614 = mux(_T_608, UInt<2>("h03"), _T_613) @[CircuitMath.scala 32:10] + node _T_615 = mux(_T_600, _T_607, _T_614) @[CircuitMath.scala 38:21] + node _T_616 = cat(_T_600, _T_615) @[Cat.scala 30:58] + node _T_617 = bits(_T_594, 7, 4) @[CircuitMath.scala 35:17] + node _T_618 = bits(_T_594, 3, 0) @[CircuitMath.scala 36:17] + node _T_620 = neq(_T_617, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_621 = bits(_T_617, 3, 3) @[CircuitMath.scala 32:12] + node _T_623 = bits(_T_617, 2, 2) @[CircuitMath.scala 32:12] + node _T_625 = bits(_T_617, 1, 1) @[CircuitMath.scala 30:8] + node _T_626 = mux(_T_623, UInt<2>("h02"), _T_625) @[CircuitMath.scala 32:10] + node _T_627 = mux(_T_621, UInt<2>("h03"), _T_626) @[CircuitMath.scala 32:10] + node _T_628 = bits(_T_618, 3, 3) @[CircuitMath.scala 32:12] + node _T_630 = bits(_T_618, 2, 2) @[CircuitMath.scala 32:12] + node _T_632 = bits(_T_618, 1, 1) @[CircuitMath.scala 30:8] + node _T_633 = mux(_T_630, UInt<2>("h02"), _T_632) @[CircuitMath.scala 32:10] + node _T_634 = mux(_T_628, UInt<2>("h03"), _T_633) @[CircuitMath.scala 32:10] + node _T_635 = mux(_T_620, _T_627, _T_634) @[CircuitMath.scala 38:21] + node _T_636 = cat(_T_620, _T_635) @[Cat.scala 30:58] + node _T_637 = mux(_T_596, _T_616, _T_636) @[CircuitMath.scala 38:21] + node _T_638 = cat(_T_596, _T_637) @[Cat.scala 30:58] + node _T_639 = mux(_T_546, _T_592, _T_638) @[CircuitMath.scala 38:21] + node _T_640 = cat(_T_546, _T_639) @[Cat.scala 30:58] + node _T_641 = bits(_T_540, 31, 16) @[CircuitMath.scala 35:17] + node _T_642 = bits(_T_540, 15, 0) @[CircuitMath.scala 36:17] + node _T_644 = neq(_T_641, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_645 = bits(_T_641, 15, 8) @[CircuitMath.scala 35:17] + node _T_646 = bits(_T_641, 7, 0) @[CircuitMath.scala 36:17] + node _T_648 = neq(_T_645, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_649 = bits(_T_645, 7, 4) @[CircuitMath.scala 35:17] + node _T_650 = bits(_T_645, 3, 0) @[CircuitMath.scala 36:17] + node _T_652 = neq(_T_649, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_653 = bits(_T_649, 3, 3) @[CircuitMath.scala 32:12] + node _T_655 = bits(_T_649, 2, 2) @[CircuitMath.scala 32:12] + node _T_657 = bits(_T_649, 1, 1) @[CircuitMath.scala 30:8] + node _T_658 = mux(_T_655, UInt<2>("h02"), _T_657) @[CircuitMath.scala 32:10] + node _T_659 = mux(_T_653, UInt<2>("h03"), _T_658) @[CircuitMath.scala 32:10] + node _T_660 = bits(_T_650, 3, 3) @[CircuitMath.scala 32:12] + node _T_662 = bits(_T_650, 2, 2) @[CircuitMath.scala 32:12] + node _T_664 = bits(_T_650, 1, 1) @[CircuitMath.scala 30:8] + node _T_665 = mux(_T_662, UInt<2>("h02"), _T_664) @[CircuitMath.scala 32:10] + node _T_666 = mux(_T_660, UInt<2>("h03"), _T_665) @[CircuitMath.scala 32:10] + node _T_667 = mux(_T_652, _T_659, _T_666) @[CircuitMath.scala 38:21] + node _T_668 = cat(_T_652, _T_667) @[Cat.scala 30:58] + node _T_669 = bits(_T_646, 7, 4) @[CircuitMath.scala 35:17] + node _T_670 = bits(_T_646, 3, 0) @[CircuitMath.scala 36:17] + node _T_672 = neq(_T_669, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_673 = bits(_T_669, 3, 3) @[CircuitMath.scala 32:12] + node _T_675 = bits(_T_669, 2, 2) @[CircuitMath.scala 32:12] + node _T_677 = bits(_T_669, 1, 1) @[CircuitMath.scala 30:8] + node _T_678 = mux(_T_675, UInt<2>("h02"), _T_677) @[CircuitMath.scala 32:10] + node _T_679 = mux(_T_673, UInt<2>("h03"), _T_678) @[CircuitMath.scala 32:10] + node _T_680 = bits(_T_670, 3, 3) @[CircuitMath.scala 32:12] + node _T_682 = bits(_T_670, 2, 2) @[CircuitMath.scala 32:12] + node _T_684 = bits(_T_670, 1, 1) @[CircuitMath.scala 30:8] + node _T_685 = mux(_T_682, UInt<2>("h02"), _T_684) @[CircuitMath.scala 32:10] + node _T_686 = mux(_T_680, UInt<2>("h03"), _T_685) @[CircuitMath.scala 32:10] + node _T_687 = mux(_T_672, _T_679, _T_686) @[CircuitMath.scala 38:21] + node _T_688 = cat(_T_672, _T_687) @[Cat.scala 30:58] + node _T_689 = mux(_T_648, _T_668, _T_688) @[CircuitMath.scala 38:21] + node _T_690 = cat(_T_648, _T_689) @[Cat.scala 30:58] + node _T_691 = bits(_T_642, 15, 8) @[CircuitMath.scala 35:17] + node _T_692 = bits(_T_642, 7, 0) @[CircuitMath.scala 36:17] + node _T_694 = neq(_T_691, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_695 = bits(_T_691, 7, 4) @[CircuitMath.scala 35:17] + node _T_696 = bits(_T_691, 3, 0) @[CircuitMath.scala 36:17] + node _T_698 = neq(_T_695, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_699 = bits(_T_695, 3, 3) @[CircuitMath.scala 32:12] + node _T_701 = bits(_T_695, 2, 2) @[CircuitMath.scala 32:12] + node _T_703 = bits(_T_695, 1, 1) @[CircuitMath.scala 30:8] + node _T_704 = mux(_T_701, UInt<2>("h02"), _T_703) @[CircuitMath.scala 32:10] + node _T_705 = mux(_T_699, UInt<2>("h03"), _T_704) @[CircuitMath.scala 32:10] + node _T_706 = bits(_T_696, 3, 3) @[CircuitMath.scala 32:12] + node _T_708 = bits(_T_696, 2, 2) @[CircuitMath.scala 32:12] + node _T_710 = bits(_T_696, 1, 1) @[CircuitMath.scala 30:8] + node _T_711 = mux(_T_708, UInt<2>("h02"), _T_710) @[CircuitMath.scala 32:10] + node _T_712 = mux(_T_706, UInt<2>("h03"), _T_711) @[CircuitMath.scala 32:10] + node _T_713 = mux(_T_698, _T_705, _T_712) @[CircuitMath.scala 38:21] + node _T_714 = cat(_T_698, _T_713) @[Cat.scala 30:58] + node _T_715 = bits(_T_692, 7, 4) @[CircuitMath.scala 35:17] + node _T_716 = bits(_T_692, 3, 0) @[CircuitMath.scala 36:17] + node _T_718 = neq(_T_715, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_719 = bits(_T_715, 3, 3) @[CircuitMath.scala 32:12] + node _T_721 = bits(_T_715, 2, 2) @[CircuitMath.scala 32:12] + node _T_723 = bits(_T_715, 1, 1) @[CircuitMath.scala 30:8] + node _T_724 = mux(_T_721, UInt<2>("h02"), _T_723) @[CircuitMath.scala 32:10] + node _T_725 = mux(_T_719, UInt<2>("h03"), _T_724) @[CircuitMath.scala 32:10] + node _T_726 = bits(_T_716, 3, 3) @[CircuitMath.scala 32:12] + node _T_728 = bits(_T_716, 2, 2) @[CircuitMath.scala 32:12] + node _T_730 = bits(_T_716, 1, 1) @[CircuitMath.scala 30:8] + node _T_731 = mux(_T_728, UInt<2>("h02"), _T_730) @[CircuitMath.scala 32:10] + node _T_732 = mux(_T_726, UInt<2>("h03"), _T_731) @[CircuitMath.scala 32:10] + node _T_733 = mux(_T_718, _T_725, _T_732) @[CircuitMath.scala 38:21] + node _T_734 = cat(_T_718, _T_733) @[Cat.scala 30:58] + node _T_735 = mux(_T_694, _T_714, _T_734) @[CircuitMath.scala 38:21] + node _T_736 = cat(_T_694, _T_735) @[Cat.scala 30:58] + node _T_737 = mux(_T_644, _T_690, _T_736) @[CircuitMath.scala 38:21] + node _T_738 = cat(_T_644, _T_737) @[Cat.scala 30:58] + node _T_739 = mux(_T_542, _T_640, _T_738) @[CircuitMath.scala 38:21] + node _T_740 = cat(_T_542, _T_739) @[Cat.scala 30:58] + node _T_741 = not(_T_740) @[recFNFromFN.scala 56:13] + node _T_742 = dshl(_T_532, _T_741) @[recFNFromFN.scala 58:25] + node _T_743 = bits(_T_742, 50, 0) @[recFNFromFN.scala 58:37] + node _T_745 = cat(_T_743, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_750 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 71:12] + node _T_751 = xor(_T_741, _T_750) @[recFNFromFN.scala 62:27] + node _T_752 = mux(_T_534, _T_751, _T_531) @[recFNFromFN.scala 61:16] + node _T_756 = mux(_T_534, UInt<2>("h02"), UInt<1>("h01")) @[recFNFromFN.scala 64:47] + node _T_757 = or(UInt<11>("h0400"), _T_756) @[recFNFromFN.scala 64:42] + node _T_758 = add(_T_752, _T_757) @[recFNFromFN.scala 64:15] + node _T_759 = tail(_T_758, 1) @[recFNFromFN.scala 64:15] + node _T_760 = bits(_T_759, 11, 10) @[recFNFromFN.scala 67:25] + node _T_762 = eq(_T_760, UInt<2>("h03")) @[recFNFromFN.scala 67:50] + node _T_764 = eq(_T_536, UInt<1>("h00")) @[recFNFromFN.scala 68:17] + node _T_765 = and(_T_762, _T_764) @[recFNFromFN.scala 67:63] + node _T_766 = bits(_T_537, 0, 0) @[Bitwise.scala 71:15] + node _T_769 = mux(_T_766, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 71:12] + node _T_770 = shl(_T_769, 9) @[recFNFromFN.scala 71:45] + node _T_771 = not(_T_770) @[recFNFromFN.scala 71:28] + node _T_772 = and(_T_759, _T_771) @[recFNFromFN.scala 71:26] + node _T_773 = shl(_T_765, 9) @[recFNFromFN.scala 72:22] + node _T_774 = or(_T_772, _T_773) @[recFNFromFN.scala 71:64] + node _T_775 = mux(_T_534, _T_745, _T_532) @[recFNFromFN.scala 73:27] + node _T_776 = cat(_T_530, _T_774) @[Cat.scala 30:58] + node _T_777 = cat(_T_776, _T_775) @[Cat.scala 30:58] + node _T_779 = or(rec_s, UInt<65>("h0e004000000000000")) @[FPU.scala 543:33] + node load_wb_data_recoded = mux(load_wb_single, _T_779, _T_777) @[FPU.scala 543:10] + cmem regfile : UInt<65>[32] @[FPU.scala 547:20] + when load_wb : @[FPU.scala 548:18] + infer mport _T_782 = regfile[load_wb_tag], clock + _T_782 <= load_wb_data_recoded @[FPU.scala 549:26] + skip @[FPU.scala 548:18] + reg ex_ra1 : UInt, clock @[FPU.scala 554:53] + reg ex_ra2 : UInt, clock @[FPU.scala 554:53] + reg ex_ra3 : UInt, clock @[FPU.scala 554:53] + when io.valid : @[FPU.scala 555:19] + when fp_decoder.io.sigs.ren1 : @[FPU.scala 556:25] + node _T_787 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00")) @[FPU.scala 557:13] + when _T_787 : @[FPU.scala 557:30] + node _T_788 = bits(io.inst, 19, 15) @[FPU.scala 557:49] + ex_ra1 <= _T_788 @[FPU.scala 557:39] + skip @[FPU.scala 557:30] + when fp_decoder.io.sigs.swap12 : @[FPU.scala 558:29] + node _T_789 = bits(io.inst, 19, 15) @[FPU.scala 558:48] + ex_ra2 <= _T_789 @[FPU.scala 558:38] + skip @[FPU.scala 558:29] + skip @[FPU.scala 556:25] + when fp_decoder.io.sigs.ren2 : @[FPU.scala 560:25] + when fp_decoder.io.sigs.swap12 : @[FPU.scala 561:29] + node _T_790 = bits(io.inst, 24, 20) @[FPU.scala 561:48] + ex_ra1 <= _T_790 @[FPU.scala 561:38] + skip @[FPU.scala 561:29] + when fp_decoder.io.sigs.swap23 : @[FPU.scala 562:29] + node _T_791 = bits(io.inst, 24, 20) @[FPU.scala 562:48] + ex_ra3 <= _T_791 @[FPU.scala 562:38] + skip @[FPU.scala 562:29] + node _T_793 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00")) @[FPU.scala 563:13] + node _T_795 = eq(fp_decoder.io.sigs.swap23, UInt<1>("h00")) @[FPU.scala 563:32] + node _T_796 = and(_T_793, _T_795) @[FPU.scala 563:29] + when _T_796 : @[FPU.scala 563:49] + node _T_797 = bits(io.inst, 24, 20) @[FPU.scala 563:68] + ex_ra2 <= _T_797 @[FPU.scala 563:58] + skip @[FPU.scala 563:49] + skip @[FPU.scala 560:25] + when fp_decoder.io.sigs.ren3 : @[FPU.scala 565:25] + node _T_798 = bits(io.inst, 31, 27) @[FPU.scala 565:44] + ex_ra3 <= _T_798 @[FPU.scala 565:34] + skip @[FPU.scala 565:25] + skip @[FPU.scala 555:19] + node _T_799 = bits(ex_reg_inst, 14, 12) @[FPU.scala 567:30] + node _T_801 = eq(_T_799, UInt<3>("h07")) @[FPU.scala 567:38] + node _T_802 = bits(ex_reg_inst, 14, 12) @[FPU.scala 567:74] + node ex_rm = mux(_T_801, io.fcsr_rm, _T_802) @[FPU.scala 567:18] + wire req : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} @[FPU.scala 569:17] + req is invalid @[FPU.scala 569:17] + req <- ex_ctrl @[FPU.scala 570:7] + req.rm <= ex_rm @[FPU.scala 571:10] + node _T_847 = or(ex_ra1, UInt<5>("h00")) + node _T_848 = bits(_T_847, 4, 0) + infer mport _T_849 = regfile[_T_848], clock + req.in1 <= _T_849 @[FPU.scala 572:11] + node _T_851 = or(ex_ra2, UInt<5>("h00")) + node _T_852 = bits(_T_851, 4, 0) + infer mport _T_853 = regfile[_T_852], clock + req.in2 <= _T_853 @[FPU.scala 573:11] + node _T_855 = or(ex_ra3, UInt<5>("h00")) + node _T_856 = bits(_T_855, 4, 0) + infer mport _T_857 = regfile[_T_856], clock + req.in3 <= _T_857 @[FPU.scala 574:11] + node _T_858 = bits(ex_reg_inst, 21, 20) @[FPU.scala 575:25] + req.typ <= _T_858 @[FPU.scala 575:11] + when ex_cp_valid : @[FPU.scala 576:22] + req <- io.cp_req.bits @[FPU.scala 577:9] + when io.cp_req.bits.swap23 : @[FPU.scala 578:34] + req.in2 <= io.cp_req.bits.in3 @[FPU.scala 579:15] + req.in3 <= io.cp_req.bits.in2 @[FPU.scala 580:15] + skip @[FPU.scala 578:34] + skip @[FPU.scala 576:22] + inst sfma of FPUFMAPipe @[FPU.scala 584:20] + sfma.io is invalid + sfma.clock <= clock + sfma.reset <= reset + node _T_859 = and(req_valid, ex_ctrl.fma) @[FPU.scala 585:33] + node _T_860 = and(_T_859, ex_ctrl.single) @[FPU.scala 585:48] + sfma.io.in.valid <= _T_860 @[FPU.scala 585:20] + sfma.io.in.bits <- req @[FPU.scala 586:19] + inst fpiu of FPToInt @[FPU.scala 588:20] + fpiu.io is invalid + fpiu.clock <= clock + fpiu.reset <= reset + node _T_861 = or(ex_ctrl.toint, ex_ctrl.div) @[FPU.scala 589:51] + node _T_862 = or(_T_861, ex_ctrl.sqrt) @[FPU.scala 589:66] + node _T_865 = and(ex_ctrl.cmd, UInt<4>("h0d")) @[FPU.scala 589:97] + node _T_866 = eq(UInt<3>("h05"), _T_865) @[FPU.scala 589:97] + node _T_867 = or(_T_862, _T_866) @[FPU.scala 589:82] + node _T_868 = and(req_valid, _T_867) @[FPU.scala 589:33] + fpiu.io.in.valid <= _T_868 @[FPU.scala 589:20] + fpiu.io.in.bits <- req @[FPU.scala 590:19] + io.store_data <= fpiu.io.out.bits.store @[FPU.scala 591:17] + io.toint_data <= fpiu.io.out.bits.toint @[FPU.scala 592:17] + node _T_869 = and(fpiu.io.out.valid, mem_cp_valid) @[FPU.scala 593:26] + node _T_870 = and(_T_869, mem_ctrl.toint) @[FPU.scala 593:42] + when _T_870 : @[FPU.scala 593:60] + io.cp_resp.bits.data <= fpiu.io.out.bits.toint @[FPU.scala 594:26] + io.cp_resp.valid <= UInt<1>("h01") @[FPU.scala 595:22] + skip @[FPU.scala 593:60] + inst ifpu of IntToFP @[FPU.scala 598:20] + ifpu.io is invalid + ifpu.clock <= clock + ifpu.reset <= reset + node _T_872 = and(req_valid, ex_ctrl.fromint) @[FPU.scala 599:33] + ifpu.io.in.valid <= _T_872 @[FPU.scala 599:20] + ifpu.io.in.bits <- req @[FPU.scala 600:19] + node _T_873 = mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) @[FPU.scala 601:29] + ifpu.io.in.bits.in1 <= _T_873 @[FPU.scala 601:23] + inst fpmu of FPToFP @[FPU.scala 603:20] + fpmu.io is invalid + fpmu.clock <= clock + fpmu.reset <= reset + node _T_874 = and(req_valid, ex_ctrl.fastpipe) @[FPU.scala 604:33] + fpmu.io.in.valid <= _T_874 @[FPU.scala 604:20] + fpmu.io.in.bits <- req @[FPU.scala 605:19] + fpmu.io.lt <= fpiu.io.out.bits.lt @[FPU.scala 606:14] + reg divSqrt_wen : UInt<1>, clock @[FPU.scala 608:24] + divSqrt_wen <= UInt<1>("h00") @[FPU.scala 608:24] + wire divSqrt_inReady : UInt<1> + divSqrt_inReady is invalid + divSqrt_inReady <= UInt<1>("h00") + reg divSqrt_waddr : UInt<5>, clock @[FPU.scala 610:26] + reg divSqrt_single : UInt<1>, clock @[FPU.scala 611:27] + wire divSqrt_wdata : UInt<65> @[FPU.scala 612:27] + divSqrt_wdata is invalid @[FPU.scala 612:27] + wire divSqrt_flags : UInt<5> @[FPU.scala 613:27] + divSqrt_flags is invalid @[FPU.scala 613:27] + reg divSqrt_in_flight : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[FPU.scala 614:30] + reg divSqrt_killed : UInt<1>, clock @[FPU.scala 615:27] + inst FPUFMAPipe of FPUFMAPipe_1 @[FPU.scala 624:28] + FPUFMAPipe.io is invalid + FPUFMAPipe.clock <= clock + FPUFMAPipe.reset <= reset + node _T_883 = and(req_valid, ex_ctrl.fma) @[FPU.scala 625:41] + node _T_885 = eq(ex_ctrl.single, UInt<1>("h00")) @[FPU.scala 625:59] + node _T_886 = and(_T_883, _T_885) @[FPU.scala 625:56] + FPUFMAPipe.io.in.valid <= _T_886 @[FPU.scala 625:28] + FPUFMAPipe.io.in.bits <- req @[FPU.scala 626:27] + node _T_889 = mux(mem_ctrl.fastpipe, UInt<1>("h01"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_892 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_893 = and(mem_ctrl.fma, mem_ctrl.single) @[FPU.scala 622:56] + node _T_896 = mux(_T_893, UInt<2>("h02"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_898 = eq(mem_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65] + node _T_899 = and(mem_ctrl.fma, _T_898) @[FPU.scala 627:62] + node _T_902 = mux(_T_899, UInt<3>("h04"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_903 = or(_T_889, _T_892) @[FPU.scala 631:78] + node _T_904 = or(_T_903, _T_896) @[FPU.scala 631:78] + node memLatencyMask = or(_T_904, _T_902) @[FPU.scala 631:78] + reg wen : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[FPU.scala 645:16] + reg wbInfo : {rd : UInt<5>, single : UInt<1>, cp : UInt<1>, pipeid : UInt<2>}[3], clock @[FPU.scala 646:19] + node _T_966 = or(mem_ctrl.fma, mem_ctrl.fastpipe) @[FPU.scala 647:48] + node _T_967 = or(_T_966, mem_ctrl.fromint) @[FPU.scala 647:69] + node mem_wen = and(mem_reg_valid, _T_967) @[FPU.scala 647:31] + node _T_970 = mux(ex_ctrl.fastpipe, UInt<2>("h02"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_973 = mux(ex_ctrl.fromint, UInt<2>("h02"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_974 = and(ex_ctrl.fma, ex_ctrl.single) @[FPU.scala 622:56] + node _T_977 = mux(_T_974, UInt<3>("h04"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_979 = eq(ex_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65] + node _T_980 = and(ex_ctrl.fma, _T_979) @[FPU.scala 627:62] + node _T_983 = mux(_T_980, UInt<4>("h08"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_984 = or(_T_970, _T_973) @[FPU.scala 631:78] + node _T_985 = or(_T_984, _T_977) @[FPU.scala 631:78] + node _T_986 = or(_T_985, _T_983) @[FPU.scala 631:78] + node _T_987 = and(memLatencyMask, _T_986) @[FPU.scala 648:62] + node _T_989 = neq(_T_987, UInt<1>("h00")) @[FPU.scala 648:89] + node _T_990 = and(mem_wen, _T_989) @[FPU.scala 648:43] + node _T_993 = mux(ex_ctrl.fastpipe, UInt<3>("h04"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_996 = mux(ex_ctrl.fromint, UInt<3>("h04"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_997 = and(ex_ctrl.fma, ex_ctrl.single) @[FPU.scala 622:56] + node _T_1000 = mux(_T_997, UInt<4>("h08"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_1002 = eq(ex_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65] + node _T_1003 = and(ex_ctrl.fma, _T_1002) @[FPU.scala 627:62] + node _T_1006 = mux(_T_1003, UInt<5>("h010"), UInt<1>("h00")) @[FPU.scala 631:23] + node _T_1007 = or(_T_993, _T_996) @[FPU.scala 631:78] + node _T_1008 = or(_T_1007, _T_1000) @[FPU.scala 631:78] + node _T_1009 = or(_T_1008, _T_1006) @[FPU.scala 631:78] + node _T_1010 = and(wen, _T_1009) @[FPU.scala 648:101] + node _T_1012 = neq(_T_1010, UInt<1>("h00")) @[FPU.scala 648:128] + node _T_1013 = or(_T_990, _T_1012) @[FPU.scala 648:93] + reg write_port_busy : UInt<1>, clock @[Reg.scala 34:16] + when req_valid : @[Reg.scala 35:19] + write_port_busy <= _T_1013 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_1015 = bits(wen, 1, 1) @[FPU.scala 651:14] + when _T_1015 : @[FPU.scala 651:21] + wbInfo[0] <- wbInfo[1] @[FPU.scala 651:33] + skip @[FPU.scala 651:21] + node _T_1016 = bits(wen, 2, 2) @[FPU.scala 651:14] + when _T_1016 : @[FPU.scala 651:21] + wbInfo[1] <- wbInfo[2] @[FPU.scala 651:33] + skip @[FPU.scala 651:21] + node _T_1017 = shr(wen, 1) @[FPU.scala 653:14] + wen <= _T_1017 @[FPU.scala 653:7] + when mem_wen : @[FPU.scala 654:18] + node _T_1019 = eq(killm, UInt<1>("h00")) @[FPU.scala 655:11] + when _T_1019 : @[FPU.scala 655:19] + node _T_1020 = shr(wen, 1) @[FPU.scala 656:18] + node _T_1021 = or(_T_1020, memLatencyMask) @[FPU.scala 656:23] + wen <= _T_1021 @[FPU.scala 656:11] + skip @[FPU.scala 655:19] + node _T_1023 = eq(write_port_busy, UInt<1>("h00")) @[FPU.scala 659:13] + node _T_1024 = bits(memLatencyMask, 0, 0) @[FPU.scala 659:47] + node _T_1025 = and(_T_1023, _T_1024) @[FPU.scala 659:30] + when _T_1025 : @[FPU.scala 659:52] + wbInfo[0].cp <= mem_cp_valid @[FPU.scala 660:22] + wbInfo[0].single <= mem_ctrl.single @[FPU.scala 661:26] + node _T_1028 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1031 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1032 = and(mem_ctrl.fma, mem_ctrl.single) @[FPU.scala 622:56] + node _T_1035 = mux(_T_1032, UInt<2>("h02"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1037 = eq(mem_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65] + node _T_1038 = and(mem_ctrl.fma, _T_1037) @[FPU.scala 627:62] + node _T_1041 = mux(_T_1038, UInt<2>("h03"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1042 = or(_T_1028, _T_1031) @[FPU.scala 633:108] + node _T_1043 = or(_T_1042, _T_1035) @[FPU.scala 633:108] + node _T_1044 = or(_T_1043, _T_1041) @[FPU.scala 633:108] + wbInfo[0].pipeid <= _T_1044 @[FPU.scala 662:26] + node _T_1045 = bits(mem_reg_inst, 11, 7) @[FPU.scala 663:37] + wbInfo[0].rd <= _T_1045 @[FPU.scala 663:22] + skip @[FPU.scala 659:52] + node _T_1047 = eq(write_port_busy, UInt<1>("h00")) @[FPU.scala 659:13] + node _T_1048 = bits(memLatencyMask, 1, 1) @[FPU.scala 659:47] + node _T_1049 = and(_T_1047, _T_1048) @[FPU.scala 659:30] + when _T_1049 : @[FPU.scala 659:52] + wbInfo[1].cp <= mem_cp_valid @[FPU.scala 660:22] + wbInfo[1].single <= mem_ctrl.single @[FPU.scala 661:26] + node _T_1052 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1055 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1056 = and(mem_ctrl.fma, mem_ctrl.single) @[FPU.scala 622:56] + node _T_1059 = mux(_T_1056, UInt<2>("h02"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1061 = eq(mem_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65] + node _T_1062 = and(mem_ctrl.fma, _T_1061) @[FPU.scala 627:62] + node _T_1065 = mux(_T_1062, UInt<2>("h03"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1066 = or(_T_1052, _T_1055) @[FPU.scala 633:108] + node _T_1067 = or(_T_1066, _T_1059) @[FPU.scala 633:108] + node _T_1068 = or(_T_1067, _T_1065) @[FPU.scala 633:108] + wbInfo[1].pipeid <= _T_1068 @[FPU.scala 662:26] + node _T_1069 = bits(mem_reg_inst, 11, 7) @[FPU.scala 663:37] + wbInfo[1].rd <= _T_1069 @[FPU.scala 663:22] + skip @[FPU.scala 659:52] + node _T_1071 = eq(write_port_busy, UInt<1>("h00")) @[FPU.scala 659:13] + node _T_1072 = bits(memLatencyMask, 2, 2) @[FPU.scala 659:47] + node _T_1073 = and(_T_1071, _T_1072) @[FPU.scala 659:30] + when _T_1073 : @[FPU.scala 659:52] + wbInfo[2].cp <= mem_cp_valid @[FPU.scala 660:22] + wbInfo[2].single <= mem_ctrl.single @[FPU.scala 661:26] + node _T_1076 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1079 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1080 = and(mem_ctrl.fma, mem_ctrl.single) @[FPU.scala 622:56] + node _T_1083 = mux(_T_1080, UInt<2>("h02"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1085 = eq(mem_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65] + node _T_1086 = and(mem_ctrl.fma, _T_1085) @[FPU.scala 627:62] + node _T_1089 = mux(_T_1086, UInt<2>("h03"), UInt<1>("h00")) @[FPU.scala 633:63] + node _T_1090 = or(_T_1076, _T_1079) @[FPU.scala 633:108] + node _T_1091 = or(_T_1090, _T_1083) @[FPU.scala 633:108] + node _T_1092 = or(_T_1091, _T_1089) @[FPU.scala 633:108] + wbInfo[2].pipeid <= _T_1092 @[FPU.scala 662:26] + node _T_1093 = bits(mem_reg_inst, 11, 7) @[FPU.scala 663:37] + wbInfo[2].rd <= _T_1093 @[FPU.scala 663:22] + skip @[FPU.scala 659:52] + skip @[FPU.scala 654:18] + node waddr = mux(divSqrt_wen, divSqrt_waddr, wbInfo[0].rd) @[FPU.scala 668:18] + node _T_1095 = and(wbInfo[0].pipeid, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1097 = geq(wbInfo[0].pipeid, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1099 = and(_T_1095, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1101 = geq(_T_1095, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1102 = mux(_T_1101, FPUFMAPipe.io.out.bits.data, sfma.io.out.bits.data) @[Package.scala 19:12] + node _T_1104 = and(_T_1095, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1106 = geq(_T_1095, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1107 = mux(_T_1106, ifpu.io.out.bits.data, fpmu.io.out.bits.data) @[Package.scala 19:12] + node _T_1108 = mux(_T_1097, _T_1102, _T_1107) @[Package.scala 19:12] + node wdata0 = mux(divSqrt_wen, divSqrt_wdata, _T_1108) @[FPU.scala 669:19] + node wsingle = mux(divSqrt_wen, divSqrt_single, wbInfo[0].single) @[FPU.scala 670:20] + node _T_1109 = bits(wdata0, 32, 0) @[FPU.scala 673:36] + node _T_1111 = or(_T_1109, UInt<65>("h0e004000000000000")) @[FPU.scala 673:44] + node wdata = mux(wsingle, _T_1111, wdata0) @[FPU.scala 673:19] + node _T_1113 = and(wbInfo[0].pipeid, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1115 = geq(wbInfo[0].pipeid, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1117 = and(_T_1113, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1119 = geq(_T_1113, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1120 = mux(_T_1119, FPUFMAPipe.io.out.bits.exc, sfma.io.out.bits.exc) @[Package.scala 19:12] + node _T_1122 = and(_T_1113, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1124 = geq(_T_1113, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1125 = mux(_T_1124, ifpu.io.out.bits.exc, fpmu.io.out.bits.exc) @[Package.scala 19:12] + node wexc = mux(_T_1115, _T_1120, _T_1125) @[Package.scala 19:12] + node _T_1127 = eq(wbInfo[0].cp, UInt<1>("h00")) @[FPU.scala 676:10] + node _T_1128 = bits(wen, 0, 0) @[FPU.scala 676:30] + node _T_1129 = and(_T_1127, _T_1128) @[FPU.scala 676:24] + node _T_1130 = or(_T_1129, divSqrt_wen) @[FPU.scala 676:35] + when _T_1130 : @[FPU.scala 676:51] + infer mport _T_1131 = regfile[waddr], clock + _T_1131 <= wdata @[FPU.scala 677:20] + skip @[FPU.scala 676:51] + node _T_1132 = bits(wen, 0, 0) @[FPU.scala 689:28] + node _T_1133 = and(wbInfo[0].cp, _T_1132) @[FPU.scala 689:22] + when _T_1133 : @[FPU.scala 689:33] + io.cp_resp.bits.data <= wdata @[FPU.scala 690:26] + io.cp_resp.valid <= UInt<1>("h01") @[FPU.scala 691:22] + skip @[FPU.scala 689:33] + node _T_1136 = eq(ex_reg_valid, UInt<1>("h00")) @[FPU.scala 693:22] + io.cp_req.ready <= _T_1136 @[FPU.scala 693:19] + node wb_toint_valid = and(wb_reg_valid, wb_ctrl.toint) @[FPU.scala 695:37] + reg wb_toint_exc : UInt<5>, clock @[Reg.scala 34:16] + when mem_ctrl.toint : @[Reg.scala 35:19] + wb_toint_exc <= fpiu.io.out.bits.exc @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_1138 = or(wb_toint_valid, divSqrt_wen) @[FPU.scala 697:41] + node _T_1139 = bits(wen, 0, 0) @[FPU.scala 697:62] + node _T_1140 = or(_T_1138, _T_1139) @[FPU.scala 697:56] + io.fcsr_flags.valid <= _T_1140 @[FPU.scala 697:23] + node _T_1142 = mux(wb_toint_valid, wb_toint_exc, UInt<1>("h00")) @[FPU.scala 699:8] + node _T_1144 = mux(divSqrt_wen, divSqrt_flags, UInt<1>("h00")) @[FPU.scala 700:8] + node _T_1145 = or(_T_1142, _T_1144) @[FPU.scala 699:48] + node _T_1146 = bits(wen, 0, 0) @[FPU.scala 701:12] + node _T_1148 = mux(_T_1146, wexc, UInt<1>("h00")) @[FPU.scala 701:8] + node _T_1149 = or(_T_1145, _T_1148) @[FPU.scala 700:46] + io.fcsr_flags.bits <= _T_1149 @[FPU.scala 698:22] + node _T_1150 = or(mem_ctrl.div, mem_ctrl.sqrt) @[FPU.scala 703:51] + node _T_1151 = and(mem_reg_valid, _T_1150) @[FPU.scala 703:34] + node _T_1153 = eq(divSqrt_inReady, UInt<1>("h00")) @[FPU.scala 703:73] + node _T_1155 = neq(wen, UInt<1>("h00")) @[FPU.scala 703:97] + node _T_1156 = or(_T_1153, _T_1155) @[FPU.scala 703:90] + node units_busy = and(_T_1151, _T_1156) @[FPU.scala 703:69] + node _T_1157 = and(ex_reg_valid, ex_ctrl.wflags) @[FPU.scala 704:33] + node _T_1158 = and(mem_reg_valid, mem_ctrl.wflags) @[FPU.scala 704:68] + node _T_1159 = or(_T_1157, _T_1158) @[FPU.scala 704:51] + node _T_1160 = and(wb_reg_valid, wb_ctrl.toint) @[FPU.scala 704:103] + node _T_1161 = or(_T_1159, _T_1160) @[FPU.scala 704:87] + node _T_1163 = neq(wen, UInt<1>("h00")) @[FPU.scala 704:127] + node _T_1164 = or(_T_1161, _T_1163) @[FPU.scala 704:120] + node _T_1165 = or(_T_1164, divSqrt_in_flight) @[FPU.scala 704:131] + node _T_1167 = eq(_T_1165, UInt<1>("h00")) @[FPU.scala 704:18] + io.fcsr_rdy <= _T_1167 @[FPU.scala 704:15] + node _T_1168 = or(units_busy, write_port_busy) @[FPU.scala 705:29] + node _T_1169 = or(_T_1168, divSqrt_in_flight) @[FPU.scala 705:48] + io.nack_mem <= _T_1169 @[FPU.scala 705:15] + io.dec <- fp_decoder.io.sigs @[FPU.scala 706:10] + node _T_1171 = eq(wb_cp_valid, UInt<1>("h00")) @[FPU.scala 708:36] + node _T_1172 = and(wb_reg_valid, _T_1171) @[FPU.scala 708:33] + node _T_1174 = eq(mem_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65] + node _T_1175 = and(mem_ctrl.fma, _T_1174) @[FPU.scala 627:62] + node _T_1177 = or(UInt<1>("h00"), _T_1175) @[FPU.scala 707:123] + node _T_1178 = or(_T_1177, mem_ctrl.div) @[FPU.scala 708:96] + node _T_1179 = or(_T_1178, mem_ctrl.sqrt) @[FPU.scala 708:112] + reg _T_1180 : UInt<1>, clock @[FPU.scala 708:55] + _T_1180 <= _T_1179 @[FPU.scala 708:55] + node _T_1181 = and(_T_1172, _T_1180) @[FPU.scala 708:49] + io.sboard_set <= _T_1181 @[FPU.scala 708:17] + node _T_1183 = eq(wb_cp_valid, UInt<1>("h00")) @[FPU.scala 709:20] + node _T_1184 = bits(wen, 0, 0) @[FPU.scala 709:56] + node _T_1186 = eq(wbInfo[0].pipeid, UInt<2>("h03")) @[FPU.scala 709:99] + node _T_1188 = or(UInt<1>("h00"), _T_1186) @[FPU.scala 707:123] + node _T_1189 = and(_T_1184, _T_1188) @[FPU.scala 709:60] + node _T_1190 = or(divSqrt_wen, _T_1189) @[FPU.scala 709:49] + node _T_1191 = and(_T_1183, _T_1190) @[FPU.scala 709:33] + io.sboard_clr <= _T_1191 @[FPU.scala 709:17] + io.sboard_clra <= waddr @[FPU.scala 710:18] + node _T_1192 = bits(io.inst, 14, 14) @[FPU.scala 712:27] + node _T_1193 = bits(io.inst, 13, 12) @[FPU.scala 712:43] + node _T_1195 = lt(_T_1193, UInt<2>("h03")) @[FPU.scala 712:51] + node _T_1197 = geq(io.fcsr_rm, UInt<3>("h04")) @[FPU.scala 712:69] + node _T_1198 = or(_T_1195, _T_1197) @[FPU.scala 712:55] + node _T_1199 = and(_T_1192, _T_1198) @[FPU.scala 712:32] + io.illegal_rm <= _T_1199 @[FPU.scala 712:17] + divSqrt_wdata <= UInt<1>("h00") @[FPU.scala 714:17] + divSqrt_flags <= UInt<1>("h00") @[FPU.scala 715:17] + reg _T_1203 : UInt, clock @[FPU.scala 718:25] + reg _T_1205 : UInt, clock @[FPU.scala 719:35] + reg _T_1207 : UInt, clock @[FPU.scala 720:35] + inst DivSqrtRecF64 of DivSqrtRecF64 @[FPU.scala 722:25] + DivSqrtRecF64.io is invalid + DivSqrtRecF64.clock <= clock + DivSqrtRecF64.reset <= reset + node _T_1208 = mux(DivSqrtRecF64.io.sqrtOp, DivSqrtRecF64.io.inReady_sqrt, DivSqrtRecF64.io.inReady_div) @[FPU.scala 723:27] + divSqrt_inReady <= _T_1208 @[FPU.scala 723:21] + node _T_1209 = or(DivSqrtRecF64.io.outValid_div, DivSqrtRecF64.io.outValid_sqrt) @[FPU.scala 724:52] + node _T_1210 = or(mem_ctrl.div, mem_ctrl.sqrt) @[FPU.scala 725:58] + node _T_1211 = and(mem_reg_valid, _T_1210) @[FPU.scala 725:41] + node _T_1213 = eq(divSqrt_in_flight, UInt<1>("h00")) @[FPU.scala 725:79] + node _T_1214 = and(_T_1211, _T_1213) @[FPU.scala 725:76] + DivSqrtRecF64.io.inValid <= _T_1214 @[FPU.scala 725:24] + DivSqrtRecF64.io.sqrtOp <= mem_ctrl.sqrt @[FPU.scala 726:23] + DivSqrtRecF64.io.a <= fpiu.io.as_double.in1 @[FPU.scala 727:18] + DivSqrtRecF64.io.b <= fpiu.io.as_double.in2 @[FPU.scala 728:18] + DivSqrtRecF64.io.roundingMode <= fpiu.io.as_double.rm @[FPU.scala 729:29] + node _T_1215 = and(DivSqrtRecF64.io.inValid, divSqrt_inReady) @[FPU.scala 731:30] + when _T_1215 : @[FPU.scala 731:50] + divSqrt_in_flight <= UInt<1>("h01") @[FPU.scala 732:25] + divSqrt_killed <= killm @[FPU.scala 733:22] + divSqrt_single <= mem_ctrl.single @[FPU.scala 734:22] + node _T_1217 = bits(mem_reg_inst, 11, 7) @[FPU.scala 735:36] + divSqrt_waddr <= _T_1217 @[FPU.scala 735:21] + _T_1203 <= DivSqrtRecF64.io.roundingMode @[FPU.scala 736:18] + skip @[FPU.scala 731:50] + when _T_1209 : @[FPU.scala 739:29] + node _T_1219 = eq(divSqrt_killed, UInt<1>("h00")) @[FPU.scala 740:22] + divSqrt_wen <= _T_1219 @[FPU.scala 740:19] + _T_1207 <= DivSqrtRecF64.io.out @[FPU.scala 741:28] + divSqrt_in_flight <= UInt<1>("h00") @[FPU.scala 742:25] + _T_1205 <= DivSqrtRecF64.io.exceptionFlags @[FPU.scala 743:28] + skip @[FPU.scala 739:29] + inst RecFNToRecFN of RecFNToRecFN_2 @[FPU.scala 746:34] + RecFNToRecFN.io is invalid + RecFNToRecFN.clock <= clock + RecFNToRecFN.reset <= reset + RecFNToRecFN.io.in <= _T_1207 @[FPU.scala 747:28] + RecFNToRecFN.io.roundingMode <= _T_1203 @[FPU.scala 748:38] + node _T_1221 = mux(divSqrt_single, RecFNToRecFN.io.out, _T_1207) @[FPU.scala 749:25] + divSqrt_wdata <= _T_1221 @[FPU.scala 749:19] + node _T_1223 = mux(divSqrt_single, RecFNToRecFN.io.exceptionFlags, UInt<1>("h00")) @[FPU.scala 750:48] + node _T_1224 = or(_T_1205, _T_1223) @[FPU.scala 750:43] + divSqrt_flags <= _T_1224 @[FPU.scala 750:19] + + module FPUDecoder : + input clock : Clock + input reset : UInt<1> + output io : {flip inst : UInt<32>, sigs : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>}} + + io is invalid + io is invalid + node _T_22 = and(io.inst, UInt<32>("h04")) @[Decode.scala 13:65] + node _T_24 = eq(_T_22, UInt<32>("h04")) @[Decode.scala 13:121] + node _T_26 = and(io.inst, UInt<32>("h08000010")) @[Decode.scala 13:65] + node _T_28 = eq(_T_26, UInt<32>("h08000010")) @[Decode.scala 13:121] + node _T_30 = or(UInt<1>("h00"), _T_24) @[Decode.scala 14:30] + node _T_31 = or(_T_30, _T_28) @[Decode.scala 14:30] + node _T_33 = and(io.inst, UInt<32>("h08")) @[Decode.scala 13:65] + node _T_35 = eq(_T_33, UInt<32>("h08")) @[Decode.scala 13:121] + node _T_37 = and(io.inst, UInt<32>("h010000010")) @[Decode.scala 13:65] + node _T_39 = eq(_T_37, UInt<32>("h010000010")) @[Decode.scala 13:121] + node _T_41 = or(UInt<1>("h00"), _T_35) @[Decode.scala 14:30] + node _T_42 = or(_T_41, _T_39) @[Decode.scala 14:30] + node _T_44 = and(io.inst, UInt<32>("h040")) @[Decode.scala 13:65] + node _T_46 = eq(_T_44, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_48 = and(io.inst, UInt<32>("h020000000")) @[Decode.scala 13:65] + node _T_50 = eq(_T_48, UInt<32>("h020000000")) @[Decode.scala 13:121] + node _T_52 = or(UInt<1>("h00"), _T_46) @[Decode.scala 14:30] + node _T_53 = or(_T_52, _T_50) @[Decode.scala 14:30] + node _T_55 = and(io.inst, UInt<32>("h040000000")) @[Decode.scala 13:65] + node _T_57 = eq(_T_55, UInt<32>("h040000000")) @[Decode.scala 13:121] + node _T_59 = or(UInt<1>("h00"), _T_46) @[Decode.scala 14:30] + node _T_60 = or(_T_59, _T_57) @[Decode.scala 14:30] + node _T_62 = and(io.inst, UInt<32>("h010")) @[Decode.scala 13:65] + node _T_64 = eq(_T_62, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_66 = or(UInt<1>("h00"), _T_64) @[Decode.scala 14:30] + node _T_67 = cat(_T_42, _T_31) @[Cat.scala 30:58] + node _T_68 = cat(_T_66, _T_60) @[Cat.scala 30:58] + node _T_69 = cat(_T_68, _T_53) @[Cat.scala 30:58] + node decoder_0 = cat(_T_69, _T_67) @[Cat.scala 30:58] + node decoder_1 = or(UInt<1>("h00"), _T_46) @[Decode.scala 14:30] + node _T_72 = and(io.inst, UInt<32>("h080000020")) @[Decode.scala 13:65] + node _T_74 = eq(_T_72, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_76 = and(io.inst, UInt<32>("h030")) @[Decode.scala 13:65] + node _T_78 = eq(_T_76, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_80 = and(io.inst, UInt<32>("h010000020")) @[Decode.scala 13:65] + node _T_82 = eq(_T_80, UInt<32>("h010000000")) @[Decode.scala 13:121] + node _T_84 = or(UInt<1>("h00"), _T_74) @[Decode.scala 14:30] + node _T_85 = or(_T_84, _T_78) @[Decode.scala 14:30] + node decoder_2 = or(_T_85, _T_82) @[Decode.scala 14:30] + node _T_87 = and(io.inst, UInt<32>("h080000004")) @[Decode.scala 13:65] + node _T_89 = eq(_T_87, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_91 = and(io.inst, UInt<32>("h010000004")) @[Decode.scala 13:65] + node _T_93 = eq(_T_91, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_95 = and(io.inst, UInt<32>("h050")) @[Decode.scala 13:65] + node _T_97 = eq(_T_95, UInt<32>("h040")) @[Decode.scala 13:121] + node _T_99 = or(UInt<1>("h00"), _T_89) @[Decode.scala 14:30] + node _T_100 = or(_T_99, _T_93) @[Decode.scala 14:30] + node decoder_3 = or(_T_100, _T_97) @[Decode.scala 14:30] + node _T_102 = and(io.inst, UInt<32>("h040000004")) @[Decode.scala 13:65] + node _T_104 = eq(_T_102, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_106 = and(io.inst, UInt<32>("h020")) @[Decode.scala 13:65] + node _T_108 = eq(_T_106, UInt<32>("h020")) @[Decode.scala 13:121] + node _T_110 = or(UInt<1>("h00"), _T_104) @[Decode.scala 14:30] + node _T_111 = or(_T_110, _T_108) @[Decode.scala 14:30] + node decoder_4 = or(_T_111, _T_97) @[Decode.scala 14:30] + node decoder_5 = or(UInt<1>("h00"), _T_97) @[Decode.scala 14:30] + node _T_114 = and(io.inst, UInt<32>("h050000010")) @[Decode.scala 13:65] + node _T_116 = eq(_T_114, UInt<32>("h050000010")) @[Decode.scala 13:121] + node _T_118 = or(UInt<1>("h00"), _T_46) @[Decode.scala 14:30] + node decoder_6 = or(_T_118, _T_116) @[Decode.scala 14:30] + node _T_120 = and(io.inst, UInt<32>("h030000010")) @[Decode.scala 13:65] + node _T_122 = eq(_T_120, UInt<32>("h010")) @[Decode.scala 13:121] + node decoder_7 = or(UInt<1>("h00"), _T_122) @[Decode.scala 14:30] + node _T_125 = and(io.inst, UInt<32>("h01040")) @[Decode.scala 13:65] + node _T_127 = eq(_T_125, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_129 = and(io.inst, UInt<32>("h02000040")) @[Decode.scala 13:65] + node _T_131 = eq(_T_129, UInt<32>("h040")) @[Decode.scala 13:121] + node _T_133 = or(UInt<1>("h00"), _T_127) @[Decode.scala 14:30] + node decoder_8 = or(_T_133, _T_131) @[Decode.scala 14:30] + node _T_135 = and(io.inst, UInt<32>("h090000010")) @[Decode.scala 13:65] + node _T_137 = eq(_T_135, UInt<32>("h090000010")) @[Decode.scala 13:121] + node decoder_9 = or(UInt<1>("h00"), _T_137) @[Decode.scala 14:30] + node _T_140 = and(io.inst, UInt<32>("h090000010")) @[Decode.scala 13:65] + node _T_142 = eq(_T_140, UInt<32>("h080000010")) @[Decode.scala 13:121] + node _T_144 = or(UInt<1>("h00"), _T_108) @[Decode.scala 14:30] + node decoder_10 = or(_T_144, _T_142) @[Decode.scala 14:30] + node _T_146 = and(io.inst, UInt<32>("h0a0000010")) @[Decode.scala 13:65] + node _T_148 = eq(_T_146, UInt<32>("h020000010")) @[Decode.scala 13:121] + node _T_150 = and(io.inst, UInt<32>("h0d0000010")) @[Decode.scala 13:65] + node _T_152 = eq(_T_150, UInt<32>("h040000010")) @[Decode.scala 13:121] + node _T_154 = or(UInt<1>("h00"), _T_148) @[Decode.scala 14:30] + node decoder_11 = or(_T_154, _T_152) @[Decode.scala 14:30] + node _T_156 = and(io.inst, UInt<32>("h070000004")) @[Decode.scala 13:65] + node _T_158 = eq(_T_156, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_160 = and(io.inst, UInt<32>("h068000004")) @[Decode.scala 13:65] + node _T_162 = eq(_T_160, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_164 = or(UInt<1>("h00"), _T_158) @[Decode.scala 14:30] + node _T_165 = or(_T_164, _T_162) @[Decode.scala 14:30] + node decoder_12 = or(_T_165, _T_97) @[Decode.scala 14:30] + node _T_167 = and(io.inst, UInt<32>("h058000010")) @[Decode.scala 13:65] + node _T_169 = eq(_T_167, UInt<32>("h018000010")) @[Decode.scala 13:121] + node decoder_13 = or(UInt<1>("h00"), _T_169) @[Decode.scala 14:30] + node _T_172 = and(io.inst, UInt<32>("h0d0000010")) @[Decode.scala 13:65] + node _T_174 = eq(_T_172, UInt<32>("h050000010")) @[Decode.scala 13:121] + node decoder_14 = or(UInt<1>("h00"), _T_174) @[Decode.scala 14:30] + node _T_177 = and(io.inst, UInt<32>("h020000004")) @[Decode.scala 13:65] + node _T_179 = eq(_T_177, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_181 = and(io.inst, UInt<32>("h08002000")) @[Decode.scala 13:65] + node _T_183 = eq(_T_181, UInt<32>("h08000000")) @[Decode.scala 13:121] + node _T_185 = and(io.inst, UInt<32>("h0c0000004")) @[Decode.scala 13:65] + node _T_187 = eq(_T_185, UInt<32>("h080000000")) @[Decode.scala 13:121] + node _T_189 = or(UInt<1>("h00"), _T_179) @[Decode.scala 14:30] + node _T_190 = or(_T_189, _T_97) @[Decode.scala 14:30] + node _T_191 = or(_T_190, _T_183) @[Decode.scala 14:30] + node decoder_15 = or(_T_191, _T_187) @[Decode.scala 14:30] + io.sigs.cmd <= decoder_0 @[FPU.scala 149:40] + io.sigs.ldst <= decoder_1 @[FPU.scala 149:40] + io.sigs.wen <= decoder_2 @[FPU.scala 149:40] + io.sigs.ren1 <= decoder_3 @[FPU.scala 149:40] + io.sigs.ren2 <= decoder_4 @[FPU.scala 149:40] + io.sigs.ren3 <= decoder_5 @[FPU.scala 149:40] + io.sigs.swap12 <= decoder_6 @[FPU.scala 149:40] + io.sigs.swap23 <= decoder_7 @[FPU.scala 149:40] + io.sigs.single <= decoder_8 @[FPU.scala 149:40] + io.sigs.fromint <= decoder_9 @[FPU.scala 149:40] + io.sigs.toint <= decoder_10 @[FPU.scala 149:40] + io.sigs.fastpipe <= decoder_11 @[FPU.scala 149:40] + io.sigs.fma <= decoder_12 @[FPU.scala 149:40] + io.sigs.div <= decoder_13 @[FPU.scala 149:40] + io.sigs.sqrt <= decoder_14 @[FPU.scala 149:40] + io.sigs.wflags <= decoder_15 @[FPU.scala 149:40] + + module FPUFMAPipe : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} + + io is invalid + io is invalid + node one = shl(UInt<1>("h01"), 31) @[FPU.scala 479:21] + node _T_131 = bits(io.in.bits.in1, 32, 32) @[FPU.scala 480:29] + node _T_132 = bits(io.in.bits.in2, 32, 32) @[FPU.scala 480:53] + node _T_133 = xor(_T_131, _T_132) @[FPU.scala 480:37] + node zero = shl(_T_133, 32) @[FPU.scala 480:62] + reg valid : UInt<1>, clock @[FPU.scala 482:18] + valid <= io.in.valid @[FPU.scala 482:18] + reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock @[FPU.scala 483:15] + when io.in.valid : @[FPU.scala 484:22] + in <- io.in.bits @[FPU.scala 485:8] + node _T_177 = bits(io.in.bits.cmd, 1, 1) @[FPU.scala 488:33] + node _T_178 = or(io.in.bits.ren3, io.in.bits.swap23) @[FPU.scala 488:48] + node _T_179 = and(_T_177, _T_178) @[FPU.scala 488:37] + node _T_180 = bits(io.in.bits.cmd, 0, 0) @[FPU.scala 488:78] + node _T_181 = cat(_T_179, _T_180) @[Cat.scala 30:58] + in.cmd <= _T_181 @[FPU.scala 488:12] + when io.in.bits.swap23 : @[FPU.scala 489:23] + in.in2 <= one @[FPU.scala 489:32] + skip @[FPU.scala 489:23] + node _T_182 = or(io.in.bits.ren3, io.in.bits.swap23) @[FPU.scala 490:21] + node _T_184 = eq(_T_182, UInt<1>("h00")) @[Conditional.scala 19:11] + when _T_184 : @[Conditional.scala 19:15] + in.in3 <= zero @[FPU.scala 490:45] + skip @[Conditional.scala 19:15] + skip @[FPU.scala 484:22] + inst fma of MulAddRecFN @[FPU.scala 493:19] + fma.io is invalid + fma.clock <= clock + fma.reset <= reset + fma.io.op <= in.cmd @[FPU.scala 494:13] + fma.io.roundingMode <= in.rm @[FPU.scala 495:23] + fma.io.a <= in.in1 @[FPU.scala 496:12] + fma.io.b <= in.in2 @[FPU.scala 497:12] + fma.io.c <= in.in3 @[FPU.scala 498:12] + wire res : {data : UInt<65>, exc : UInt<5>} @[FPU.scala 500:17] + res is invalid @[FPU.scala 500:17] + res.data <= fma.io.out @[FPU.scala 501:12] + res.exc <= fma.io.exceptionFlags @[FPU.scala 502:11] + reg _T_192 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18] + _T_192 <= valid @[Valid.scala 47:18] + reg _T_196 : {data : UInt<65>, exc : UInt<5>}, clock @[Reg.scala 34:16] + when valid : @[Reg.scala 35:19] + _T_196 <- res @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg _T_201 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18] + _T_201 <= _T_192 @[Valid.scala 47:18] + reg _T_205 : {data : UInt<65>, exc : UInt<5>}, clock @[Reg.scala 34:16] + when _T_192 : @[Reg.scala 35:19] + _T_205 <- _T_196 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + wire _T_217 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} @[Valid.scala 42:21] + _T_217 is invalid @[Valid.scala 42:21] + _T_217.valid <= _T_201 @[Valid.scala 43:17] + _T_217.bits <- _T_205 @[Valid.scala 44:16] + io.out <- _T_217 @[FPU.scala 503:10] + + module FPToInt : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, as_double : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, out : {valid : UInt<1>, bits : {lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}} + + io is invalid + io is invalid + reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock @[FPU.scala 286:15] + reg valid : UInt<1>, clock @[FPU.scala 287:18] + valid <= io.in.valid @[FPU.scala 287:18] + when io.in.valid : @[FPU.scala 291:22] + in <- io.in.bits @[FPU.scala 292:8] + node _T_224 = eq(io.in.bits.ldst, UInt<1>("h00")) @[FPU.scala 293:47] + node _T_225 = and(io.in.bits.single, _T_224) @[FPU.scala 293:44] + node _T_228 = and(io.in.bits.cmd, UInt<4>("h0c")) @[FPU.scala 293:82] + node _T_229 = eq(UInt<4>("h0c"), _T_228) @[FPU.scala 293:82] + node _T_231 = eq(_T_229, UInt<1>("h00")) @[FPU.scala 293:82] + node _T_232 = and(_T_225, _T_231) @[FPU.scala 293:64] + when _T_232 : @[FPU.scala 293:98] + node _T_233 = bits(io.in.bits.in1, 32, 32) @[FPU.scala 237:18] + node _T_234 = bits(io.in.bits.in1, 22, 0) @[FPU.scala 238:21] + node _T_235 = bits(io.in.bits.in1, 31, 23) @[FPU.scala 239:19] + node _T_236 = shl(_T_234, 53) @[FPU.scala 240:28] + node _T_237 = shr(_T_236, 24) @[FPU.scala 240:43] + node _T_238 = bits(_T_235, 8, 6) @[FPU.scala 242:26] + node _T_240 = add(_T_235, UInt<12>("h0800")) @[FPU.scala 243:31] + node _T_241 = tail(_T_240, 1) @[FPU.scala 243:31] + node _T_243 = sub(_T_241, UInt<9>("h0100")) @[FPU.scala 243:53] + node _T_244 = asUInt(_T_243) @[FPU.scala 243:53] + node _T_245 = tail(_T_244, 1) @[FPU.scala 243:53] + node _T_247 = eq(_T_238, UInt<1>("h00")) @[FPU.scala 244:19] + node _T_249 = geq(_T_238, UInt<3>("h06")) @[FPU.scala 244:36] + node _T_250 = or(_T_247, _T_249) @[FPU.scala 244:25] + node _T_251 = bits(_T_245, 8, 0) @[FPU.scala 244:65] + node _T_252 = cat(_T_238, _T_251) @[Cat.scala 30:58] + node _T_253 = bits(_T_245, 11, 0) @[FPU.scala 245:52] + node _T_254 = mux(_T_250, _T_252, _T_253) @[FPU.scala 244:10] + node _T_255 = cat(_T_233, _T_254) @[Cat.scala 30:58] + node _T_256 = cat(_T_255, _T_237) @[Cat.scala 30:58] + in.in1 <= _T_256 @[FPU.scala 294:14] + node _T_257 = bits(io.in.bits.in2, 32, 32) @[FPU.scala 237:18] + node _T_258 = bits(io.in.bits.in2, 22, 0) @[FPU.scala 238:21] + node _T_259 = bits(io.in.bits.in2, 31, 23) @[FPU.scala 239:19] + node _T_260 = shl(_T_258, 53) @[FPU.scala 240:28] + node _T_261 = shr(_T_260, 24) @[FPU.scala 240:43] + node _T_262 = bits(_T_259, 8, 6) @[FPU.scala 242:26] + node _T_264 = add(_T_259, UInt<12>("h0800")) @[FPU.scala 243:31] + node _T_265 = tail(_T_264, 1) @[FPU.scala 243:31] + node _T_267 = sub(_T_265, UInt<9>("h0100")) @[FPU.scala 243:53] + node _T_268 = asUInt(_T_267) @[FPU.scala 243:53] + node _T_269 = tail(_T_268, 1) @[FPU.scala 243:53] + node _T_271 = eq(_T_262, UInt<1>("h00")) @[FPU.scala 244:19] + node _T_273 = geq(_T_262, UInt<3>("h06")) @[FPU.scala 244:36] + node _T_274 = or(_T_271, _T_273) @[FPU.scala 244:25] + node _T_275 = bits(_T_269, 8, 0) @[FPU.scala 244:65] + node _T_276 = cat(_T_262, _T_275) @[Cat.scala 30:58] + node _T_277 = bits(_T_269, 11, 0) @[FPU.scala 245:52] + node _T_278 = mux(_T_274, _T_276, _T_277) @[FPU.scala 244:10] + node _T_279 = cat(_T_257, _T_278) @[Cat.scala 30:58] + node _T_280 = cat(_T_279, _T_261) @[Cat.scala 30:58] + in.in2 <= _T_280 @[FPU.scala 295:14] + skip @[FPU.scala 293:98] + skip @[FPU.scala 291:22] + node _T_281 = bits(in.in1, 32, 32) @[fNFromRecFN.scala 45:22] + node _T_282 = bits(in.in1, 31, 23) @[fNFromRecFN.scala 46:23] + node _T_283 = bits(in.in1, 22, 0) @[fNFromRecFN.scala 47:25] + node _T_284 = bits(_T_282, 6, 0) @[fNFromRecFN.scala 49:39] + node _T_286 = lt(_T_284, UInt<2>("h02")) @[fNFromRecFN.scala 49:57] + node _T_287 = bits(_T_282, 8, 6) @[fNFromRecFN.scala 51:19] + node _T_289 = eq(_T_287, UInt<1>("h01")) @[fNFromRecFN.scala 51:44] + node _T_290 = bits(_T_282, 8, 7) @[fNFromRecFN.scala 52:24] + node _T_292 = eq(_T_290, UInt<1>("h01")) @[fNFromRecFN.scala 52:49] + node _T_293 = and(_T_292, _T_286) @[fNFromRecFN.scala 52:62] + node _T_294 = or(_T_289, _T_293) @[fNFromRecFN.scala 51:57] + node _T_295 = bits(_T_282, 8, 7) @[fNFromRecFN.scala 55:20] + node _T_297 = eq(_T_295, UInt<1>("h01")) @[fNFromRecFN.scala 55:45] + node _T_299 = eq(_T_286, UInt<1>("h00")) @[fNFromRecFN.scala 56:18] + node _T_300 = and(_T_297, _T_299) @[fNFromRecFN.scala 55:58] + node _T_301 = bits(_T_282, 8, 7) @[fNFromRecFN.scala 57:23] + node _T_303 = eq(_T_301, UInt<2>("h02")) @[fNFromRecFN.scala 57:48] + node _T_304 = or(_T_300, _T_303) @[fNFromRecFN.scala 56:39] + node _T_305 = bits(_T_282, 8, 7) @[fNFromRecFN.scala 58:30] + node _T_307 = eq(_T_305, UInt<2>("h03")) @[fNFromRecFN.scala 58:55] + node _T_308 = bits(_T_282, 6, 6) @[fNFromRecFN.scala 59:39] + node _T_309 = and(_T_307, _T_308) @[fNFromRecFN.scala 59:31] + node _T_311 = bits(_T_282, 4, 0) @[fNFromRecFN.scala 61:46] + node _T_312 = sub(UInt<2>("h02"), _T_311) @[fNFromRecFN.scala 61:39] + node _T_313 = asUInt(_T_312) @[fNFromRecFN.scala 61:39] + node _T_314 = tail(_T_313, 1) @[fNFromRecFN.scala 61:39] + node _T_316 = cat(UInt<1>("h01"), _T_283) @[Cat.scala 30:58] + node _T_317 = dshr(_T_316, _T_314) @[fNFromRecFN.scala 63:35] + node _T_318 = bits(_T_317, 22, 0) @[fNFromRecFN.scala 63:53] + node _T_319 = bits(_T_282, 7, 0) @[fNFromRecFN.scala 65:18] + node _T_321 = sub(_T_319, UInt<8>("h081")) @[fNFromRecFN.scala 65:36] + node _T_322 = asUInt(_T_321) @[fNFromRecFN.scala 65:36] + node _T_323 = tail(_T_322, 1) @[fNFromRecFN.scala 65:36] + node _T_324 = bits(_T_307, 0, 0) @[Bitwise.scala 71:15] + node _T_327 = mux(_T_324, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_328 = mux(_T_304, _T_323, _T_327) @[fNFromRecFN.scala 68:16] + node _T_329 = or(_T_304, _T_309) @[fNFromRecFN.scala 70:26] + node _T_331 = mux(_T_294, _T_318, UInt<1>("h00")) @[fNFromRecFN.scala 72:20] + node _T_332 = mux(_T_329, _T_283, _T_331) @[fNFromRecFN.scala 70:16] + node _T_333 = cat(_T_281, _T_328) @[Cat.scala 30:58] + node _T_334 = cat(_T_333, _T_332) @[Cat.scala 30:58] + node _T_335 = bits(_T_334, 31, 31) @[Package.scala 40:38] + node _T_336 = bits(_T_335, 0, 0) @[Bitwise.scala 71:15] + node _T_339 = mux(_T_336, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12] + node unrec_s = cat(_T_339, _T_334) @[Cat.scala 30:58] + node _T_340 = bits(in.in1, 64, 64) @[fNFromRecFN.scala 45:22] + node _T_341 = bits(in.in1, 63, 52) @[fNFromRecFN.scala 46:23] + node _T_342 = bits(in.in1, 51, 0) @[fNFromRecFN.scala 47:25] + node _T_343 = bits(_T_341, 9, 0) @[fNFromRecFN.scala 49:39] + node _T_345 = lt(_T_343, UInt<2>("h02")) @[fNFromRecFN.scala 49:57] + node _T_346 = bits(_T_341, 11, 9) @[fNFromRecFN.scala 51:19] + node _T_348 = eq(_T_346, UInt<1>("h01")) @[fNFromRecFN.scala 51:44] + node _T_349 = bits(_T_341, 11, 10) @[fNFromRecFN.scala 52:24] + node _T_351 = eq(_T_349, UInt<1>("h01")) @[fNFromRecFN.scala 52:49] + node _T_352 = and(_T_351, _T_345) @[fNFromRecFN.scala 52:62] + node _T_353 = or(_T_348, _T_352) @[fNFromRecFN.scala 51:57] + node _T_354 = bits(_T_341, 11, 10) @[fNFromRecFN.scala 55:20] + node _T_356 = eq(_T_354, UInt<1>("h01")) @[fNFromRecFN.scala 55:45] + node _T_358 = eq(_T_345, UInt<1>("h00")) @[fNFromRecFN.scala 56:18] + node _T_359 = and(_T_356, _T_358) @[fNFromRecFN.scala 55:58] + node _T_360 = bits(_T_341, 11, 10) @[fNFromRecFN.scala 57:23] + node _T_362 = eq(_T_360, UInt<2>("h02")) @[fNFromRecFN.scala 57:48] + node _T_363 = or(_T_359, _T_362) @[fNFromRecFN.scala 56:39] + node _T_364 = bits(_T_341, 11, 10) @[fNFromRecFN.scala 58:30] + node _T_366 = eq(_T_364, UInt<2>("h03")) @[fNFromRecFN.scala 58:55] + node _T_367 = bits(_T_341, 9, 9) @[fNFromRecFN.scala 59:39] + node _T_368 = and(_T_366, _T_367) @[fNFromRecFN.scala 59:31] + node _T_370 = bits(_T_341, 5, 0) @[fNFromRecFN.scala 61:46] + node _T_371 = sub(UInt<2>("h02"), _T_370) @[fNFromRecFN.scala 61:39] + node _T_372 = asUInt(_T_371) @[fNFromRecFN.scala 61:39] + node _T_373 = tail(_T_372, 1) @[fNFromRecFN.scala 61:39] + node _T_375 = cat(UInt<1>("h01"), _T_342) @[Cat.scala 30:58] + node _T_376 = dshr(_T_375, _T_373) @[fNFromRecFN.scala 63:35] + node _T_377 = bits(_T_376, 51, 0) @[fNFromRecFN.scala 63:53] + node _T_378 = bits(_T_341, 10, 0) @[fNFromRecFN.scala 65:18] + node _T_380 = sub(_T_378, UInt<11>("h0401")) @[fNFromRecFN.scala 65:36] + node _T_381 = asUInt(_T_380) @[fNFromRecFN.scala 65:36] + node _T_382 = tail(_T_381, 1) @[fNFromRecFN.scala 65:36] + node _T_383 = bits(_T_366, 0, 0) @[Bitwise.scala 71:15] + node _T_386 = mux(_T_383, UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 71:12] + node _T_387 = mux(_T_363, _T_382, _T_386) @[fNFromRecFN.scala 68:16] + node _T_388 = or(_T_363, _T_368) @[fNFromRecFN.scala 70:26] + node _T_390 = mux(_T_353, _T_377, UInt<1>("h00")) @[fNFromRecFN.scala 72:20] + node _T_391 = mux(_T_388, _T_342, _T_390) @[fNFromRecFN.scala 70:16] + node _T_392 = cat(_T_340, _T_387) @[Cat.scala 30:58] + node _T_393 = cat(_T_392, _T_391) @[Cat.scala 30:58] + node unrec_int = mux(in.single, unrec_s, _T_393) @[FPU.scala 304:10] + node _T_394 = bits(in.in1, 32, 32) @[FPU.scala 201:18] + node _T_395 = bits(in.in1, 31, 23) @[FPU.scala 202:17] + node _T_396 = bits(in.in1, 22, 0) @[FPU.scala 203:17] + node _T_397 = bits(_T_395, 8, 6) @[FPU.scala 205:26] + node _T_398 = bits(_T_397, 2, 1) @[FPU.scala 206:27] + node _T_400 = eq(_T_398, UInt<2>("h03")) @[FPU.scala 207:30] + node _T_401 = bits(_T_395, 6, 0) @[FPU.scala 209:32] + node _T_403 = lt(_T_401, UInt<2>("h02")) @[FPU.scala 209:48] + node _T_405 = eq(_T_397, UInt<1>("h01")) @[FPU.scala 210:28] + node _T_407 = eq(_T_398, UInt<1>("h01")) @[FPU.scala 210:50] + node _T_408 = and(_T_407, _T_403) @[FPU.scala 210:62] + node _T_409 = or(_T_405, _T_408) @[FPU.scala 210:40] + node _T_411 = eq(_T_398, UInt<1>("h01")) @[FPU.scala 211:27] + node _T_413 = eq(_T_403, UInt<1>("h00")) @[FPU.scala 211:42] + node _T_414 = and(_T_411, _T_413) @[FPU.scala 211:39] + node _T_416 = eq(_T_398, UInt<2>("h02")) @[FPU.scala 211:71] + node _T_417 = or(_T_414, _T_416) @[FPU.scala 211:61] + node _T_419 = eq(_T_397, UInt<1>("h00")) @[FPU.scala 212:23] + node _T_420 = bits(_T_395, 6, 6) @[FPU.scala 213:34] + node _T_422 = eq(_T_420, UInt<1>("h00")) @[FPU.scala 213:30] + node _T_423 = and(_T_400, _T_422) @[FPU.scala 213:27] + node _T_424 = not(_T_397) @[FPU.scala 214:22] + node _T_426 = eq(_T_424, UInt<1>("h00")) @[FPU.scala 214:22] + node _T_427 = bits(_T_396, 22, 22) @[FPU.scala 215:31] + node _T_429 = eq(_T_427, UInt<1>("h00")) @[FPU.scala 215:27] + node _T_430 = and(_T_426, _T_429) @[FPU.scala 215:24] + node _T_431 = bits(_T_396, 22, 22) @[FPU.scala 216:30] + node _T_432 = and(_T_426, _T_431) @[FPU.scala 216:24] + node _T_434 = eq(_T_394, UInt<1>("h00")) @[FPU.scala 218:34] + node _T_435 = and(_T_423, _T_434) @[FPU.scala 218:31] + node _T_437 = eq(_T_394, UInt<1>("h00")) @[FPU.scala 218:53] + node _T_438 = and(_T_417, _T_437) @[FPU.scala 218:50] + node _T_440 = eq(_T_394, UInt<1>("h00")) @[FPU.scala 219:24] + node _T_441 = and(_T_409, _T_440) @[FPU.scala 219:21] + node _T_443 = eq(_T_394, UInt<1>("h00")) @[FPU.scala 219:41] + node _T_444 = and(_T_419, _T_443) @[FPU.scala 219:38] + node _T_445 = and(_T_419, _T_394) @[FPU.scala 219:55] + node _T_446 = and(_T_409, _T_394) @[FPU.scala 220:21] + node _T_447 = and(_T_417, _T_394) @[FPU.scala 220:39] + node _T_448 = and(_T_423, _T_394) @[FPU.scala 220:54] + node _T_449 = cat(_T_447, _T_448) @[Cat.scala 30:58] + node _T_450 = cat(_T_444, _T_445) @[Cat.scala 30:58] + node _T_451 = cat(_T_450, _T_446) @[Cat.scala 30:58] + node _T_452 = cat(_T_451, _T_449) @[Cat.scala 30:58] + node _T_453 = cat(_T_438, _T_441) @[Cat.scala 30:58] + node _T_454 = cat(_T_432, _T_430) @[Cat.scala 30:58] + node _T_455 = cat(_T_454, _T_435) @[Cat.scala 30:58] + node _T_456 = cat(_T_455, _T_453) @[Cat.scala 30:58] + node classify_s = cat(_T_456, _T_452) @[Cat.scala 30:58] + node _T_457 = bits(in.in1, 64, 64) @[FPU.scala 201:18] + node _T_458 = bits(in.in1, 63, 52) @[FPU.scala 202:17] + node _T_459 = bits(in.in1, 51, 0) @[FPU.scala 203:17] + node _T_460 = bits(_T_458, 11, 9) @[FPU.scala 205:26] + node _T_461 = bits(_T_460, 2, 1) @[FPU.scala 206:27] + node _T_463 = eq(_T_461, UInt<2>("h03")) @[FPU.scala 207:30] + node _T_464 = bits(_T_458, 9, 0) @[FPU.scala 209:32] + node _T_466 = lt(_T_464, UInt<2>("h02")) @[FPU.scala 209:48] + node _T_468 = eq(_T_460, UInt<1>("h01")) @[FPU.scala 210:28] + node _T_470 = eq(_T_461, UInt<1>("h01")) @[FPU.scala 210:50] + node _T_471 = and(_T_470, _T_466) @[FPU.scala 210:62] + node _T_472 = or(_T_468, _T_471) @[FPU.scala 210:40] + node _T_474 = eq(_T_461, UInt<1>("h01")) @[FPU.scala 211:27] + node _T_476 = eq(_T_466, UInt<1>("h00")) @[FPU.scala 211:42] + node _T_477 = and(_T_474, _T_476) @[FPU.scala 211:39] + node _T_479 = eq(_T_461, UInt<2>("h02")) @[FPU.scala 211:71] + node _T_480 = or(_T_477, _T_479) @[FPU.scala 211:61] + node _T_482 = eq(_T_460, UInt<1>("h00")) @[FPU.scala 212:23] + node _T_483 = bits(_T_458, 9, 9) @[FPU.scala 213:34] + node _T_485 = eq(_T_483, UInt<1>("h00")) @[FPU.scala 213:30] + node _T_486 = and(_T_463, _T_485) @[FPU.scala 213:27] + node _T_487 = not(_T_460) @[FPU.scala 214:22] + node _T_489 = eq(_T_487, UInt<1>("h00")) @[FPU.scala 214:22] + node _T_490 = bits(_T_459, 51, 51) @[FPU.scala 215:31] + node _T_492 = eq(_T_490, UInt<1>("h00")) @[FPU.scala 215:27] + node _T_493 = and(_T_489, _T_492) @[FPU.scala 215:24] + node _T_494 = bits(_T_459, 51, 51) @[FPU.scala 216:30] + node _T_495 = and(_T_489, _T_494) @[FPU.scala 216:24] + node _T_497 = eq(_T_457, UInt<1>("h00")) @[FPU.scala 218:34] + node _T_498 = and(_T_486, _T_497) @[FPU.scala 218:31] + node _T_500 = eq(_T_457, UInt<1>("h00")) @[FPU.scala 218:53] + node _T_501 = and(_T_480, _T_500) @[FPU.scala 218:50] + node _T_503 = eq(_T_457, UInt<1>("h00")) @[FPU.scala 219:24] + node _T_504 = and(_T_472, _T_503) @[FPU.scala 219:21] + node _T_506 = eq(_T_457, UInt<1>("h00")) @[FPU.scala 219:41] + node _T_507 = and(_T_482, _T_506) @[FPU.scala 219:38] + node _T_508 = and(_T_482, _T_457) @[FPU.scala 219:55] + node _T_509 = and(_T_472, _T_457) @[FPU.scala 220:21] + node _T_510 = and(_T_480, _T_457) @[FPU.scala 220:39] + node _T_511 = and(_T_486, _T_457) @[FPU.scala 220:54] + node _T_512 = cat(_T_510, _T_511) @[Cat.scala 30:58] + node _T_513 = cat(_T_507, _T_508) @[Cat.scala 30:58] + node _T_514 = cat(_T_513, _T_509) @[Cat.scala 30:58] + node _T_515 = cat(_T_514, _T_512) @[Cat.scala 30:58] + node _T_516 = cat(_T_501, _T_504) @[Cat.scala 30:58] + node _T_517 = cat(_T_495, _T_493) @[Cat.scala 30:58] + node _T_518 = cat(_T_517, _T_498) @[Cat.scala 30:58] + node _T_519 = cat(_T_518, _T_516) @[Cat.scala 30:58] + node _T_520 = cat(_T_519, _T_515) @[Cat.scala 30:58] + node classify_out = mux(in.single, classify_s, _T_520) @[FPU.scala 316:10] + inst dcmp of CompareRecFN @[FPU.scala 319:20] + dcmp.io is invalid + dcmp.clock <= clock + dcmp.reset <= reset + dcmp.io.a <= in.in1 @[FPU.scala 320:13] + dcmp.io.b <= in.in2 @[FPU.scala 321:13] + node _T_521 = bits(in.rm, 1, 1) @[FPU.scala 322:30] + node _T_523 = eq(_T_521, UInt<1>("h00")) @[FPU.scala 322:24] + dcmp.io.signaling <= _T_523 @[FPU.scala 322:21] + node _T_524 = bits(in.rm, 0, 0) @[FPU.scala 324:33] + node _T_525 = mux(_T_524, classify_out, unrec_int) @[FPU.scala 324:27] + io.out.bits.toint <= _T_525 @[FPU.scala 324:21] + io.out.bits.store <= unrec_int @[FPU.scala 325:21] + io.out.bits.exc <= UInt<1>("h00") @[FPU.scala 326:19] + node _T_529 = and(in.cmd, UInt<4>("h0c")) @[FPU.scala 328:16] + node _T_530 = eq(UInt<3>("h04"), _T_529) @[FPU.scala 328:16] + when _T_530 : @[FPU.scala 328:30] + node _T_531 = not(in.rm) @[FPU.scala 329:27] + node _T_532 = cat(dcmp.io.lt, dcmp.io.eq) @[Cat.scala 30:58] + node _T_533 = and(_T_531, _T_532) @[FPU.scala 329:34] + node _T_535 = neq(_T_533, UInt<1>("h00")) @[FPU.scala 329:65] + io.out.bits.toint <= _T_535 @[FPU.scala 329:23] + io.out.bits.exc <= dcmp.io.exceptionFlags @[FPU.scala 330:21] + skip @[FPU.scala 328:30] + node _T_538 = and(in.cmd, UInt<4>("h0c")) @[FPU.scala 332:16] + node _T_539 = eq(UInt<4>("h08"), _T_538) @[FPU.scala 332:16] + when _T_539 : @[FPU.scala 332:33] + inst RecFNToIN of RecFNToIN @[FPU.scala 336:24] + RecFNToIN.io is invalid + RecFNToIN.clock <= clock + RecFNToIN.reset <= reset + RecFNToIN.io.in <= in.in1 @[FPU.scala 337:18] + RecFNToIN.io.roundingMode <= in.rm @[FPU.scala 338:28] + node _T_540 = bits(in.typ, 0, 0) @[FPU.scala 339:35] + node _T_541 = not(_T_540) @[FPU.scala 339:28] + RecFNToIN.io.signedOut <= _T_541 @[FPU.scala 339:25] + node _T_542 = bits(in.typ, 1, 1) @[Package.scala 44:13] + node _T_544 = eq(_T_542, UInt<1>("h00")) @[FPU.scala 340:44] + when _T_544 : @[FPU.scala 340:51] + node _T_545 = bits(RecFNToIN.io.out, 31, 31) @[Package.scala 40:38] + node _T_546 = bits(_T_545, 0, 0) @[Bitwise.scala 71:15] + node _T_549 = mux(_T_546, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12] + node _T_550 = cat(_T_549, RecFNToIN.io.out) @[Cat.scala 30:58] + io.out.bits.toint <= _T_550 @[FPU.scala 341:27] + node _T_551 = bits(RecFNToIN.io.intExceptionFlags, 2, 1) @[FPU.scala 342:57] + node _T_553 = neq(_T_551, UInt<1>("h00")) @[FPU.scala 342:64] + node _T_555 = bits(RecFNToIN.io.intExceptionFlags, 0, 0) @[FPU.scala 342:106] + node _T_556 = cat(_T_553, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_557 = cat(_T_556, _T_555) @[Cat.scala 30:58] + io.out.bits.exc <= _T_557 @[FPU.scala 342:25] + skip @[FPU.scala 340:51] + inst RecFNToIN_1 of RecFNToIN_1 @[FPU.scala 336:24] + RecFNToIN_1.io is invalid + RecFNToIN_1.clock <= clock + RecFNToIN_1.reset <= reset + RecFNToIN_1.io.in <= in.in1 @[FPU.scala 337:18] + RecFNToIN_1.io.roundingMode <= in.rm @[FPU.scala 338:28] + node _T_558 = bits(in.typ, 0, 0) @[FPU.scala 339:35] + node _T_559 = not(_T_558) @[FPU.scala 339:28] + RecFNToIN_1.io.signedOut <= _T_559 @[FPU.scala 339:25] + node _T_560 = bits(in.typ, 1, 1) @[Package.scala 44:13] + node _T_562 = eq(_T_560, UInt<1>("h01")) @[FPU.scala 340:44] + when _T_562 : @[FPU.scala 340:51] + io.out.bits.toint <= RecFNToIN_1.io.out @[FPU.scala 341:27] + node _T_563 = bits(RecFNToIN_1.io.intExceptionFlags, 2, 1) @[FPU.scala 342:57] + node _T_565 = neq(_T_563, UInt<1>("h00")) @[FPU.scala 342:64] + node _T_567 = bits(RecFNToIN_1.io.intExceptionFlags, 0, 0) @[FPU.scala 342:106] + node _T_568 = cat(_T_565, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_569 = cat(_T_568, _T_567) @[Cat.scala 30:58] + io.out.bits.exc <= _T_569 @[FPU.scala 342:25] + skip @[FPU.scala 340:51] + skip @[FPU.scala 332:33] + io.out.valid <= valid @[FPU.scala 347:16] + io.out.bits.lt <= dcmp.io.lt @[FPU.scala 348:18] + io.as_double <- in @[FPU.scala 349:16] + + module IntToFP : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} + + io is invalid + io is invalid + reg _T_132 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18] + _T_132 <= io.in.valid @[Valid.scala 47:18] + reg _T_155 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock @[Reg.scala 34:16] + when io.in.valid : @[Reg.scala 35:19] + _T_155 <- io.in.bits @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + wire in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} @[Valid.scala 42:21] + in is invalid @[Valid.scala 42:21] + in.valid <= _T_132 @[Valid.scala 43:17] + in.bits <- _T_155 @[Valid.scala 44:16] + wire mux : {data : UInt<65>, exc : UInt<5>} @[FPU.scala 360:17] + mux is invalid @[FPU.scala 360:17] + mux.exc <= UInt<1>("h00") @[FPU.scala 361:11] + node _T_276 = bits(in.bits.in1, 31, 31) @[recFNFromFN.scala 47:22] + node _T_277 = bits(in.bits.in1, 30, 23) @[recFNFromFN.scala 48:23] + node _T_278 = bits(in.bits.in1, 22, 0) @[recFNFromFN.scala 49:25] + node _T_280 = eq(_T_277, UInt<1>("h00")) @[recFNFromFN.scala 51:34] + node _T_282 = eq(_T_278, UInt<1>("h00")) @[recFNFromFN.scala 52:38] + node _T_283 = and(_T_280, _T_282) @[recFNFromFN.scala 53:34] + node _T_284 = shl(_T_278, 9) @[recFNFromFN.scala 56:26] + node _T_285 = bits(_T_284, 31, 16) @[CircuitMath.scala 35:17] + node _T_286 = bits(_T_284, 15, 0) @[CircuitMath.scala 36:17] + node _T_288 = neq(_T_285, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_289 = bits(_T_285, 15, 8) @[CircuitMath.scala 35:17] + node _T_290 = bits(_T_285, 7, 0) @[CircuitMath.scala 36:17] + node _T_292 = neq(_T_289, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_293 = bits(_T_289, 7, 4) @[CircuitMath.scala 35:17] + node _T_294 = bits(_T_289, 3, 0) @[CircuitMath.scala 36:17] + node _T_296 = neq(_T_293, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_297 = bits(_T_293, 3, 3) @[CircuitMath.scala 32:12] + node _T_299 = bits(_T_293, 2, 2) @[CircuitMath.scala 32:12] + node _T_301 = bits(_T_293, 1, 1) @[CircuitMath.scala 30:8] + node _T_302 = mux(_T_299, UInt<2>("h02"), _T_301) @[CircuitMath.scala 32:10] + node _T_303 = mux(_T_297, UInt<2>("h03"), _T_302) @[CircuitMath.scala 32:10] + node _T_304 = bits(_T_294, 3, 3) @[CircuitMath.scala 32:12] + node _T_306 = bits(_T_294, 2, 2) @[CircuitMath.scala 32:12] + node _T_308 = bits(_T_294, 1, 1) @[CircuitMath.scala 30:8] + node _T_309 = mux(_T_306, UInt<2>("h02"), _T_308) @[CircuitMath.scala 32:10] + node _T_310 = mux(_T_304, UInt<2>("h03"), _T_309) @[CircuitMath.scala 32:10] + node _T_311 = mux(_T_296, _T_303, _T_310) @[CircuitMath.scala 38:21] + node _T_312 = cat(_T_296, _T_311) @[Cat.scala 30:58] + node _T_313 = bits(_T_290, 7, 4) @[CircuitMath.scala 35:17] + node _T_314 = bits(_T_290, 3, 0) @[CircuitMath.scala 36:17] + node _T_316 = neq(_T_313, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_317 = bits(_T_313, 3, 3) @[CircuitMath.scala 32:12] + node _T_319 = bits(_T_313, 2, 2) @[CircuitMath.scala 32:12] + node _T_321 = bits(_T_313, 1, 1) @[CircuitMath.scala 30:8] + node _T_322 = mux(_T_319, UInt<2>("h02"), _T_321) @[CircuitMath.scala 32:10] + node _T_323 = mux(_T_317, UInt<2>("h03"), _T_322) @[CircuitMath.scala 32:10] + node _T_324 = bits(_T_314, 3, 3) @[CircuitMath.scala 32:12] + node _T_326 = bits(_T_314, 2, 2) @[CircuitMath.scala 32:12] + node _T_328 = bits(_T_314, 1, 1) @[CircuitMath.scala 30:8] + node _T_329 = mux(_T_326, UInt<2>("h02"), _T_328) @[CircuitMath.scala 32:10] + node _T_330 = mux(_T_324, UInt<2>("h03"), _T_329) @[CircuitMath.scala 32:10] + node _T_331 = mux(_T_316, _T_323, _T_330) @[CircuitMath.scala 38:21] + node _T_332 = cat(_T_316, _T_331) @[Cat.scala 30:58] + node _T_333 = mux(_T_292, _T_312, _T_332) @[CircuitMath.scala 38:21] + node _T_334 = cat(_T_292, _T_333) @[Cat.scala 30:58] + node _T_335 = bits(_T_286, 15, 8) @[CircuitMath.scala 35:17] + node _T_336 = bits(_T_286, 7, 0) @[CircuitMath.scala 36:17] + node _T_338 = neq(_T_335, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_339 = bits(_T_335, 7, 4) @[CircuitMath.scala 35:17] + node _T_340 = bits(_T_335, 3, 0) @[CircuitMath.scala 36:17] + node _T_342 = neq(_T_339, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_343 = bits(_T_339, 3, 3) @[CircuitMath.scala 32:12] + node _T_345 = bits(_T_339, 2, 2) @[CircuitMath.scala 32:12] + node _T_347 = bits(_T_339, 1, 1) @[CircuitMath.scala 30:8] + node _T_348 = mux(_T_345, UInt<2>("h02"), _T_347) @[CircuitMath.scala 32:10] + node _T_349 = mux(_T_343, UInt<2>("h03"), _T_348) @[CircuitMath.scala 32:10] + node _T_350 = bits(_T_340, 3, 3) @[CircuitMath.scala 32:12] + node _T_352 = bits(_T_340, 2, 2) @[CircuitMath.scala 32:12] + node _T_354 = bits(_T_340, 1, 1) @[CircuitMath.scala 30:8] + node _T_355 = mux(_T_352, UInt<2>("h02"), _T_354) @[CircuitMath.scala 32:10] + node _T_356 = mux(_T_350, UInt<2>("h03"), _T_355) @[CircuitMath.scala 32:10] + node _T_357 = mux(_T_342, _T_349, _T_356) @[CircuitMath.scala 38:21] + node _T_358 = cat(_T_342, _T_357) @[Cat.scala 30:58] + node _T_359 = bits(_T_336, 7, 4) @[CircuitMath.scala 35:17] + node _T_360 = bits(_T_336, 3, 0) @[CircuitMath.scala 36:17] + node _T_362 = neq(_T_359, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_363 = bits(_T_359, 3, 3) @[CircuitMath.scala 32:12] + node _T_365 = bits(_T_359, 2, 2) @[CircuitMath.scala 32:12] + node _T_367 = bits(_T_359, 1, 1) @[CircuitMath.scala 30:8] + node _T_368 = mux(_T_365, UInt<2>("h02"), _T_367) @[CircuitMath.scala 32:10] + node _T_369 = mux(_T_363, UInt<2>("h03"), _T_368) @[CircuitMath.scala 32:10] + node _T_370 = bits(_T_360, 3, 3) @[CircuitMath.scala 32:12] + node _T_372 = bits(_T_360, 2, 2) @[CircuitMath.scala 32:12] + node _T_374 = bits(_T_360, 1, 1) @[CircuitMath.scala 30:8] + node _T_375 = mux(_T_372, UInt<2>("h02"), _T_374) @[CircuitMath.scala 32:10] + node _T_376 = mux(_T_370, UInt<2>("h03"), _T_375) @[CircuitMath.scala 32:10] + node _T_377 = mux(_T_362, _T_369, _T_376) @[CircuitMath.scala 38:21] + node _T_378 = cat(_T_362, _T_377) @[Cat.scala 30:58] + node _T_379 = mux(_T_338, _T_358, _T_378) @[CircuitMath.scala 38:21] + node _T_380 = cat(_T_338, _T_379) @[Cat.scala 30:58] + node _T_381 = mux(_T_288, _T_334, _T_380) @[CircuitMath.scala 38:21] + node _T_382 = cat(_T_288, _T_381) @[Cat.scala 30:58] + node _T_383 = not(_T_382) @[recFNFromFN.scala 56:13] + node _T_384 = dshl(_T_278, _T_383) @[recFNFromFN.scala 58:25] + node _T_385 = bits(_T_384, 21, 0) @[recFNFromFN.scala 58:37] + node _T_387 = cat(_T_385, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_392 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 71:12] + node _T_393 = xor(_T_383, _T_392) @[recFNFromFN.scala 62:27] + node _T_394 = mux(_T_280, _T_393, _T_277) @[recFNFromFN.scala 61:16] + node _T_398 = mux(_T_280, UInt<2>("h02"), UInt<1>("h01")) @[recFNFromFN.scala 64:47] + node _T_399 = or(UInt<8>("h080"), _T_398) @[recFNFromFN.scala 64:42] + node _T_400 = add(_T_394, _T_399) @[recFNFromFN.scala 64:15] + node _T_401 = tail(_T_400, 1) @[recFNFromFN.scala 64:15] + node _T_402 = bits(_T_401, 8, 7) @[recFNFromFN.scala 67:25] + node _T_404 = eq(_T_402, UInt<2>("h03")) @[recFNFromFN.scala 67:50] + node _T_406 = eq(_T_282, UInt<1>("h00")) @[recFNFromFN.scala 68:17] + node _T_407 = and(_T_404, _T_406) @[recFNFromFN.scala 67:63] + node _T_408 = bits(_T_283, 0, 0) @[Bitwise.scala 71:15] + node _T_411 = mux(_T_408, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 71:12] + node _T_412 = shl(_T_411, 6) @[recFNFromFN.scala 71:45] + node _T_413 = not(_T_412) @[recFNFromFN.scala 71:28] + node _T_414 = and(_T_401, _T_413) @[recFNFromFN.scala 71:26] + node _T_415 = shl(_T_407, 6) @[recFNFromFN.scala 72:22] + node _T_416 = or(_T_414, _T_415) @[recFNFromFN.scala 71:64] + node _T_417 = mux(_T_280, _T_387, _T_278) @[recFNFromFN.scala 73:27] + node _T_418 = cat(_T_276, _T_416) @[Cat.scala 30:58] + node _T_419 = cat(_T_418, _T_417) @[Cat.scala 30:58] + mux.data <= _T_419 @[FPU.scala 362:12] + node _T_421 = eq(in.bits.single, UInt<1>("h00")) @[FPU.scala 363:24] + when _T_421 : @[FPU.scala 363:41] + node _T_422 = bits(in.bits.in1, 63, 63) @[recFNFromFN.scala 47:22] + node _T_423 = bits(in.bits.in1, 62, 52) @[recFNFromFN.scala 48:23] + node _T_424 = bits(in.bits.in1, 51, 0) @[recFNFromFN.scala 49:25] + node _T_426 = eq(_T_423, UInt<1>("h00")) @[recFNFromFN.scala 51:34] + node _T_428 = eq(_T_424, UInt<1>("h00")) @[recFNFromFN.scala 52:38] + node _T_429 = and(_T_426, _T_428) @[recFNFromFN.scala 53:34] + node _T_430 = shl(_T_424, 12) @[recFNFromFN.scala 56:26] + node _T_431 = bits(_T_430, 63, 32) @[CircuitMath.scala 35:17] + node _T_432 = bits(_T_430, 31, 0) @[CircuitMath.scala 36:17] + node _T_434 = neq(_T_431, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_435 = bits(_T_431, 31, 16) @[CircuitMath.scala 35:17] + node _T_436 = bits(_T_431, 15, 0) @[CircuitMath.scala 36:17] + node _T_438 = neq(_T_435, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_439 = bits(_T_435, 15, 8) @[CircuitMath.scala 35:17] + node _T_440 = bits(_T_435, 7, 0) @[CircuitMath.scala 36:17] + node _T_442 = neq(_T_439, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_443 = bits(_T_439, 7, 4) @[CircuitMath.scala 35:17] + node _T_444 = bits(_T_439, 3, 0) @[CircuitMath.scala 36:17] + node _T_446 = neq(_T_443, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_447 = bits(_T_443, 3, 3) @[CircuitMath.scala 32:12] + node _T_449 = bits(_T_443, 2, 2) @[CircuitMath.scala 32:12] + node _T_451 = bits(_T_443, 1, 1) @[CircuitMath.scala 30:8] + node _T_452 = mux(_T_449, UInt<2>("h02"), _T_451) @[CircuitMath.scala 32:10] + node _T_453 = mux(_T_447, UInt<2>("h03"), _T_452) @[CircuitMath.scala 32:10] + node _T_454 = bits(_T_444, 3, 3) @[CircuitMath.scala 32:12] + node _T_456 = bits(_T_444, 2, 2) @[CircuitMath.scala 32:12] + node _T_458 = bits(_T_444, 1, 1) @[CircuitMath.scala 30:8] + node _T_459 = mux(_T_456, UInt<2>("h02"), _T_458) @[CircuitMath.scala 32:10] + node _T_460 = mux(_T_454, UInt<2>("h03"), _T_459) @[CircuitMath.scala 32:10] + node _T_461 = mux(_T_446, _T_453, _T_460) @[CircuitMath.scala 38:21] + node _T_462 = cat(_T_446, _T_461) @[Cat.scala 30:58] + node _T_463 = bits(_T_440, 7, 4) @[CircuitMath.scala 35:17] + node _T_464 = bits(_T_440, 3, 0) @[CircuitMath.scala 36:17] + node _T_466 = neq(_T_463, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_467 = bits(_T_463, 3, 3) @[CircuitMath.scala 32:12] + node _T_469 = bits(_T_463, 2, 2) @[CircuitMath.scala 32:12] + node _T_471 = bits(_T_463, 1, 1) @[CircuitMath.scala 30:8] + node _T_472 = mux(_T_469, UInt<2>("h02"), _T_471) @[CircuitMath.scala 32:10] + node _T_473 = mux(_T_467, UInt<2>("h03"), _T_472) @[CircuitMath.scala 32:10] + node _T_474 = bits(_T_464, 3, 3) @[CircuitMath.scala 32:12] + node _T_476 = bits(_T_464, 2, 2) @[CircuitMath.scala 32:12] + node _T_478 = bits(_T_464, 1, 1) @[CircuitMath.scala 30:8] + node _T_479 = mux(_T_476, UInt<2>("h02"), _T_478) @[CircuitMath.scala 32:10] + node _T_480 = mux(_T_474, UInt<2>("h03"), _T_479) @[CircuitMath.scala 32:10] + node _T_481 = mux(_T_466, _T_473, _T_480) @[CircuitMath.scala 38:21] + node _T_482 = cat(_T_466, _T_481) @[Cat.scala 30:58] + node _T_483 = mux(_T_442, _T_462, _T_482) @[CircuitMath.scala 38:21] + node _T_484 = cat(_T_442, _T_483) @[Cat.scala 30:58] + node _T_485 = bits(_T_436, 15, 8) @[CircuitMath.scala 35:17] + node _T_486 = bits(_T_436, 7, 0) @[CircuitMath.scala 36:17] + node _T_488 = neq(_T_485, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_489 = bits(_T_485, 7, 4) @[CircuitMath.scala 35:17] + node _T_490 = bits(_T_485, 3, 0) @[CircuitMath.scala 36:17] + node _T_492 = neq(_T_489, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_493 = bits(_T_489, 3, 3) @[CircuitMath.scala 32:12] + node _T_495 = bits(_T_489, 2, 2) @[CircuitMath.scala 32:12] + node _T_497 = bits(_T_489, 1, 1) @[CircuitMath.scala 30:8] + node _T_498 = mux(_T_495, UInt<2>("h02"), _T_497) @[CircuitMath.scala 32:10] + node _T_499 = mux(_T_493, UInt<2>("h03"), _T_498) @[CircuitMath.scala 32:10] + node _T_500 = bits(_T_490, 3, 3) @[CircuitMath.scala 32:12] + node _T_502 = bits(_T_490, 2, 2) @[CircuitMath.scala 32:12] + node _T_504 = bits(_T_490, 1, 1) @[CircuitMath.scala 30:8] + node _T_505 = mux(_T_502, UInt<2>("h02"), _T_504) @[CircuitMath.scala 32:10] + node _T_506 = mux(_T_500, UInt<2>("h03"), _T_505) @[CircuitMath.scala 32:10] + node _T_507 = mux(_T_492, _T_499, _T_506) @[CircuitMath.scala 38:21] + node _T_508 = cat(_T_492, _T_507) @[Cat.scala 30:58] + node _T_509 = bits(_T_486, 7, 4) @[CircuitMath.scala 35:17] + node _T_510 = bits(_T_486, 3, 0) @[CircuitMath.scala 36:17] + node _T_512 = neq(_T_509, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_513 = bits(_T_509, 3, 3) @[CircuitMath.scala 32:12] + node _T_515 = bits(_T_509, 2, 2) @[CircuitMath.scala 32:12] + node _T_517 = bits(_T_509, 1, 1) @[CircuitMath.scala 30:8] + node _T_518 = mux(_T_515, UInt<2>("h02"), _T_517) @[CircuitMath.scala 32:10] + node _T_519 = mux(_T_513, UInt<2>("h03"), _T_518) @[CircuitMath.scala 32:10] + node _T_520 = bits(_T_510, 3, 3) @[CircuitMath.scala 32:12] + node _T_522 = bits(_T_510, 2, 2) @[CircuitMath.scala 32:12] + node _T_524 = bits(_T_510, 1, 1) @[CircuitMath.scala 30:8] + node _T_525 = mux(_T_522, UInt<2>("h02"), _T_524) @[CircuitMath.scala 32:10] + node _T_526 = mux(_T_520, UInt<2>("h03"), _T_525) @[CircuitMath.scala 32:10] + node _T_527 = mux(_T_512, _T_519, _T_526) @[CircuitMath.scala 38:21] + node _T_528 = cat(_T_512, _T_527) @[Cat.scala 30:58] + node _T_529 = mux(_T_488, _T_508, _T_528) @[CircuitMath.scala 38:21] + node _T_530 = cat(_T_488, _T_529) @[Cat.scala 30:58] + node _T_531 = mux(_T_438, _T_484, _T_530) @[CircuitMath.scala 38:21] + node _T_532 = cat(_T_438, _T_531) @[Cat.scala 30:58] + node _T_533 = bits(_T_432, 31, 16) @[CircuitMath.scala 35:17] + node _T_534 = bits(_T_432, 15, 0) @[CircuitMath.scala 36:17] + node _T_536 = neq(_T_533, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_537 = bits(_T_533, 15, 8) @[CircuitMath.scala 35:17] + node _T_538 = bits(_T_533, 7, 0) @[CircuitMath.scala 36:17] + node _T_540 = neq(_T_537, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_541 = bits(_T_537, 7, 4) @[CircuitMath.scala 35:17] + node _T_542 = bits(_T_537, 3, 0) @[CircuitMath.scala 36:17] + node _T_544 = neq(_T_541, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_545 = bits(_T_541, 3, 3) @[CircuitMath.scala 32:12] + node _T_547 = bits(_T_541, 2, 2) @[CircuitMath.scala 32:12] + node _T_549 = bits(_T_541, 1, 1) @[CircuitMath.scala 30:8] + node _T_550 = mux(_T_547, UInt<2>("h02"), _T_549) @[CircuitMath.scala 32:10] + node _T_551 = mux(_T_545, UInt<2>("h03"), _T_550) @[CircuitMath.scala 32:10] + node _T_552 = bits(_T_542, 3, 3) @[CircuitMath.scala 32:12] + node _T_554 = bits(_T_542, 2, 2) @[CircuitMath.scala 32:12] + node _T_556 = bits(_T_542, 1, 1) @[CircuitMath.scala 30:8] + node _T_557 = mux(_T_554, UInt<2>("h02"), _T_556) @[CircuitMath.scala 32:10] + node _T_558 = mux(_T_552, UInt<2>("h03"), _T_557) @[CircuitMath.scala 32:10] + node _T_559 = mux(_T_544, _T_551, _T_558) @[CircuitMath.scala 38:21] + node _T_560 = cat(_T_544, _T_559) @[Cat.scala 30:58] + node _T_561 = bits(_T_538, 7, 4) @[CircuitMath.scala 35:17] + node _T_562 = bits(_T_538, 3, 0) @[CircuitMath.scala 36:17] + node _T_564 = neq(_T_561, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_565 = bits(_T_561, 3, 3) @[CircuitMath.scala 32:12] + node _T_567 = bits(_T_561, 2, 2) @[CircuitMath.scala 32:12] + node _T_569 = bits(_T_561, 1, 1) @[CircuitMath.scala 30:8] + node _T_570 = mux(_T_567, UInt<2>("h02"), _T_569) @[CircuitMath.scala 32:10] + node _T_571 = mux(_T_565, UInt<2>("h03"), _T_570) @[CircuitMath.scala 32:10] + node _T_572 = bits(_T_562, 3, 3) @[CircuitMath.scala 32:12] + node _T_574 = bits(_T_562, 2, 2) @[CircuitMath.scala 32:12] + node _T_576 = bits(_T_562, 1, 1) @[CircuitMath.scala 30:8] + node _T_577 = mux(_T_574, UInt<2>("h02"), _T_576) @[CircuitMath.scala 32:10] + node _T_578 = mux(_T_572, UInt<2>("h03"), _T_577) @[CircuitMath.scala 32:10] + node _T_579 = mux(_T_564, _T_571, _T_578) @[CircuitMath.scala 38:21] + node _T_580 = cat(_T_564, _T_579) @[Cat.scala 30:58] + node _T_581 = mux(_T_540, _T_560, _T_580) @[CircuitMath.scala 38:21] + node _T_582 = cat(_T_540, _T_581) @[Cat.scala 30:58] + node _T_583 = bits(_T_534, 15, 8) @[CircuitMath.scala 35:17] + node _T_584 = bits(_T_534, 7, 0) @[CircuitMath.scala 36:17] + node _T_586 = neq(_T_583, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_587 = bits(_T_583, 7, 4) @[CircuitMath.scala 35:17] + node _T_588 = bits(_T_583, 3, 0) @[CircuitMath.scala 36:17] + node _T_590 = neq(_T_587, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_591 = bits(_T_587, 3, 3) @[CircuitMath.scala 32:12] + node _T_593 = bits(_T_587, 2, 2) @[CircuitMath.scala 32:12] + node _T_595 = bits(_T_587, 1, 1) @[CircuitMath.scala 30:8] + node _T_596 = mux(_T_593, UInt<2>("h02"), _T_595) @[CircuitMath.scala 32:10] + node _T_597 = mux(_T_591, UInt<2>("h03"), _T_596) @[CircuitMath.scala 32:10] + node _T_598 = bits(_T_588, 3, 3) @[CircuitMath.scala 32:12] + node _T_600 = bits(_T_588, 2, 2) @[CircuitMath.scala 32:12] + node _T_602 = bits(_T_588, 1, 1) @[CircuitMath.scala 30:8] + node _T_603 = mux(_T_600, UInt<2>("h02"), _T_602) @[CircuitMath.scala 32:10] + node _T_604 = mux(_T_598, UInt<2>("h03"), _T_603) @[CircuitMath.scala 32:10] + node _T_605 = mux(_T_590, _T_597, _T_604) @[CircuitMath.scala 38:21] + node _T_606 = cat(_T_590, _T_605) @[Cat.scala 30:58] + node _T_607 = bits(_T_584, 7, 4) @[CircuitMath.scala 35:17] + node _T_608 = bits(_T_584, 3, 0) @[CircuitMath.scala 36:17] + node _T_610 = neq(_T_607, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_611 = bits(_T_607, 3, 3) @[CircuitMath.scala 32:12] + node _T_613 = bits(_T_607, 2, 2) @[CircuitMath.scala 32:12] + node _T_615 = bits(_T_607, 1, 1) @[CircuitMath.scala 30:8] + node _T_616 = mux(_T_613, UInt<2>("h02"), _T_615) @[CircuitMath.scala 32:10] + node _T_617 = mux(_T_611, UInt<2>("h03"), _T_616) @[CircuitMath.scala 32:10] + node _T_618 = bits(_T_608, 3, 3) @[CircuitMath.scala 32:12] + node _T_620 = bits(_T_608, 2, 2) @[CircuitMath.scala 32:12] + node _T_622 = bits(_T_608, 1, 1) @[CircuitMath.scala 30:8] + node _T_623 = mux(_T_620, UInt<2>("h02"), _T_622) @[CircuitMath.scala 32:10] + node _T_624 = mux(_T_618, UInt<2>("h03"), _T_623) @[CircuitMath.scala 32:10] + node _T_625 = mux(_T_610, _T_617, _T_624) @[CircuitMath.scala 38:21] + node _T_626 = cat(_T_610, _T_625) @[Cat.scala 30:58] + node _T_627 = mux(_T_586, _T_606, _T_626) @[CircuitMath.scala 38:21] + node _T_628 = cat(_T_586, _T_627) @[Cat.scala 30:58] + node _T_629 = mux(_T_536, _T_582, _T_628) @[CircuitMath.scala 38:21] + node _T_630 = cat(_T_536, _T_629) @[Cat.scala 30:58] + node _T_631 = mux(_T_434, _T_532, _T_630) @[CircuitMath.scala 38:21] + node _T_632 = cat(_T_434, _T_631) @[Cat.scala 30:58] + node _T_633 = not(_T_632) @[recFNFromFN.scala 56:13] + node _T_634 = dshl(_T_424, _T_633) @[recFNFromFN.scala 58:25] + node _T_635 = bits(_T_634, 50, 0) @[recFNFromFN.scala 58:37] + node _T_637 = cat(_T_635, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_642 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 71:12] + node _T_643 = xor(_T_633, _T_642) @[recFNFromFN.scala 62:27] + node _T_644 = mux(_T_426, _T_643, _T_423) @[recFNFromFN.scala 61:16] + node _T_648 = mux(_T_426, UInt<2>("h02"), UInt<1>("h01")) @[recFNFromFN.scala 64:47] + node _T_649 = or(UInt<11>("h0400"), _T_648) @[recFNFromFN.scala 64:42] + node _T_650 = add(_T_644, _T_649) @[recFNFromFN.scala 64:15] + node _T_651 = tail(_T_650, 1) @[recFNFromFN.scala 64:15] + node _T_652 = bits(_T_651, 11, 10) @[recFNFromFN.scala 67:25] + node _T_654 = eq(_T_652, UInt<2>("h03")) @[recFNFromFN.scala 67:50] + node _T_656 = eq(_T_428, UInt<1>("h00")) @[recFNFromFN.scala 68:17] + node _T_657 = and(_T_654, _T_656) @[recFNFromFN.scala 67:63] + node _T_658 = bits(_T_429, 0, 0) @[Bitwise.scala 71:15] + node _T_661 = mux(_T_658, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 71:12] + node _T_662 = shl(_T_661, 9) @[recFNFromFN.scala 71:45] + node _T_663 = not(_T_662) @[recFNFromFN.scala 71:28] + node _T_664 = and(_T_651, _T_663) @[recFNFromFN.scala 71:26] + node _T_665 = shl(_T_657, 9) @[recFNFromFN.scala 72:22] + node _T_666 = or(_T_664, _T_665) @[recFNFromFN.scala 71:64] + node _T_667 = mux(_T_426, _T_637, _T_424) @[recFNFromFN.scala 73:27] + node _T_668 = cat(_T_422, _T_666) @[Cat.scala 30:58] + node _T_669 = cat(_T_668, _T_667) @[Cat.scala 30:58] + mux.data <= _T_669 @[FPU.scala 364:14] + skip @[FPU.scala 363:41] + node _T_670 = asSInt(in.bits.in1) @[FPU.scala 370:39] + wire _T_671 : SInt + _T_671 is invalid + _T_671 <= _T_670 + node _T_672 = bits(in.bits.in1, 31, 0) @[FPU.scala 372:33] + node _T_673 = bits(in.bits.typ, 1, 1) @[Package.scala 44:13] + node _T_675 = eq(_T_673, UInt<1>("h00")) @[FPU.scala 373:49] + when _T_675 : @[FPU.scala 373:56] + node _T_676 = bits(in.bits.typ, 0, 0) @[FPU.scala 374:31] + node _T_677 = cvt(_T_672) @[FPU.scala 374:45] + node _T_678 = asSInt(_T_672) @[FPU.scala 374:60] + node _T_679 = mux(_T_676, _T_677, _T_678) @[FPU.scala 374:19] + _T_671 <= _T_679 @[FPU.scala 374:13] + skip @[FPU.scala 373:56] + node intValue = asUInt(_T_671) @[FPU.scala 377:9] + node _T_682 = and(in.bits.cmd, UInt<3>("h04")) @[FPU.scala 380:21] + node _T_683 = eq(UInt<1>("h00"), _T_682) @[FPU.scala 380:21] + when _T_683 : @[FPU.scala 380:38] + inst INToRecFN of INToRecFN @[FPU.scala 381:21] + INToRecFN.io is invalid + INToRecFN.clock <= clock + INToRecFN.reset <= reset + node _T_684 = bits(in.bits.typ, 0, 0) @[FPU.scala 382:36] + node _T_685 = not(_T_684) @[FPU.scala 382:24] + INToRecFN.io.signedIn <= _T_685 @[FPU.scala 382:21] + INToRecFN.io.in <= intValue @[FPU.scala 383:15] + INToRecFN.io.roundingMode <= in.bits.rm @[FPU.scala 384:25] + inst INToRecFN_1 of INToRecFN_1 @[FPU.scala 391:25] + INToRecFN_1.io is invalid + INToRecFN_1.clock <= clock + INToRecFN_1.reset <= reset + node _T_686 = bits(in.bits.typ, 0, 0) @[FPU.scala 392:40] + node _T_687 = not(_T_686) @[FPU.scala 392:28] + INToRecFN_1.io.signedIn <= _T_687 @[FPU.scala 392:25] + INToRecFN_1.io.in <= intValue @[FPU.scala 393:19] + INToRecFN_1.io.roundingMode <= in.bits.rm @[FPU.scala 394:29] + node _T_688 = shr(INToRecFN_1.io.out, 33) @[FPU.scala 396:36] + node _T_689 = cat(_T_688, INToRecFN.io.out) @[Cat.scala 30:58] + mux.data <= _T_689 @[FPU.scala 396:18] + mux.exc <= INToRecFN.io.exceptionFlags @[FPU.scala 397:17] + node _T_691 = eq(in.bits.single, UInt<1>("h00")) @[FPU.scala 398:15] + when _T_691 : @[FPU.scala 398:32] + mux.data <= INToRecFN_1.io.out @[FPU.scala 399:20] + mux.exc <= INToRecFN_1.io.exceptionFlags @[FPU.scala 400:19] + skip @[FPU.scala 398:32] + skip @[FPU.scala 380:38] + reg _T_694 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18] + _T_694 <= in.valid @[Valid.scala 47:18] + reg _T_698 : {data : UInt<65>, exc : UInt<5>}, clock @[Reg.scala 34:16] + when in.valid : @[Reg.scala 35:19] + _T_698 <- mux @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + wire _T_710 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} @[Valid.scala 42:21] + _T_710 is invalid @[Valid.scala 42:21] + _T_710.valid <= _T_694 @[Valid.scala 43:17] + _T_710.bits <- _T_698 @[Valid.scala 44:16] + io.out <- _T_710 @[FPU.scala 405:12] + + module FPToFP : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}, flip lt : UInt<1>} + + io is invalid + io is invalid + reg _T_134 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18] + _T_134 <= io.in.valid @[Valid.scala 47:18] + reg _T_157 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock @[Reg.scala 34:16] + when io.in.valid : @[Reg.scala 35:19] + _T_157 <- io.in.bits @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + wire in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} @[Valid.scala 42:21] + in is invalid @[Valid.scala 42:21] + in.valid <= _T_134 @[Valid.scala 43:17] + in.bits <- _T_157 @[Valid.scala 44:16] + node _T_272 = bits(in.bits.rm, 1, 1) @[FPU.scala 417:33] + node _T_273 = xor(in.bits.in1, in.bits.in2) @[FPU.scala 417:50] + node _T_274 = bits(in.bits.rm, 0, 0) @[FPU.scala 417:79] + node _T_275 = not(in.bits.in2) @[FPU.scala 417:84] + node _T_276 = mux(_T_274, _T_275, in.bits.in2) @[FPU.scala 417:68] + node signNum = mux(_T_272, _T_273, _T_276) @[FPU.scala 417:22] + node _T_277 = bits(signNum, 32, 32) @[FPU.scala 418:30] + node _T_278 = bits(in.bits.in1, 31, 0) @[FPU.scala 418:47] + node fsgnj_s = cat(_T_277, _T_278) @[Cat.scala 30:58] + node _T_279 = shr(in.bits.in1, 33) @[FPU.scala 421:54] + node _T_280 = cat(_T_279, fsgnj_s) @[Cat.scala 30:58] + node _T_281 = bits(signNum, 64, 64) @[FPU.scala 422:49] + node _T_282 = bits(in.bits.in1, 63, 0) @[FPU.scala 422:66] + node _T_283 = cat(_T_281, _T_282) @[Cat.scala 30:58] + node fsgnj = mux(in.bits.single, _T_280, _T_283) @[FPU.scala 421:21] + wire mux : {data : UInt<65>, exc : UInt<5>} @[FPU.scala 424:19] + mux is invalid @[FPU.scala 424:19] + mux.exc <= UInt<1>("h00") @[FPU.scala 425:13] + mux.data <= fsgnj @[FPU.scala 426:14] + node _T_292 = and(in.bits.cmd, UInt<4>("h0d")) @[FPU.scala 428:23] + node _T_293 = eq(UInt<3>("h05"), _T_292) @[FPU.scala 428:23] + when _T_293 : @[FPU.scala 428:40] + node _T_294 = bits(in.bits.in1, 31, 29) @[FPU.scala 226:7] + node _T_295 = not(_T_294) @[FPU.scala 226:58] + node _T_297 = eq(_T_295, UInt<1>("h00")) @[FPU.scala 226:58] + node _T_298 = bits(in.bits.in2, 31, 29) @[FPU.scala 226:7] + node _T_299 = not(_T_298) @[FPU.scala 226:58] + node _T_301 = eq(_T_299, UInt<1>("h00")) @[FPU.scala 226:58] + node _T_302 = bits(in.bits.in1, 31, 29) @[FPU.scala 226:7] + node _T_303 = not(_T_302) @[FPU.scala 226:58] + node _T_305 = eq(_T_303, UInt<1>("h00")) @[FPU.scala 226:58] + node _T_306 = bits(in.bits.in1, 22, 22) @[FPU.scala 231:46] + node _T_308 = eq(_T_306, UInt<1>("h00")) @[FPU.scala 231:43] + node _T_309 = and(_T_305, _T_308) @[FPU.scala 231:40] + node _T_310 = bits(in.bits.in2, 31, 29) @[FPU.scala 226:7] + node _T_311 = not(_T_310) @[FPU.scala 226:58] + node _T_313 = eq(_T_311, UInt<1>("h00")) @[FPU.scala 226:58] + node _T_314 = bits(in.bits.in2, 22, 22) @[FPU.scala 231:46] + node _T_316 = eq(_T_314, UInt<1>("h00")) @[FPU.scala 231:43] + node _T_317 = and(_T_313, _T_316) @[FPU.scala 231:40] + node _T_318 = or(_T_309, _T_317) @[FPU.scala 434:31] + node _T_319 = and(_T_297, _T_301) @[FPU.scala 435:43] + node _T_320 = or(_T_318, _T_319) @[FPU.scala 435:32] + node _T_323 = add(UInt<33>("h0e0400000"), UInt<65>("h0e008000000000000")) @[FPU.scala 436:100] + node _T_324 = tail(_T_323, 1) @[FPU.scala 436:100] + node _T_325 = bits(in.bits.rm, 0, 0) @[FPU.scala 437:30] + node _T_326 = neq(_T_325, io.lt) @[FPU.scala 437:34] + node _T_328 = eq(_T_297, UInt<1>("h00")) @[FPU.scala 437:47] + node _T_329 = and(_T_326, _T_328) @[FPU.scala 437:44] + node _T_330 = or(_T_301, _T_329) @[FPU.scala 437:17] + node _T_331 = bits(in.bits.in1, 63, 61) @[FPU.scala 226:7] + node _T_332 = not(_T_331) @[FPU.scala 226:58] + node _T_334 = eq(_T_332, UInt<1>("h00")) @[FPU.scala 226:58] + node _T_335 = bits(in.bits.in2, 63, 61) @[FPU.scala 226:7] + node _T_336 = not(_T_335) @[FPU.scala 226:58] + node _T_338 = eq(_T_336, UInt<1>("h00")) @[FPU.scala 226:58] + node _T_339 = bits(in.bits.in1, 63, 61) @[FPU.scala 226:7] + node _T_340 = not(_T_339) @[FPU.scala 226:58] + node _T_342 = eq(_T_340, UInt<1>("h00")) @[FPU.scala 226:58] + node _T_343 = bits(in.bits.in1, 51, 51) @[FPU.scala 231:46] + node _T_345 = eq(_T_343, UInt<1>("h00")) @[FPU.scala 231:43] + node _T_346 = and(_T_342, _T_345) @[FPU.scala 231:40] + node _T_347 = bits(in.bits.in2, 63, 61) @[FPU.scala 226:7] + node _T_348 = not(_T_347) @[FPU.scala 226:58] + node _T_350 = eq(_T_348, UInt<1>("h00")) @[FPU.scala 226:58] + node _T_351 = bits(in.bits.in2, 51, 51) @[FPU.scala 231:46] + node _T_353 = eq(_T_351, UInt<1>("h00")) @[FPU.scala 231:43] + node _T_354 = and(_T_350, _T_353) @[FPU.scala 231:40] + node _T_355 = or(_T_346, _T_354) @[FPU.scala 434:31] + node _T_356 = and(_T_334, _T_338) @[FPU.scala 435:43] + node _T_357 = or(_T_355, _T_356) @[FPU.scala 435:32] + node _T_359 = bits(in.bits.rm, 0, 0) @[FPU.scala 437:30] + node _T_360 = neq(_T_359, io.lt) @[FPU.scala 437:34] + node _T_362 = eq(_T_334, UInt<1>("h00")) @[FPU.scala 437:47] + node _T_363 = and(_T_360, _T_362) @[FPU.scala 437:44] + node _T_364 = or(_T_338, _T_363) @[FPU.scala 437:17] + node _T_365 = mux(in.bits.single, _T_330, _T_364) @[Misc.scala 42:9] + node _T_366 = mux(in.bits.single, _T_318, _T_355) @[Misc.scala 42:36] + node _T_367 = mux(in.bits.single, _T_320, _T_357) @[Misc.scala 42:63] + node _T_368 = mux(in.bits.single, _T_324, UInt<65>("h0e008000000000000")) @[Misc.scala 42:90] + node _T_369 = shl(_T_366, 4) @[FPU.scala 443:28] + mux.exc <= _T_369 @[FPU.scala 443:15] + node _T_370 = mux(_T_365, in.bits.in1, in.bits.in2) @[FPU.scala 444:42] + node _T_371 = mux(_T_367, _T_368, _T_370) @[FPU.scala 444:22] + mux.data <= _T_371 @[FPU.scala 444:16] + skip @[FPU.scala 428:40] + node _T_374 = and(in.bits.cmd, UInt<3>("h04")) @[FPU.scala 450:25] + node _T_375 = eq(UInt<1>("h00"), _T_374) @[FPU.scala 450:25] + when _T_375 : @[FPU.scala 450:42] + inst RecFNToRecFN of RecFNToRecFN @[FPU.scala 451:25] + RecFNToRecFN.io is invalid + RecFNToRecFN.clock <= clock + RecFNToRecFN.reset <= reset + RecFNToRecFN.io.in <= in.bits.in1 @[FPU.scala 452:19] + RecFNToRecFN.io.roundingMode <= in.bits.rm @[FPU.scala 453:29] + inst RecFNToRecFN_1 of RecFNToRecFN_1 @[FPU.scala 455:25] + RecFNToRecFN_1.io is invalid + RecFNToRecFN_1.clock <= clock + RecFNToRecFN_1.reset <= reset + RecFNToRecFN_1.io.in <= in.bits.in1 @[FPU.scala 456:19] + RecFNToRecFN_1.io.roundingMode <= in.bits.rm @[FPU.scala 457:29] + when in.bits.single : @[FPU.scala 459:31] + node _T_376 = shr(RecFNToRecFN_1.io.out, 33) @[FPU.scala 460:38] + node _T_377 = cat(_T_376, RecFNToRecFN.io.out) @[Cat.scala 30:58] + mux.data <= _T_377 @[FPU.scala 460:20] + mux.exc <= RecFNToRecFN.io.exceptionFlags @[FPU.scala 461:19] + skip @[FPU.scala 459:31] + node _T_379 = eq(in.bits.single, UInt<1>("h00")) @[FPU.scala 459:31] + when _T_379 : @[FPU.scala 462:21] + mux.data <= RecFNToRecFN_1.io.out @[FPU.scala 463:20] + mux.exc <= RecFNToRecFN_1.io.exceptionFlags @[FPU.scala 464:19] + skip @[FPU.scala 462:21] + skip @[FPU.scala 450:42] + reg _T_382 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18] + _T_382 <= in.valid @[Valid.scala 47:18] + reg _T_386 : {data : UInt<65>, exc : UInt<5>}, clock @[Reg.scala 34:16] + when in.valid : @[Reg.scala 35:19] + _T_386 <- mux @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + wire _T_398 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} @[Valid.scala 42:21] + _T_398 is invalid @[Valid.scala 42:21] + _T_398.valid <= _T_382 @[Valid.scala 43:17] + _T_398.bits <- _T_386 @[Valid.scala 44:16] + io.out <- _T_398 @[FPU.scala 469:10] + + module FPUFMAPipe_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} + + io is invalid + io is invalid + node one = shl(UInt<1>("h01"), 63) @[FPU.scala 479:21] + node _T_131 = bits(io.in.bits.in1, 64, 64) @[FPU.scala 480:29] + node _T_132 = bits(io.in.bits.in2, 64, 64) @[FPU.scala 480:53] + node _T_133 = xor(_T_131, _T_132) @[FPU.scala 480:37] + node zero = shl(_T_133, 64) @[FPU.scala 480:62] + reg valid : UInt<1>, clock @[FPU.scala 482:18] + valid <= io.in.valid @[FPU.scala 482:18] + reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock @[FPU.scala 483:15] + when io.in.valid : @[FPU.scala 484:22] + in <- io.in.bits @[FPU.scala 485:8] + node _T_177 = bits(io.in.bits.cmd, 1, 1) @[FPU.scala 488:33] + node _T_178 = or(io.in.bits.ren3, io.in.bits.swap23) @[FPU.scala 488:48] + node _T_179 = and(_T_177, _T_178) @[FPU.scala 488:37] + node _T_180 = bits(io.in.bits.cmd, 0, 0) @[FPU.scala 488:78] + node _T_181 = cat(_T_179, _T_180) @[Cat.scala 30:58] + in.cmd <= _T_181 @[FPU.scala 488:12] + when io.in.bits.swap23 : @[FPU.scala 489:23] + in.in2 <= one @[FPU.scala 489:32] + skip @[FPU.scala 489:23] + node _T_182 = or(io.in.bits.ren3, io.in.bits.swap23) @[FPU.scala 490:21] + node _T_184 = eq(_T_182, UInt<1>("h00")) @[Conditional.scala 19:11] + when _T_184 : @[Conditional.scala 19:15] + in.in3 <= zero @[FPU.scala 490:45] + skip @[Conditional.scala 19:15] + skip @[FPU.scala 484:22] + inst fma of MulAddRecFN_1 @[FPU.scala 493:19] + fma.io is invalid + fma.clock <= clock + fma.reset <= reset + fma.io.op <= in.cmd @[FPU.scala 494:13] + fma.io.roundingMode <= in.rm @[FPU.scala 495:23] + fma.io.a <= in.in1 @[FPU.scala 496:12] + fma.io.b <= in.in2 @[FPU.scala 497:12] + fma.io.c <= in.in3 @[FPU.scala 498:12] + wire res : {data : UInt<65>, exc : UInt<5>} @[FPU.scala 500:17] + res is invalid @[FPU.scala 500:17] + res.data <= fma.io.out @[FPU.scala 501:12] + res.exc <= fma.io.exceptionFlags @[FPU.scala 502:11] + reg _T_192 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18] + _T_192 <= valid @[Valid.scala 47:18] + reg _T_196 : {data : UInt<65>, exc : UInt<5>}, clock @[Reg.scala 34:16] + when valid : @[Reg.scala 35:19] + _T_196 <- res @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg _T_201 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18] + _T_201 <= _T_192 @[Valid.scala 47:18] + reg _T_205 : {data : UInt<65>, exc : UInt<5>}, clock @[Reg.scala 34:16] + when _T_192 : @[Reg.scala 35:19] + _T_205 <- _T_196 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + reg _T_210 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18] + _T_210 <= _T_201 @[Valid.scala 47:18] + reg _T_214 : {data : UInt<65>, exc : UInt<5>}, clock @[Reg.scala 34:16] + when _T_201 : @[Reg.scala 35:19] + _T_214 <- _T_205 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + wire _T_226 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} @[Valid.scala 42:21] + _T_226 is invalid @[Valid.scala 42:21] + _T_226.valid <= _T_210 @[Valid.scala 43:17] + _T_226.bits <- _T_214 @[Valid.scala 44:16] + io.out <- _T_226 @[FPU.scala 503:10] + + module DivSqrtRecF64 : + input clock : Clock + input reset : UInt<1> + output io : {inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + inst ds of DivSqrtRecF64_mulAddZ31 @[DivSqrtRecF64.scala 59:20] + ds.io is invalid + ds.clock <= clock + ds.reset <= reset + io.inReady_div <= ds.io.inReady_div @[DivSqrtRecF64.scala 61:20] + io.inReady_sqrt <= ds.io.inReady_sqrt @[DivSqrtRecF64.scala 62:21] + ds.io.inValid <= io.inValid @[DivSqrtRecF64.scala 63:19] + ds.io.sqrtOp <= io.sqrtOp @[DivSqrtRecF64.scala 64:18] + ds.io.a <= io.a @[DivSqrtRecF64.scala 65:13] + ds.io.b <= io.b @[DivSqrtRecF64.scala 66:13] + ds.io.roundingMode <= io.roundingMode @[DivSqrtRecF64.scala 67:24] + io.outValid_div <= ds.io.outValid_div @[DivSqrtRecF64.scala 68:21] + io.outValid_sqrt <= ds.io.outValid_sqrt @[DivSqrtRecF64.scala 69:22] + io.out <= ds.io.out @[DivSqrtRecF64.scala 70:12] + io.exceptionFlags <= ds.io.exceptionFlags @[DivSqrtRecF64.scala 71:23] + inst mul of Mul54 @[DivSqrtRecF64.scala 73:21] + mul.io is invalid + mul.clock <= clock + mul.reset <= reset + node _T_24 = bits(ds.io.usingMulAdd, 0, 0) @[DivSqrtRecF64.scala 75:39] + mul.io.val_s0 <= _T_24 @[DivSqrtRecF64.scala 75:19] + mul.io.latch_a_s0 <= ds.io.latchMulAddA_0 @[DivSqrtRecF64.scala 76:23] + mul.io.a_s0 <= ds.io.mulAddA_0 @[DivSqrtRecF64.scala 77:17] + mul.io.latch_b_s0 <= ds.io.latchMulAddB_0 @[DivSqrtRecF64.scala 78:23] + mul.io.b_s0 <= ds.io.mulAddB_0 @[DivSqrtRecF64.scala 79:17] + mul.io.c_s2 <= ds.io.mulAddC_2 @[DivSqrtRecF64.scala 80:17] + ds.io.mulAddResult_3 <= mul.io.result_s3 @[DivSqrtRecF64.scala 81:26] + + module RecFNToRecFN_2 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + node _T_10 = bits(io.in, 63, 52) @[rawFNFromRecFN.scala 50:21] + node _T_11 = bits(_T_10, 11, 9) @[rawFNFromRecFN.scala 51:29] + node _T_13 = eq(_T_11, UInt<1>("h00")) @[rawFNFromRecFN.scala 51:54] + node _T_14 = bits(_T_10, 11, 10) @[rawFNFromRecFN.scala 52:29] + node _T_16 = eq(_T_14, UInt<2>("h03")) @[rawFNFromRecFN.scala 52:54] + wire _T_24 : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} @[rawFNFromRecFN.scala 54:23] + _T_24 is invalid @[rawFNFromRecFN.scala 54:23] + node _T_31 = bits(io.in, 64, 64) @[rawFNFromRecFN.scala 55:23] + _T_24.sign <= _T_31 @[rawFNFromRecFN.scala 55:18] + node _T_32 = bits(_T_10, 9, 9) @[rawFNFromRecFN.scala 56:40] + node _T_33 = and(_T_16, _T_32) @[rawFNFromRecFN.scala 56:32] + _T_24.isNaN <= _T_33 @[rawFNFromRecFN.scala 56:19] + node _T_34 = bits(_T_10, 9, 9) @[rawFNFromRecFN.scala 57:40] + node _T_36 = eq(_T_34, UInt<1>("h00")) @[rawFNFromRecFN.scala 57:35] + node _T_37 = and(_T_16, _T_36) @[rawFNFromRecFN.scala 57:32] + _T_24.isInf <= _T_37 @[rawFNFromRecFN.scala 57:19] + _T_24.isZero <= _T_13 @[rawFNFromRecFN.scala 58:20] + node _T_38 = cvt(_T_10) @[rawFNFromRecFN.scala 59:25] + _T_24.sExp <= _T_38 @[rawFNFromRecFN.scala 59:18] + node _T_41 = eq(_T_13, UInt<1>("h00")) @[rawFNFromRecFN.scala 60:36] + node _T_42 = bits(io.in, 51, 0) @[rawFNFromRecFN.scala 60:48] + node _T_44 = cat(_T_42, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_45 = cat(UInt<1>("h00"), _T_41) @[Cat.scala 30:58] + node _T_46 = cat(_T_45, _T_44) @[Cat.scala 30:58] + _T_24.sig <= _T_46 @[rawFNFromRecFN.scala 60:17] + node _T_48 = add(_T_24.sExp, asSInt(UInt<12>("h0900"))) @[resizeRawFN.scala 49:31] + wire outRawFloat : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} @[resizeRawFN.scala 51:23] + outRawFloat is invalid @[resizeRawFN.scala 51:23] + outRawFloat.sign <= _T_24.sign @[resizeRawFN.scala 52:20] + outRawFloat.isNaN <= _T_24.isNaN @[resizeRawFN.scala 53:20] + outRawFloat.isInf <= _T_24.isInf @[resizeRawFN.scala 54:20] + outRawFloat.isZero <= _T_24.isZero @[resizeRawFN.scala 55:20] + node _T_63 = lt(_T_48, asSInt(UInt<1>("h00"))) @[resizeRawFN.scala 60:31] + node _T_64 = bits(_T_48, 12, 9) @[resizeRawFN.scala 61:33] + node _T_66 = neq(_T_64, UInt<1>("h00")) @[resizeRawFN.scala 61:65] + node _T_71 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12] + node _T_73 = cat(_T_71, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_74 = bits(_T_48, 8, 0) @[resizeRawFN.scala 63:33] + node _T_75 = mux(_T_66, _T_73, _T_74) @[resizeRawFN.scala 61:25] + node _T_76 = cat(_T_63, _T_75) @[Cat.scala 30:58] + node _T_77 = asSInt(_T_76) @[resizeRawFN.scala 65:20] + outRawFloat.sExp <= _T_77 @[resizeRawFN.scala 56:18] + node _T_78 = bits(_T_24.sig, 55, 30) @[resizeRawFN.scala 71:28] + node _T_79 = bits(_T_24.sig, 29, 0) @[resizeRawFN.scala 72:28] + node _T_81 = neq(_T_79, UInt<1>("h00")) @[resizeRawFN.scala 72:56] + node _T_82 = cat(_T_78, _T_81) @[Cat.scala 30:58] + outRawFloat.sig <= _T_82 @[resizeRawFN.scala 67:17] + node _T_83 = bits(outRawFloat.sig, 24, 24) @[RoundRawFNToRecFN.scala 61:57] + node _T_85 = eq(_T_83, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 61:49] + node invalidExc = and(outRawFloat.isNaN, _T_85) @[RoundRawFNToRecFN.scala 61:46] + inst RoundRawFNToRecFN of RoundRawFNToRecFN_1 @[RecFNToRecFN.scala 102:19] + RoundRawFNToRecFN.io is invalid + RoundRawFNToRecFN.clock <= clock + RoundRawFNToRecFN.reset <= reset + RoundRawFNToRecFN.io.invalidExc <= invalidExc @[RecFNToRecFN.scala 103:41] + RoundRawFNToRecFN.io.infiniteExc <= UInt<1>("h00") @[RecFNToRecFN.scala 104:42] + RoundRawFNToRecFN.io.in <- outRawFloat @[RecFNToRecFN.scala 105:33] + RoundRawFNToRecFN.io.roundingMode <= io.roundingMode @[RecFNToRecFN.scala 106:43] + io.out <= RoundRawFNToRecFN.io.out @[RecFNToRecFN.scala 107:16] + io.exceptionFlags <= RoundRawFNToRecFN.io.exceptionFlags @[RecFNToRecFN.scala 108:27] + + module MulAddRecFN : + input clock : Clock + input reset : UInt<1> + output io : {flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + inst mulAddRecFN_preMul of MulAddRecFN_preMul @[MulAddRecFN.scala 598:15] + mulAddRecFN_preMul.io is invalid + mulAddRecFN_preMul.clock <= clock + mulAddRecFN_preMul.reset <= reset + inst mulAddRecFN_postMul of MulAddRecFN_postMul @[MulAddRecFN.scala 600:15] + mulAddRecFN_postMul.io is invalid + mulAddRecFN_postMul.clock <= clock + mulAddRecFN_postMul.reset <= reset + mulAddRecFN_preMul.io.op <= io.op @[MulAddRecFN.scala 602:30] + mulAddRecFN_preMul.io.a <= io.a @[MulAddRecFN.scala 603:30] + mulAddRecFN_preMul.io.b <= io.b @[MulAddRecFN.scala 604:30] + mulAddRecFN_preMul.io.c <= io.c @[MulAddRecFN.scala 605:30] + mulAddRecFN_preMul.io.roundingMode <= io.roundingMode @[MulAddRecFN.scala 606:40] + mulAddRecFN_postMul.io.fromPreMul <- mulAddRecFN_preMul.io.toPostMul @[MulAddRecFN.scala 608:39] + node _T_16 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB) @[MulAddRecFN.scala 610:39] + node _T_18 = cat(UInt<1>("h00"), mulAddRecFN_preMul.io.mulAddC) @[Cat.scala 30:58] + node _T_19 = add(_T_16, _T_18) @[MulAddRecFN.scala 610:71] + node _T_20 = tail(_T_19, 1) @[MulAddRecFN.scala 610:71] + mulAddRecFN_postMul.io.mulAddResult <= _T_20 @[MulAddRecFN.scala 609:41] + io.out <= mulAddRecFN_postMul.io.out @[MulAddRecFN.scala 613:12] + io.exceptionFlags <= mulAddRecFN_postMul.io.exceptionFlags @[MulAddRecFN.scala 614:23] + + module CompareRecFN : + input clock : Clock + input reset : UInt<1> + output io : {flip a : UInt<65>, flip b : UInt<65>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + node _T_16 = bits(io.a, 63, 52) @[rawFNFromRecFN.scala 50:21] + node _T_17 = bits(_T_16, 11, 9) @[rawFNFromRecFN.scala 51:29] + node _T_19 = eq(_T_17, UInt<1>("h00")) @[rawFNFromRecFN.scala 51:54] + node _T_20 = bits(_T_16, 11, 10) @[rawFNFromRecFN.scala 52:29] + node _T_22 = eq(_T_20, UInt<2>("h03")) @[rawFNFromRecFN.scala 52:54] + wire rawA : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} @[rawFNFromRecFN.scala 54:23] + rawA is invalid @[rawFNFromRecFN.scala 54:23] + node _T_36 = bits(io.a, 64, 64) @[rawFNFromRecFN.scala 55:23] + rawA.sign <= _T_36 @[rawFNFromRecFN.scala 55:18] + node _T_37 = bits(_T_16, 9, 9) @[rawFNFromRecFN.scala 56:40] + node _T_38 = and(_T_22, _T_37) @[rawFNFromRecFN.scala 56:32] + rawA.isNaN <= _T_38 @[rawFNFromRecFN.scala 56:19] + node _T_39 = bits(_T_16, 9, 9) @[rawFNFromRecFN.scala 57:40] + node _T_41 = eq(_T_39, UInt<1>("h00")) @[rawFNFromRecFN.scala 57:35] + node _T_42 = and(_T_22, _T_41) @[rawFNFromRecFN.scala 57:32] + rawA.isInf <= _T_42 @[rawFNFromRecFN.scala 57:19] + rawA.isZero <= _T_19 @[rawFNFromRecFN.scala 58:20] + node _T_43 = cvt(_T_16) @[rawFNFromRecFN.scala 59:25] + rawA.sExp <= _T_43 @[rawFNFromRecFN.scala 59:18] + node _T_46 = eq(_T_19, UInt<1>("h00")) @[rawFNFromRecFN.scala 60:36] + node _T_47 = bits(io.a, 51, 0) @[rawFNFromRecFN.scala 60:48] + node _T_49 = cat(_T_47, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_50 = cat(UInt<1>("h00"), _T_46) @[Cat.scala 30:58] + node _T_51 = cat(_T_50, _T_49) @[Cat.scala 30:58] + rawA.sig <= _T_51 @[rawFNFromRecFN.scala 60:17] + node _T_52 = bits(io.b, 63, 52) @[rawFNFromRecFN.scala 50:21] + node _T_53 = bits(_T_52, 11, 9) @[rawFNFromRecFN.scala 51:29] + node _T_55 = eq(_T_53, UInt<1>("h00")) @[rawFNFromRecFN.scala 51:54] + node _T_56 = bits(_T_52, 11, 10) @[rawFNFromRecFN.scala 52:29] + node _T_58 = eq(_T_56, UInt<2>("h03")) @[rawFNFromRecFN.scala 52:54] + wire rawB : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} @[rawFNFromRecFN.scala 54:23] + rawB is invalid @[rawFNFromRecFN.scala 54:23] + node _T_72 = bits(io.b, 64, 64) @[rawFNFromRecFN.scala 55:23] + rawB.sign <= _T_72 @[rawFNFromRecFN.scala 55:18] + node _T_73 = bits(_T_52, 9, 9) @[rawFNFromRecFN.scala 56:40] + node _T_74 = and(_T_58, _T_73) @[rawFNFromRecFN.scala 56:32] + rawB.isNaN <= _T_74 @[rawFNFromRecFN.scala 56:19] + node _T_75 = bits(_T_52, 9, 9) @[rawFNFromRecFN.scala 57:40] + node _T_77 = eq(_T_75, UInt<1>("h00")) @[rawFNFromRecFN.scala 57:35] + node _T_78 = and(_T_58, _T_77) @[rawFNFromRecFN.scala 57:32] + rawB.isInf <= _T_78 @[rawFNFromRecFN.scala 57:19] + rawB.isZero <= _T_55 @[rawFNFromRecFN.scala 58:20] + node _T_79 = cvt(_T_52) @[rawFNFromRecFN.scala 59:25] + rawB.sExp <= _T_79 @[rawFNFromRecFN.scala 59:18] + node _T_82 = eq(_T_55, UInt<1>("h00")) @[rawFNFromRecFN.scala 60:36] + node _T_83 = bits(io.b, 51, 0) @[rawFNFromRecFN.scala 60:48] + node _T_85 = cat(_T_83, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_86 = cat(UInt<1>("h00"), _T_82) @[Cat.scala 30:58] + node _T_87 = cat(_T_86, _T_85) @[Cat.scala 30:58] + rawB.sig <= _T_87 @[rawFNFromRecFN.scala 60:17] + node _T_89 = eq(rawA.isNaN, UInt<1>("h00")) @[CompareRecFN.scala 57:19] + node _T_91 = eq(rawB.isNaN, UInt<1>("h00")) @[CompareRecFN.scala 57:35] + node ordered = and(_T_89, _T_91) @[CompareRecFN.scala 57:32] + node bothInfs = and(rawA.isInf, rawB.isInf) @[CompareRecFN.scala 58:33] + node bothZeros = and(rawA.isZero, rawB.isZero) @[CompareRecFN.scala 59:33] + node eqExps = eq(rawA.sExp, rawB.sExp) @[CompareRecFN.scala 60:29] + node _T_92 = lt(rawA.sExp, rawB.sExp) @[CompareRecFN.scala 62:20] + node _T_93 = lt(rawA.sig, rawB.sig) @[CompareRecFN.scala 62:57] + node _T_94 = and(eqExps, _T_93) @[CompareRecFN.scala 62:44] + node common_ltMags = or(_T_92, _T_94) @[CompareRecFN.scala 62:33] + node _T_95 = eq(rawA.sig, rawB.sig) @[CompareRecFN.scala 63:45] + node common_eqMags = and(eqExps, _T_95) @[CompareRecFN.scala 63:32] + node _T_97 = eq(bothZeros, UInt<1>("h00")) @[CompareRecFN.scala 66:9] + node _T_99 = eq(rawB.sign, UInt<1>("h00")) @[CompareRecFN.scala 67:28] + node _T_100 = and(rawA.sign, _T_99) @[CompareRecFN.scala 67:25] + node _T_102 = eq(bothInfs, UInt<1>("h00")) @[CompareRecFN.scala 68:19] + node _T_104 = eq(common_ltMags, UInt<1>("h00")) @[CompareRecFN.scala 69:38] + node _T_105 = and(rawA.sign, _T_104) @[CompareRecFN.scala 69:35] + node _T_107 = eq(common_eqMags, UInt<1>("h00")) @[CompareRecFN.scala 69:57] + node _T_108 = and(_T_105, _T_107) @[CompareRecFN.scala 69:54] + node _T_110 = eq(rawB.sign, UInt<1>("h00")) @[CompareRecFN.scala 70:29] + node _T_111 = and(_T_110, common_ltMags) @[CompareRecFN.scala 70:41] + node _T_112 = or(_T_108, _T_111) @[CompareRecFN.scala 69:74] + node _T_113 = and(_T_102, _T_112) @[CompareRecFN.scala 68:30] + node _T_114 = or(_T_100, _T_113) @[CompareRecFN.scala 67:41] + node ordered_lt = and(_T_97, _T_114) @[CompareRecFN.scala 66:21] + node _T_115 = eq(rawA.sign, rawB.sign) @[CompareRecFN.scala 72:34] + node _T_116 = or(bothInfs, common_eqMags) @[CompareRecFN.scala 72:62] + node _T_117 = and(_T_115, _T_116) @[CompareRecFN.scala 72:49] + node ordered_eq = or(bothZeros, _T_117) @[CompareRecFN.scala 72:19] + node _T_118 = bits(rawA.sig, 53, 53) @[RoundRawFNToRecFN.scala 61:57] + node _T_120 = eq(_T_118, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 61:49] + node _T_121 = and(rawA.isNaN, _T_120) @[RoundRawFNToRecFN.scala 61:46] + node _T_122 = bits(rawB.sig, 53, 53) @[RoundRawFNToRecFN.scala 61:57] + node _T_124 = eq(_T_122, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 61:49] + node _T_125 = and(rawB.isNaN, _T_124) @[RoundRawFNToRecFN.scala 61:46] + node _T_126 = or(_T_121, _T_125) @[CompareRecFN.scala 75:29] + node _T_128 = eq(ordered, UInt<1>("h00")) @[CompareRecFN.scala 76:30] + node _T_129 = and(io.signaling, _T_128) @[CompareRecFN.scala 76:27] + node invalid = or(_T_126, _T_129) @[CompareRecFN.scala 75:52] + node _T_130 = and(ordered, ordered_lt) @[CompareRecFN.scala 78:22] + io.lt <= _T_130 @[CompareRecFN.scala 78:11] + node _T_131 = and(ordered, ordered_eq) @[CompareRecFN.scala 79:22] + io.eq <= _T_131 @[CompareRecFN.scala 79:11] + node _T_133 = eq(ordered_lt, UInt<1>("h00")) @[CompareRecFN.scala 80:25] + node _T_134 = and(ordered, _T_133) @[CompareRecFN.scala 80:22] + node _T_136 = eq(ordered_eq, UInt<1>("h00")) @[CompareRecFN.scala 80:41] + node _T_137 = and(_T_134, _T_136) @[CompareRecFN.scala 80:38] + io.gt <= _T_137 @[CompareRecFN.scala 80:11] + node _T_139 = cat(invalid, UInt<4>("h00")) @[Cat.scala 30:58] + io.exceptionFlags <= _T_139 @[CompareRecFN.scala 82:23] + + module RecFNToIN : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, flip signedOut : UInt<1>, out : UInt<32>, intExceptionFlags : UInt<3>} + + io is invalid + io is invalid + node sign = bits(io.in, 64, 64) @[RecFNToIN.scala 54:21] + node exp = bits(io.in, 63, 52) @[RecFNToIN.scala 55:20] + node fract = bits(io.in, 51, 0) @[RecFNToIN.scala 56:22] + node _T_12 = bits(exp, 11, 9) @[RecFNToIN.scala 58:22] + node isZero = eq(_T_12, UInt<1>("h00")) @[RecFNToIN.scala 58:47] + node _T_14 = bits(exp, 11, 10) @[RecFNToIN.scala 59:25] + node invalid = eq(_T_14, UInt<2>("h03")) @[RecFNToIN.scala 59:50] + node _T_16 = bits(exp, 9, 9) @[RecFNToIN.scala 60:33] + node isNaN = and(invalid, _T_16) @[RecFNToIN.scala 60:27] + node notSpecial_magGeOne = bits(exp, 11, 11) @[RecFNToIN.scala 61:34] + node _T_17 = cat(notSpecial_magGeOne, fract) @[Cat.scala 30:58] + node _T_18 = bits(exp, 4, 0) @[RecFNToIN.scala 74:20] + node _T_20 = mux(notSpecial_magGeOne, _T_18, UInt<1>("h00")) @[RecFNToIN.scala 73:16] + node shiftedSig = dshl(_T_17, _T_20) @[RecFNToIN.scala 72:40] + node unroundedInt = bits(shiftedSig, 83, 52) @[RecFNToIN.scala 82:24] + node _T_21 = bits(shiftedSig, 52, 51) @[RecFNToIN.scala 85:23] + node _T_22 = bits(shiftedSig, 50, 0) @[RecFNToIN.scala 86:23] + node _T_24 = neq(_T_22, UInt<1>("h00")) @[RecFNToIN.scala 86:41] + node roundBits = cat(_T_21, _T_24) @[Cat.scala 30:58] + node _T_25 = bits(roundBits, 1, 0) @[RecFNToIN.scala 88:58] + node _T_27 = neq(_T_25, UInt<1>("h00")) @[RecFNToIN.scala 88:65] + node _T_29 = eq(isZero, UInt<1>("h00")) @[RecFNToIN.scala 88:70] + node roundInexact = mux(notSpecial_magGeOne, _T_27, _T_29) @[RecFNToIN.scala 88:27] + node _T_30 = bits(roundBits, 2, 1) @[RecFNToIN.scala 91:22] + node _T_31 = not(_T_30) @[RecFNToIN.scala 91:29] + node _T_33 = eq(_T_31, UInt<1>("h00")) @[RecFNToIN.scala 91:29] + node _T_34 = bits(roundBits, 1, 0) @[RecFNToIN.scala 91:46] + node _T_35 = not(_T_34) @[RecFNToIN.scala 91:53] + node _T_37 = eq(_T_35, UInt<1>("h00")) @[RecFNToIN.scala 91:53] + node _T_38 = or(_T_33, _T_37) @[RecFNToIN.scala 91:34] + node _T_39 = bits(exp, 10, 0) @[RecFNToIN.scala 92:20] + node _T_40 = not(_T_39) @[RecFNToIN.scala 92:38] + node _T_42 = eq(_T_40, UInt<1>("h00")) @[RecFNToIN.scala 92:38] + node _T_43 = bits(roundBits, 1, 0) @[RecFNToIN.scala 92:53] + node _T_45 = neq(_T_43, UInt<1>("h00")) @[RecFNToIN.scala 92:60] + node _T_47 = mux(_T_42, _T_45, UInt<1>("h00")) @[RecFNToIN.scala 92:16] + node roundIncr_nearestEven = mux(notSpecial_magGeOne, _T_38, _T_47) @[RecFNToIN.scala 90:12] + node _T_48 = eq(io.roundingMode, UInt<2>("h00")) @[RecFNToIN.scala 95:27] + node _T_49 = and(_T_48, roundIncr_nearestEven) @[RecFNToIN.scala 95:51] + node _T_50 = eq(io.roundingMode, UInt<2>("h02")) @[RecFNToIN.scala 96:27] + node _T_51 = and(sign, roundInexact) @[RecFNToIN.scala 96:60] + node _T_52 = and(_T_50, _T_51) @[RecFNToIN.scala 96:49] + node _T_53 = or(_T_49, _T_52) @[RecFNToIN.scala 95:78] + node _T_54 = eq(io.roundingMode, UInt<2>("h03")) @[RecFNToIN.scala 97:27] + node _T_56 = eq(sign, UInt<1>("h00")) @[RecFNToIN.scala 97:53] + node _T_57 = and(_T_56, roundInexact) @[RecFNToIN.scala 97:60] + node _T_58 = and(_T_54, _T_57) @[RecFNToIN.scala 97:49] + node roundIncr = or(_T_53, _T_58) @[RecFNToIN.scala 96:78] + node _T_59 = not(unroundedInt) @[RecFNToIN.scala 98:39] + node complUnroundedInt = mux(sign, _T_59, unroundedInt) @[RecFNToIN.scala 98:32] + node _T_60 = xor(roundIncr, sign) @[RecFNToIN.scala 100:23] + node _T_62 = add(complUnroundedInt, UInt<1>("h01")) @[RecFNToIN.scala 100:49] + node _T_63 = tail(_T_62, 1) @[RecFNToIN.scala 100:49] + node roundedInt = mux(_T_60, _T_63, complUnroundedInt) @[RecFNToIN.scala 100:12] + node _T_64 = bits(unroundedInt, 29, 0) @[RecFNToIN.scala 103:38] + node _T_65 = not(_T_64) @[RecFNToIN.scala 103:56] + node _T_67 = eq(_T_65, UInt<1>("h00")) @[RecFNToIN.scala 103:56] + node roundCarryBut2 = and(_T_67, roundIncr) @[RecFNToIN.scala 103:61] + node posExp = bits(exp, 10, 0) @[RecFNToIN.scala 104:21] + node _T_69 = geq(posExp, UInt<6>("h020")) @[RecFNToIN.scala 108:21] + node _T_71 = eq(posExp, UInt<5>("h01f")) @[RecFNToIN.scala 109:26] + node _T_73 = eq(sign, UInt<1>("h00")) @[RecFNToIN.scala 110:23] + node _T_74 = bits(unroundedInt, 30, 0) @[RecFNToIN.scala 110:45] + node _T_76 = neq(_T_74, UInt<1>("h00")) @[RecFNToIN.scala 110:63] + node _T_77 = or(_T_73, _T_76) @[RecFNToIN.scala 110:30] + node _T_78 = or(_T_77, roundIncr) @[RecFNToIN.scala 111:27] + node _T_79 = and(_T_71, _T_78) @[RecFNToIN.scala 109:50] + node _T_80 = or(_T_69, _T_79) @[RecFNToIN.scala 108:40] + node _T_82 = eq(sign, UInt<1>("h00")) @[RecFNToIN.scala 112:18] + node _T_84 = eq(posExp, UInt<5>("h01e")) @[RecFNToIN.scala 112:36] + node _T_85 = and(_T_82, _T_84) @[RecFNToIN.scala 112:25] + node _T_86 = and(_T_85, roundCarryBut2) @[RecFNToIN.scala 112:60] + node _T_87 = or(_T_80, _T_86) @[RecFNToIN.scala 111:42] + node overflow_signed = mux(notSpecial_magGeOne, _T_87, UInt<1>("h00")) @[RecFNToIN.scala 107:12] + node _T_90 = geq(posExp, UInt<6>("h020")) @[RecFNToIN.scala 117:29] + node _T_91 = or(sign, _T_90) @[RecFNToIN.scala 117:18] + node _T_93 = eq(posExp, UInt<5>("h01f")) @[RecFNToIN.scala 118:26] + node _T_94 = bits(unroundedInt, 30, 30) @[RecFNToIN.scala 119:34] + node _T_95 = and(_T_93, _T_94) @[RecFNToIN.scala 118:50] + node _T_96 = and(_T_95, roundCarryBut2) @[RecFNToIN.scala 119:49] + node _T_97 = or(_T_91, _T_96) @[RecFNToIN.scala 117:48] + node _T_98 = and(sign, roundIncr) @[RecFNToIN.scala 120:18] + node overflow_unsigned = mux(notSpecial_magGeOne, _T_97, _T_98) @[RecFNToIN.scala 116:12] + node overflow = mux(io.signedOut, overflow_signed, overflow_unsigned) @[RecFNToIN.scala 122:23] + node _T_100 = eq(isNaN, UInt<1>("h00")) @[RecFNToIN.scala 124:27] + node excSign = and(sign, _T_100) @[RecFNToIN.scala 124:24] + node _T_101 = and(io.signedOut, excSign) @[RecFNToIN.scala 126:26] + node _T_103 = shl(UInt<1>("h01"), 31) @[RecFNToIN.scala 126:45] + node _T_105 = mux(_T_101, _T_103, UInt<1>("h00")) @[RecFNToIN.scala 126:12] + node _T_107 = eq(excSign, UInt<1>("h00")) @[RecFNToIN.scala 127:29] + node _T_108 = and(io.signedOut, _T_107) @[RecFNToIN.scala 127:26] + node _T_111 = mux(_T_108, UInt<31>("h07fffffff"), UInt<1>("h00")) @[RecFNToIN.scala 127:12] + node _T_112 = or(_T_105, _T_111) @[RecFNToIN.scala 126:72] + node _T_114 = eq(io.signedOut, UInt<1>("h00")) @[RecFNToIN.scala 131:13] + node _T_116 = eq(excSign, UInt<1>("h00")) @[RecFNToIN.scala 131:31] + node _T_117 = and(_T_114, _T_116) @[RecFNToIN.scala 131:28] + node _T_120 = mux(_T_117, UInt<32>("h0ffffffff"), UInt<1>("h00")) @[RecFNToIN.scala 131:12] + node excValue = or(_T_112, _T_120) @[RecFNToIN.scala 130:11] + node _T_122 = eq(invalid, UInt<1>("h00")) @[RecFNToIN.scala 135:35] + node _T_123 = and(roundInexact, _T_122) @[RecFNToIN.scala 135:32] + node _T_125 = eq(overflow, UInt<1>("h00")) @[RecFNToIN.scala 135:48] + node inexact = and(_T_123, _T_125) @[RecFNToIN.scala 135:45] + node _T_126 = or(invalid, overflow) @[RecFNToIN.scala 137:27] + node _T_127 = mux(_T_126, excValue, roundedInt) @[RecFNToIN.scala 137:18] + io.out <= _T_127 @[RecFNToIN.scala 137:12] + node _T_128 = cat(invalid, overflow) @[Cat.scala 30:58] + node _T_129 = cat(_T_128, inexact) @[Cat.scala 30:58] + io.intExceptionFlags <= _T_129 @[RecFNToIN.scala 138:26] + + module RecFNToIN_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, flip signedOut : UInt<1>, out : UInt<64>, intExceptionFlags : UInt<3>} + + io is invalid + io is invalid + node sign = bits(io.in, 64, 64) @[RecFNToIN.scala 54:21] + node exp = bits(io.in, 63, 52) @[RecFNToIN.scala 55:20] + node fract = bits(io.in, 51, 0) @[RecFNToIN.scala 56:22] + node _T_12 = bits(exp, 11, 9) @[RecFNToIN.scala 58:22] + node isZero = eq(_T_12, UInt<1>("h00")) @[RecFNToIN.scala 58:47] + node _T_14 = bits(exp, 11, 10) @[RecFNToIN.scala 59:25] + node invalid = eq(_T_14, UInt<2>("h03")) @[RecFNToIN.scala 59:50] + node _T_16 = bits(exp, 9, 9) @[RecFNToIN.scala 60:33] + node isNaN = and(invalid, _T_16) @[RecFNToIN.scala 60:27] + node notSpecial_magGeOne = bits(exp, 11, 11) @[RecFNToIN.scala 61:34] + node _T_17 = cat(notSpecial_magGeOne, fract) @[Cat.scala 30:58] + node _T_18 = bits(exp, 5, 0) @[RecFNToIN.scala 74:20] + node _T_20 = mux(notSpecial_magGeOne, _T_18, UInt<1>("h00")) @[RecFNToIN.scala 73:16] + node shiftedSig = dshl(_T_17, _T_20) @[RecFNToIN.scala 72:40] + node unroundedInt = bits(shiftedSig, 115, 52) @[RecFNToIN.scala 82:24] + node _T_21 = bits(shiftedSig, 52, 51) @[RecFNToIN.scala 85:23] + node _T_22 = bits(shiftedSig, 50, 0) @[RecFNToIN.scala 86:23] + node _T_24 = neq(_T_22, UInt<1>("h00")) @[RecFNToIN.scala 86:41] + node roundBits = cat(_T_21, _T_24) @[Cat.scala 30:58] + node _T_25 = bits(roundBits, 1, 0) @[RecFNToIN.scala 88:58] + node _T_27 = neq(_T_25, UInt<1>("h00")) @[RecFNToIN.scala 88:65] + node _T_29 = eq(isZero, UInt<1>("h00")) @[RecFNToIN.scala 88:70] + node roundInexact = mux(notSpecial_magGeOne, _T_27, _T_29) @[RecFNToIN.scala 88:27] + node _T_30 = bits(roundBits, 2, 1) @[RecFNToIN.scala 91:22] + node _T_31 = not(_T_30) @[RecFNToIN.scala 91:29] + node _T_33 = eq(_T_31, UInt<1>("h00")) @[RecFNToIN.scala 91:29] + node _T_34 = bits(roundBits, 1, 0) @[RecFNToIN.scala 91:46] + node _T_35 = not(_T_34) @[RecFNToIN.scala 91:53] + node _T_37 = eq(_T_35, UInt<1>("h00")) @[RecFNToIN.scala 91:53] + node _T_38 = or(_T_33, _T_37) @[RecFNToIN.scala 91:34] + node _T_39 = bits(exp, 10, 0) @[RecFNToIN.scala 92:20] + node _T_40 = not(_T_39) @[RecFNToIN.scala 92:38] + node _T_42 = eq(_T_40, UInt<1>("h00")) @[RecFNToIN.scala 92:38] + node _T_43 = bits(roundBits, 1, 0) @[RecFNToIN.scala 92:53] + node _T_45 = neq(_T_43, UInt<1>("h00")) @[RecFNToIN.scala 92:60] + node _T_47 = mux(_T_42, _T_45, UInt<1>("h00")) @[RecFNToIN.scala 92:16] + node roundIncr_nearestEven = mux(notSpecial_magGeOne, _T_38, _T_47) @[RecFNToIN.scala 90:12] + node _T_48 = eq(io.roundingMode, UInt<2>("h00")) @[RecFNToIN.scala 95:27] + node _T_49 = and(_T_48, roundIncr_nearestEven) @[RecFNToIN.scala 95:51] + node _T_50 = eq(io.roundingMode, UInt<2>("h02")) @[RecFNToIN.scala 96:27] + node _T_51 = and(sign, roundInexact) @[RecFNToIN.scala 96:60] + node _T_52 = and(_T_50, _T_51) @[RecFNToIN.scala 96:49] + node _T_53 = or(_T_49, _T_52) @[RecFNToIN.scala 95:78] + node _T_54 = eq(io.roundingMode, UInt<2>("h03")) @[RecFNToIN.scala 97:27] + node _T_56 = eq(sign, UInt<1>("h00")) @[RecFNToIN.scala 97:53] + node _T_57 = and(_T_56, roundInexact) @[RecFNToIN.scala 97:60] + node _T_58 = and(_T_54, _T_57) @[RecFNToIN.scala 97:49] + node roundIncr = or(_T_53, _T_58) @[RecFNToIN.scala 96:78] + node _T_59 = not(unroundedInt) @[RecFNToIN.scala 98:39] + node complUnroundedInt = mux(sign, _T_59, unroundedInt) @[RecFNToIN.scala 98:32] + node _T_60 = xor(roundIncr, sign) @[RecFNToIN.scala 100:23] + node _T_62 = add(complUnroundedInt, UInt<1>("h01")) @[RecFNToIN.scala 100:49] + node _T_63 = tail(_T_62, 1) @[RecFNToIN.scala 100:49] + node roundedInt = mux(_T_60, _T_63, complUnroundedInt) @[RecFNToIN.scala 100:12] + node _T_64 = bits(unroundedInt, 61, 0) @[RecFNToIN.scala 103:38] + node _T_65 = not(_T_64) @[RecFNToIN.scala 103:56] + node _T_67 = eq(_T_65, UInt<1>("h00")) @[RecFNToIN.scala 103:56] + node roundCarryBut2 = and(_T_67, roundIncr) @[RecFNToIN.scala 103:61] + node posExp = bits(exp, 10, 0) @[RecFNToIN.scala 104:21] + node _T_69 = geq(posExp, UInt<7>("h040")) @[RecFNToIN.scala 108:21] + node _T_71 = eq(posExp, UInt<6>("h03f")) @[RecFNToIN.scala 109:26] + node _T_73 = eq(sign, UInt<1>("h00")) @[RecFNToIN.scala 110:23] + node _T_74 = bits(unroundedInt, 62, 0) @[RecFNToIN.scala 110:45] + node _T_76 = neq(_T_74, UInt<1>("h00")) @[RecFNToIN.scala 110:63] + node _T_77 = or(_T_73, _T_76) @[RecFNToIN.scala 110:30] + node _T_78 = or(_T_77, roundIncr) @[RecFNToIN.scala 111:27] + node _T_79 = and(_T_71, _T_78) @[RecFNToIN.scala 109:50] + node _T_80 = or(_T_69, _T_79) @[RecFNToIN.scala 108:40] + node _T_82 = eq(sign, UInt<1>("h00")) @[RecFNToIN.scala 112:18] + node _T_84 = eq(posExp, UInt<6>("h03e")) @[RecFNToIN.scala 112:36] + node _T_85 = and(_T_82, _T_84) @[RecFNToIN.scala 112:25] + node _T_86 = and(_T_85, roundCarryBut2) @[RecFNToIN.scala 112:60] + node _T_87 = or(_T_80, _T_86) @[RecFNToIN.scala 111:42] + node overflow_signed = mux(notSpecial_magGeOne, _T_87, UInt<1>("h00")) @[RecFNToIN.scala 107:12] + node _T_90 = geq(posExp, UInt<7>("h040")) @[RecFNToIN.scala 117:29] + node _T_91 = or(sign, _T_90) @[RecFNToIN.scala 117:18] + node _T_93 = eq(posExp, UInt<6>("h03f")) @[RecFNToIN.scala 118:26] + node _T_94 = bits(unroundedInt, 62, 62) @[RecFNToIN.scala 119:34] + node _T_95 = and(_T_93, _T_94) @[RecFNToIN.scala 118:50] + node _T_96 = and(_T_95, roundCarryBut2) @[RecFNToIN.scala 119:49] + node _T_97 = or(_T_91, _T_96) @[RecFNToIN.scala 117:48] + node _T_98 = and(sign, roundIncr) @[RecFNToIN.scala 120:18] + node overflow_unsigned = mux(notSpecial_magGeOne, _T_97, _T_98) @[RecFNToIN.scala 116:12] + node overflow = mux(io.signedOut, overflow_signed, overflow_unsigned) @[RecFNToIN.scala 122:23] + node _T_100 = eq(isNaN, UInt<1>("h00")) @[RecFNToIN.scala 124:27] + node excSign = and(sign, _T_100) @[RecFNToIN.scala 124:24] + node _T_101 = and(io.signedOut, excSign) @[RecFNToIN.scala 126:26] + node _T_103 = shl(UInt<1>("h01"), 63) @[RecFNToIN.scala 126:45] + node _T_105 = mux(_T_101, _T_103, UInt<1>("h00")) @[RecFNToIN.scala 126:12] + node _T_107 = eq(excSign, UInt<1>("h00")) @[RecFNToIN.scala 127:29] + node _T_108 = and(io.signedOut, _T_107) @[RecFNToIN.scala 127:26] + node _T_111 = mux(_T_108, UInt<63>("h07fffffffffffffff"), UInt<1>("h00")) @[RecFNToIN.scala 127:12] + node _T_112 = or(_T_105, _T_111) @[RecFNToIN.scala 126:72] + node _T_114 = eq(io.signedOut, UInt<1>("h00")) @[RecFNToIN.scala 131:13] + node _T_116 = eq(excSign, UInt<1>("h00")) @[RecFNToIN.scala 131:31] + node _T_117 = and(_T_114, _T_116) @[RecFNToIN.scala 131:28] + node _T_120 = mux(_T_117, UInt<64>("h0ffffffffffffffff"), UInt<1>("h00")) @[RecFNToIN.scala 131:12] + node excValue = or(_T_112, _T_120) @[RecFNToIN.scala 130:11] + node _T_122 = eq(invalid, UInt<1>("h00")) @[RecFNToIN.scala 135:35] + node _T_123 = and(roundInexact, _T_122) @[RecFNToIN.scala 135:32] + node _T_125 = eq(overflow, UInt<1>("h00")) @[RecFNToIN.scala 135:48] + node inexact = and(_T_123, _T_125) @[RecFNToIN.scala 135:45] + node _T_126 = or(invalid, overflow) @[RecFNToIN.scala 137:27] + node _T_127 = mux(_T_126, excValue, roundedInt) @[RecFNToIN.scala 137:18] + io.out <= _T_127 @[RecFNToIN.scala 137:12] + node _T_128 = cat(invalid, overflow) @[Cat.scala 30:58] + node _T_129 = cat(_T_128, inexact) @[Cat.scala 30:58] + io.intExceptionFlags <= _T_129 @[RecFNToIN.scala 138:26] + + module INToRecFN : + input clock : Clock + input reset : UInt<1> + output io : {flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + node _T_12 = bits(io.in, 63, 63) @[INToRecFN.scala 55:36] + node sign = and(io.signedIn, _T_12) @[INToRecFN.scala 55:28] + node _T_14 = sub(UInt<1>("h00"), io.in) @[INToRecFN.scala 56:27] + node _T_15 = asUInt(_T_14) @[INToRecFN.scala 56:27] + node _T_16 = tail(_T_15, 1) @[INToRecFN.scala 56:27] + node absIn = mux(sign, _T_16, io.in) @[INToRecFN.scala 56:20] + node _T_17 = shl(absIn, 0) @[INToRecFN.scala 57:32] + node _T_18 = bits(_T_17, 63, 32) @[CircuitMath.scala 35:17] + node _T_19 = bits(_T_17, 31, 0) @[CircuitMath.scala 36:17] + node _T_21 = neq(_T_18, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_22 = bits(_T_18, 31, 16) @[CircuitMath.scala 35:17] + node _T_23 = bits(_T_18, 15, 0) @[CircuitMath.scala 36:17] + node _T_25 = neq(_T_22, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_26 = bits(_T_22, 15, 8) @[CircuitMath.scala 35:17] + node _T_27 = bits(_T_22, 7, 0) @[CircuitMath.scala 36:17] + node _T_29 = neq(_T_26, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_30 = bits(_T_26, 7, 4) @[CircuitMath.scala 35:17] + node _T_31 = bits(_T_26, 3, 0) @[CircuitMath.scala 36:17] + node _T_33 = neq(_T_30, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_34 = bits(_T_30, 3, 3) @[CircuitMath.scala 32:12] + node _T_36 = bits(_T_30, 2, 2) @[CircuitMath.scala 32:12] + node _T_38 = bits(_T_30, 1, 1) @[CircuitMath.scala 30:8] + node _T_39 = mux(_T_36, UInt<2>("h02"), _T_38) @[CircuitMath.scala 32:10] + node _T_40 = mux(_T_34, UInt<2>("h03"), _T_39) @[CircuitMath.scala 32:10] + node _T_41 = bits(_T_31, 3, 3) @[CircuitMath.scala 32:12] + node _T_43 = bits(_T_31, 2, 2) @[CircuitMath.scala 32:12] + node _T_45 = bits(_T_31, 1, 1) @[CircuitMath.scala 30:8] + node _T_46 = mux(_T_43, UInt<2>("h02"), _T_45) @[CircuitMath.scala 32:10] + node _T_47 = mux(_T_41, UInt<2>("h03"), _T_46) @[CircuitMath.scala 32:10] + node _T_48 = mux(_T_33, _T_40, _T_47) @[CircuitMath.scala 38:21] + node _T_49 = cat(_T_33, _T_48) @[Cat.scala 30:58] + node _T_50 = bits(_T_27, 7, 4) @[CircuitMath.scala 35:17] + node _T_51 = bits(_T_27, 3, 0) @[CircuitMath.scala 36:17] + node _T_53 = neq(_T_50, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_54 = bits(_T_50, 3, 3) @[CircuitMath.scala 32:12] + node _T_56 = bits(_T_50, 2, 2) @[CircuitMath.scala 32:12] + node _T_58 = bits(_T_50, 1, 1) @[CircuitMath.scala 30:8] + node _T_59 = mux(_T_56, UInt<2>("h02"), _T_58) @[CircuitMath.scala 32:10] + node _T_60 = mux(_T_54, UInt<2>("h03"), _T_59) @[CircuitMath.scala 32:10] + node _T_61 = bits(_T_51, 3, 3) @[CircuitMath.scala 32:12] + node _T_63 = bits(_T_51, 2, 2) @[CircuitMath.scala 32:12] + node _T_65 = bits(_T_51, 1, 1) @[CircuitMath.scala 30:8] + node _T_66 = mux(_T_63, UInt<2>("h02"), _T_65) @[CircuitMath.scala 32:10] + node _T_67 = mux(_T_61, UInt<2>("h03"), _T_66) @[CircuitMath.scala 32:10] + node _T_68 = mux(_T_53, _T_60, _T_67) @[CircuitMath.scala 38:21] + node _T_69 = cat(_T_53, _T_68) @[Cat.scala 30:58] + node _T_70 = mux(_T_29, _T_49, _T_69) @[CircuitMath.scala 38:21] + node _T_71 = cat(_T_29, _T_70) @[Cat.scala 30:58] + node _T_72 = bits(_T_23, 15, 8) @[CircuitMath.scala 35:17] + node _T_73 = bits(_T_23, 7, 0) @[CircuitMath.scala 36:17] + node _T_75 = neq(_T_72, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_76 = bits(_T_72, 7, 4) @[CircuitMath.scala 35:17] + node _T_77 = bits(_T_72, 3, 0) @[CircuitMath.scala 36:17] + node _T_79 = neq(_T_76, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_80 = bits(_T_76, 3, 3) @[CircuitMath.scala 32:12] + node _T_82 = bits(_T_76, 2, 2) @[CircuitMath.scala 32:12] + node _T_84 = bits(_T_76, 1, 1) @[CircuitMath.scala 30:8] + node _T_85 = mux(_T_82, UInt<2>("h02"), _T_84) @[CircuitMath.scala 32:10] + node _T_86 = mux(_T_80, UInt<2>("h03"), _T_85) @[CircuitMath.scala 32:10] + node _T_87 = bits(_T_77, 3, 3) @[CircuitMath.scala 32:12] + node _T_89 = bits(_T_77, 2, 2) @[CircuitMath.scala 32:12] + node _T_91 = bits(_T_77, 1, 1) @[CircuitMath.scala 30:8] + node _T_92 = mux(_T_89, UInt<2>("h02"), _T_91) @[CircuitMath.scala 32:10] + node _T_93 = mux(_T_87, UInt<2>("h03"), _T_92) @[CircuitMath.scala 32:10] + node _T_94 = mux(_T_79, _T_86, _T_93) @[CircuitMath.scala 38:21] + node _T_95 = cat(_T_79, _T_94) @[Cat.scala 30:58] + node _T_96 = bits(_T_73, 7, 4) @[CircuitMath.scala 35:17] + node _T_97 = bits(_T_73, 3, 0) @[CircuitMath.scala 36:17] + node _T_99 = neq(_T_96, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_100 = bits(_T_96, 3, 3) @[CircuitMath.scala 32:12] + node _T_102 = bits(_T_96, 2, 2) @[CircuitMath.scala 32:12] + node _T_104 = bits(_T_96, 1, 1) @[CircuitMath.scala 30:8] + node _T_105 = mux(_T_102, UInt<2>("h02"), _T_104) @[CircuitMath.scala 32:10] + node _T_106 = mux(_T_100, UInt<2>("h03"), _T_105) @[CircuitMath.scala 32:10] + node _T_107 = bits(_T_97, 3, 3) @[CircuitMath.scala 32:12] + node _T_109 = bits(_T_97, 2, 2) @[CircuitMath.scala 32:12] + node _T_111 = bits(_T_97, 1, 1) @[CircuitMath.scala 30:8] + node _T_112 = mux(_T_109, UInt<2>("h02"), _T_111) @[CircuitMath.scala 32:10] + node _T_113 = mux(_T_107, UInt<2>("h03"), _T_112) @[CircuitMath.scala 32:10] + node _T_114 = mux(_T_99, _T_106, _T_113) @[CircuitMath.scala 38:21] + node _T_115 = cat(_T_99, _T_114) @[Cat.scala 30:58] + node _T_116 = mux(_T_75, _T_95, _T_115) @[CircuitMath.scala 38:21] + node _T_117 = cat(_T_75, _T_116) @[Cat.scala 30:58] + node _T_118 = mux(_T_25, _T_71, _T_117) @[CircuitMath.scala 38:21] + node _T_119 = cat(_T_25, _T_118) @[Cat.scala 30:58] + node _T_120 = bits(_T_19, 31, 16) @[CircuitMath.scala 35:17] + node _T_121 = bits(_T_19, 15, 0) @[CircuitMath.scala 36:17] + node _T_123 = neq(_T_120, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_124 = bits(_T_120, 15, 8) @[CircuitMath.scala 35:17] + node _T_125 = bits(_T_120, 7, 0) @[CircuitMath.scala 36:17] + node _T_127 = neq(_T_124, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_128 = bits(_T_124, 7, 4) @[CircuitMath.scala 35:17] + node _T_129 = bits(_T_124, 3, 0) @[CircuitMath.scala 36:17] + node _T_131 = neq(_T_128, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_132 = bits(_T_128, 3, 3) @[CircuitMath.scala 32:12] + node _T_134 = bits(_T_128, 2, 2) @[CircuitMath.scala 32:12] + node _T_136 = bits(_T_128, 1, 1) @[CircuitMath.scala 30:8] + node _T_137 = mux(_T_134, UInt<2>("h02"), _T_136) @[CircuitMath.scala 32:10] + node _T_138 = mux(_T_132, UInt<2>("h03"), _T_137) @[CircuitMath.scala 32:10] + node _T_139 = bits(_T_129, 3, 3) @[CircuitMath.scala 32:12] + node _T_141 = bits(_T_129, 2, 2) @[CircuitMath.scala 32:12] + node _T_143 = bits(_T_129, 1, 1) @[CircuitMath.scala 30:8] + node _T_144 = mux(_T_141, UInt<2>("h02"), _T_143) @[CircuitMath.scala 32:10] + node _T_145 = mux(_T_139, UInt<2>("h03"), _T_144) @[CircuitMath.scala 32:10] + node _T_146 = mux(_T_131, _T_138, _T_145) @[CircuitMath.scala 38:21] + node _T_147 = cat(_T_131, _T_146) @[Cat.scala 30:58] + node _T_148 = bits(_T_125, 7, 4) @[CircuitMath.scala 35:17] + node _T_149 = bits(_T_125, 3, 0) @[CircuitMath.scala 36:17] + node _T_151 = neq(_T_148, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_152 = bits(_T_148, 3, 3) @[CircuitMath.scala 32:12] + node _T_154 = bits(_T_148, 2, 2) @[CircuitMath.scala 32:12] + node _T_156 = bits(_T_148, 1, 1) @[CircuitMath.scala 30:8] + node _T_157 = mux(_T_154, UInt<2>("h02"), _T_156) @[CircuitMath.scala 32:10] + node _T_158 = mux(_T_152, UInt<2>("h03"), _T_157) @[CircuitMath.scala 32:10] + node _T_159 = bits(_T_149, 3, 3) @[CircuitMath.scala 32:12] + node _T_161 = bits(_T_149, 2, 2) @[CircuitMath.scala 32:12] + node _T_163 = bits(_T_149, 1, 1) @[CircuitMath.scala 30:8] + node _T_164 = mux(_T_161, UInt<2>("h02"), _T_163) @[CircuitMath.scala 32:10] + node _T_165 = mux(_T_159, UInt<2>("h03"), _T_164) @[CircuitMath.scala 32:10] + node _T_166 = mux(_T_151, _T_158, _T_165) @[CircuitMath.scala 38:21] + node _T_167 = cat(_T_151, _T_166) @[Cat.scala 30:58] + node _T_168 = mux(_T_127, _T_147, _T_167) @[CircuitMath.scala 38:21] + node _T_169 = cat(_T_127, _T_168) @[Cat.scala 30:58] + node _T_170 = bits(_T_121, 15, 8) @[CircuitMath.scala 35:17] + node _T_171 = bits(_T_121, 7, 0) @[CircuitMath.scala 36:17] + node _T_173 = neq(_T_170, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_174 = bits(_T_170, 7, 4) @[CircuitMath.scala 35:17] + node _T_175 = bits(_T_170, 3, 0) @[CircuitMath.scala 36:17] + node _T_177 = neq(_T_174, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_178 = bits(_T_174, 3, 3) @[CircuitMath.scala 32:12] + node _T_180 = bits(_T_174, 2, 2) @[CircuitMath.scala 32:12] + node _T_182 = bits(_T_174, 1, 1) @[CircuitMath.scala 30:8] + node _T_183 = mux(_T_180, UInt<2>("h02"), _T_182) @[CircuitMath.scala 32:10] + node _T_184 = mux(_T_178, UInt<2>("h03"), _T_183) @[CircuitMath.scala 32:10] + node _T_185 = bits(_T_175, 3, 3) @[CircuitMath.scala 32:12] + node _T_187 = bits(_T_175, 2, 2) @[CircuitMath.scala 32:12] + node _T_189 = bits(_T_175, 1, 1) @[CircuitMath.scala 30:8] + node _T_190 = mux(_T_187, UInt<2>("h02"), _T_189) @[CircuitMath.scala 32:10] + node _T_191 = mux(_T_185, UInt<2>("h03"), _T_190) @[CircuitMath.scala 32:10] + node _T_192 = mux(_T_177, _T_184, _T_191) @[CircuitMath.scala 38:21] + node _T_193 = cat(_T_177, _T_192) @[Cat.scala 30:58] + node _T_194 = bits(_T_171, 7, 4) @[CircuitMath.scala 35:17] + node _T_195 = bits(_T_171, 3, 0) @[CircuitMath.scala 36:17] + node _T_197 = neq(_T_194, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_198 = bits(_T_194, 3, 3) @[CircuitMath.scala 32:12] + node _T_200 = bits(_T_194, 2, 2) @[CircuitMath.scala 32:12] + node _T_202 = bits(_T_194, 1, 1) @[CircuitMath.scala 30:8] + node _T_203 = mux(_T_200, UInt<2>("h02"), _T_202) @[CircuitMath.scala 32:10] + node _T_204 = mux(_T_198, UInt<2>("h03"), _T_203) @[CircuitMath.scala 32:10] + node _T_205 = bits(_T_195, 3, 3) @[CircuitMath.scala 32:12] + node _T_207 = bits(_T_195, 2, 2) @[CircuitMath.scala 32:12] + node _T_209 = bits(_T_195, 1, 1) @[CircuitMath.scala 30:8] + node _T_210 = mux(_T_207, UInt<2>("h02"), _T_209) @[CircuitMath.scala 32:10] + node _T_211 = mux(_T_205, UInt<2>("h03"), _T_210) @[CircuitMath.scala 32:10] + node _T_212 = mux(_T_197, _T_204, _T_211) @[CircuitMath.scala 38:21] + node _T_213 = cat(_T_197, _T_212) @[Cat.scala 30:58] + node _T_214 = mux(_T_173, _T_193, _T_213) @[CircuitMath.scala 38:21] + node _T_215 = cat(_T_173, _T_214) @[Cat.scala 30:58] + node _T_216 = mux(_T_123, _T_169, _T_215) @[CircuitMath.scala 38:21] + node _T_217 = cat(_T_123, _T_216) @[Cat.scala 30:58] + node _T_218 = mux(_T_21, _T_119, _T_217) @[CircuitMath.scala 38:21] + node _T_219 = cat(_T_21, _T_218) @[Cat.scala 30:58] + node normCount = not(_T_219) @[INToRecFN.scala 57:21] + node _T_220 = dshl(absIn, normCount) @[INToRecFN.scala 58:27] + node normAbsIn = bits(_T_220, 63, 0) @[INToRecFN.scala 58:39] + node _T_222 = bits(normAbsIn, 40, 39) @[INToRecFN.scala 63:26] + node _T_223 = bits(normAbsIn, 38, 0) @[INToRecFN.scala 64:26] + node _T_225 = neq(_T_223, UInt<1>("h00")) @[INToRecFN.scala 64:55] + node roundBits = cat(_T_222, _T_225) @[Cat.scala 30:58] + node _T_226 = bits(roundBits, 1, 0) @[INToRecFN.scala 72:33] + node roundInexact = neq(_T_226, UInt<1>("h00")) @[INToRecFN.scala 72:40] + node _T_228 = eq(io.roundingMode, UInt<2>("h00")) @[INToRecFN.scala 74:30] + node _T_229 = bits(roundBits, 2, 1) @[INToRecFN.scala 75:22] + node _T_230 = not(_T_229) @[INToRecFN.scala 75:29] + node _T_232 = eq(_T_230, UInt<1>("h00")) @[INToRecFN.scala 75:29] + node _T_233 = bits(roundBits, 1, 0) @[INToRecFN.scala 75:46] + node _T_234 = not(_T_233) @[INToRecFN.scala 75:53] + node _T_236 = eq(_T_234, UInt<1>("h00")) @[INToRecFN.scala 75:53] + node _T_237 = or(_T_232, _T_236) @[INToRecFN.scala 75:34] + node _T_239 = mux(_T_228, _T_237, UInt<1>("h00")) @[INToRecFN.scala 74:12] + node _T_240 = eq(io.roundingMode, UInt<2>("h02")) @[INToRecFN.scala 78:30] + node _T_241 = and(sign, roundInexact) @[INToRecFN.scala 79:18] + node _T_243 = mux(_T_240, _T_241, UInt<1>("h00")) @[INToRecFN.scala 78:12] + node _T_244 = or(_T_239, _T_243) @[INToRecFN.scala 77:11] + node _T_245 = eq(io.roundingMode, UInt<2>("h03")) @[INToRecFN.scala 82:30] + node _T_247 = eq(sign, UInt<1>("h00")) @[INToRecFN.scala 83:13] + node _T_248 = and(_T_247, roundInexact) @[INToRecFN.scala 83:20] + node _T_250 = mux(_T_245, _T_248, UInt<1>("h00")) @[INToRecFN.scala 82:12] + node round = or(_T_244, _T_250) @[INToRecFN.scala 81:11] + node _T_252 = bits(normAbsIn, 63, 40) @[INToRecFN.scala 89:34] + node unroundedNorm = cat(UInt<1>("h00"), _T_252) @[Cat.scala 30:58] + node _T_255 = add(unroundedNorm, UInt<1>("h01")) @[INToRecFN.scala 94:48] + node _T_256 = tail(_T_255, 1) @[INToRecFN.scala 94:48] + node roundedNorm = mux(round, _T_256, unroundedNorm) @[INToRecFN.scala 94:26] + node _T_257 = not(normCount) @[INToRecFN.scala 97:24] + node unroundedExp = cat(UInt<1>("h00"), _T_257) @[Cat.scala 30:58] + node _T_260 = cat(UInt<1>("h00"), unroundedExp) @[Cat.scala 30:58] + node _T_261 = bits(roundedNorm, 24, 24) @[INToRecFN.scala 106:65] + node _T_262 = add(_T_260, _T_261) @[INToRecFN.scala 106:52] + node roundedExp = tail(_T_262, 1) @[INToRecFN.scala 106:52] + node _T_263 = bits(normAbsIn, 63, 63) @[INToRecFN.scala 112:22] + node _T_265 = bits(roundedExp, 7, 0) @[INToRecFN.scala 115:27] + node _T_266 = mux(UInt<1>("h00"), UInt<8>("h080"), _T_265) @[INToRecFN.scala 113:16] + node expOut = cat(_T_263, _T_266) @[Cat.scala 30:58] + node overflow = or(UInt<1>("h00"), UInt<1>("h00")) @[INToRecFN.scala 119:39] + node inexact = or(roundInexact, overflow) @[INToRecFN.scala 120:32] + node _T_267 = bits(roundedNorm, 22, 0) @[INToRecFN.scala 122:44] + node _T_268 = cat(sign, expOut) @[Cat.scala 30:58] + node _T_269 = cat(_T_268, _T_267) @[Cat.scala 30:58] + io.out <= _T_269 @[INToRecFN.scala 122:12] + node _T_272 = cat(UInt<1>("h00"), inexact) @[Cat.scala 30:58] + node _T_273 = cat(UInt<2>("h00"), overflow) @[Cat.scala 30:58] + node _T_274 = cat(_T_273, _T_272) @[Cat.scala 30:58] + io.exceptionFlags <= _T_274 @[INToRecFN.scala 123:23] + + module INToRecFN_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + node _T_12 = bits(io.in, 63, 63) @[INToRecFN.scala 55:36] + node sign = and(io.signedIn, _T_12) @[INToRecFN.scala 55:28] + node _T_14 = sub(UInt<1>("h00"), io.in) @[INToRecFN.scala 56:27] + node _T_15 = asUInt(_T_14) @[INToRecFN.scala 56:27] + node _T_16 = tail(_T_15, 1) @[INToRecFN.scala 56:27] + node absIn = mux(sign, _T_16, io.in) @[INToRecFN.scala 56:20] + node _T_17 = shl(absIn, 0) @[INToRecFN.scala 57:32] + node _T_18 = bits(_T_17, 63, 32) @[CircuitMath.scala 35:17] + node _T_19 = bits(_T_17, 31, 0) @[CircuitMath.scala 36:17] + node _T_21 = neq(_T_18, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_22 = bits(_T_18, 31, 16) @[CircuitMath.scala 35:17] + node _T_23 = bits(_T_18, 15, 0) @[CircuitMath.scala 36:17] + node _T_25 = neq(_T_22, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_26 = bits(_T_22, 15, 8) @[CircuitMath.scala 35:17] + node _T_27 = bits(_T_22, 7, 0) @[CircuitMath.scala 36:17] + node _T_29 = neq(_T_26, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_30 = bits(_T_26, 7, 4) @[CircuitMath.scala 35:17] + node _T_31 = bits(_T_26, 3, 0) @[CircuitMath.scala 36:17] + node _T_33 = neq(_T_30, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_34 = bits(_T_30, 3, 3) @[CircuitMath.scala 32:12] + node _T_36 = bits(_T_30, 2, 2) @[CircuitMath.scala 32:12] + node _T_38 = bits(_T_30, 1, 1) @[CircuitMath.scala 30:8] + node _T_39 = mux(_T_36, UInt<2>("h02"), _T_38) @[CircuitMath.scala 32:10] + node _T_40 = mux(_T_34, UInt<2>("h03"), _T_39) @[CircuitMath.scala 32:10] + node _T_41 = bits(_T_31, 3, 3) @[CircuitMath.scala 32:12] + node _T_43 = bits(_T_31, 2, 2) @[CircuitMath.scala 32:12] + node _T_45 = bits(_T_31, 1, 1) @[CircuitMath.scala 30:8] + node _T_46 = mux(_T_43, UInt<2>("h02"), _T_45) @[CircuitMath.scala 32:10] + node _T_47 = mux(_T_41, UInt<2>("h03"), _T_46) @[CircuitMath.scala 32:10] + node _T_48 = mux(_T_33, _T_40, _T_47) @[CircuitMath.scala 38:21] + node _T_49 = cat(_T_33, _T_48) @[Cat.scala 30:58] + node _T_50 = bits(_T_27, 7, 4) @[CircuitMath.scala 35:17] + node _T_51 = bits(_T_27, 3, 0) @[CircuitMath.scala 36:17] + node _T_53 = neq(_T_50, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_54 = bits(_T_50, 3, 3) @[CircuitMath.scala 32:12] + node _T_56 = bits(_T_50, 2, 2) @[CircuitMath.scala 32:12] + node _T_58 = bits(_T_50, 1, 1) @[CircuitMath.scala 30:8] + node _T_59 = mux(_T_56, UInt<2>("h02"), _T_58) @[CircuitMath.scala 32:10] + node _T_60 = mux(_T_54, UInt<2>("h03"), _T_59) @[CircuitMath.scala 32:10] + node _T_61 = bits(_T_51, 3, 3) @[CircuitMath.scala 32:12] + node _T_63 = bits(_T_51, 2, 2) @[CircuitMath.scala 32:12] + node _T_65 = bits(_T_51, 1, 1) @[CircuitMath.scala 30:8] + node _T_66 = mux(_T_63, UInt<2>("h02"), _T_65) @[CircuitMath.scala 32:10] + node _T_67 = mux(_T_61, UInt<2>("h03"), _T_66) @[CircuitMath.scala 32:10] + node _T_68 = mux(_T_53, _T_60, _T_67) @[CircuitMath.scala 38:21] + node _T_69 = cat(_T_53, _T_68) @[Cat.scala 30:58] + node _T_70 = mux(_T_29, _T_49, _T_69) @[CircuitMath.scala 38:21] + node _T_71 = cat(_T_29, _T_70) @[Cat.scala 30:58] + node _T_72 = bits(_T_23, 15, 8) @[CircuitMath.scala 35:17] + node _T_73 = bits(_T_23, 7, 0) @[CircuitMath.scala 36:17] + node _T_75 = neq(_T_72, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_76 = bits(_T_72, 7, 4) @[CircuitMath.scala 35:17] + node _T_77 = bits(_T_72, 3, 0) @[CircuitMath.scala 36:17] + node _T_79 = neq(_T_76, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_80 = bits(_T_76, 3, 3) @[CircuitMath.scala 32:12] + node _T_82 = bits(_T_76, 2, 2) @[CircuitMath.scala 32:12] + node _T_84 = bits(_T_76, 1, 1) @[CircuitMath.scala 30:8] + node _T_85 = mux(_T_82, UInt<2>("h02"), _T_84) @[CircuitMath.scala 32:10] + node _T_86 = mux(_T_80, UInt<2>("h03"), _T_85) @[CircuitMath.scala 32:10] + node _T_87 = bits(_T_77, 3, 3) @[CircuitMath.scala 32:12] + node _T_89 = bits(_T_77, 2, 2) @[CircuitMath.scala 32:12] + node _T_91 = bits(_T_77, 1, 1) @[CircuitMath.scala 30:8] + node _T_92 = mux(_T_89, UInt<2>("h02"), _T_91) @[CircuitMath.scala 32:10] + node _T_93 = mux(_T_87, UInt<2>("h03"), _T_92) @[CircuitMath.scala 32:10] + node _T_94 = mux(_T_79, _T_86, _T_93) @[CircuitMath.scala 38:21] + node _T_95 = cat(_T_79, _T_94) @[Cat.scala 30:58] + node _T_96 = bits(_T_73, 7, 4) @[CircuitMath.scala 35:17] + node _T_97 = bits(_T_73, 3, 0) @[CircuitMath.scala 36:17] + node _T_99 = neq(_T_96, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_100 = bits(_T_96, 3, 3) @[CircuitMath.scala 32:12] + node _T_102 = bits(_T_96, 2, 2) @[CircuitMath.scala 32:12] + node _T_104 = bits(_T_96, 1, 1) @[CircuitMath.scala 30:8] + node _T_105 = mux(_T_102, UInt<2>("h02"), _T_104) @[CircuitMath.scala 32:10] + node _T_106 = mux(_T_100, UInt<2>("h03"), _T_105) @[CircuitMath.scala 32:10] + node _T_107 = bits(_T_97, 3, 3) @[CircuitMath.scala 32:12] + node _T_109 = bits(_T_97, 2, 2) @[CircuitMath.scala 32:12] + node _T_111 = bits(_T_97, 1, 1) @[CircuitMath.scala 30:8] + node _T_112 = mux(_T_109, UInt<2>("h02"), _T_111) @[CircuitMath.scala 32:10] + node _T_113 = mux(_T_107, UInt<2>("h03"), _T_112) @[CircuitMath.scala 32:10] + node _T_114 = mux(_T_99, _T_106, _T_113) @[CircuitMath.scala 38:21] + node _T_115 = cat(_T_99, _T_114) @[Cat.scala 30:58] + node _T_116 = mux(_T_75, _T_95, _T_115) @[CircuitMath.scala 38:21] + node _T_117 = cat(_T_75, _T_116) @[Cat.scala 30:58] + node _T_118 = mux(_T_25, _T_71, _T_117) @[CircuitMath.scala 38:21] + node _T_119 = cat(_T_25, _T_118) @[Cat.scala 30:58] + node _T_120 = bits(_T_19, 31, 16) @[CircuitMath.scala 35:17] + node _T_121 = bits(_T_19, 15, 0) @[CircuitMath.scala 36:17] + node _T_123 = neq(_T_120, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_124 = bits(_T_120, 15, 8) @[CircuitMath.scala 35:17] + node _T_125 = bits(_T_120, 7, 0) @[CircuitMath.scala 36:17] + node _T_127 = neq(_T_124, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_128 = bits(_T_124, 7, 4) @[CircuitMath.scala 35:17] + node _T_129 = bits(_T_124, 3, 0) @[CircuitMath.scala 36:17] + node _T_131 = neq(_T_128, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_132 = bits(_T_128, 3, 3) @[CircuitMath.scala 32:12] + node _T_134 = bits(_T_128, 2, 2) @[CircuitMath.scala 32:12] + node _T_136 = bits(_T_128, 1, 1) @[CircuitMath.scala 30:8] + node _T_137 = mux(_T_134, UInt<2>("h02"), _T_136) @[CircuitMath.scala 32:10] + node _T_138 = mux(_T_132, UInt<2>("h03"), _T_137) @[CircuitMath.scala 32:10] + node _T_139 = bits(_T_129, 3, 3) @[CircuitMath.scala 32:12] + node _T_141 = bits(_T_129, 2, 2) @[CircuitMath.scala 32:12] + node _T_143 = bits(_T_129, 1, 1) @[CircuitMath.scala 30:8] + node _T_144 = mux(_T_141, UInt<2>("h02"), _T_143) @[CircuitMath.scala 32:10] + node _T_145 = mux(_T_139, UInt<2>("h03"), _T_144) @[CircuitMath.scala 32:10] + node _T_146 = mux(_T_131, _T_138, _T_145) @[CircuitMath.scala 38:21] + node _T_147 = cat(_T_131, _T_146) @[Cat.scala 30:58] + node _T_148 = bits(_T_125, 7, 4) @[CircuitMath.scala 35:17] + node _T_149 = bits(_T_125, 3, 0) @[CircuitMath.scala 36:17] + node _T_151 = neq(_T_148, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_152 = bits(_T_148, 3, 3) @[CircuitMath.scala 32:12] + node _T_154 = bits(_T_148, 2, 2) @[CircuitMath.scala 32:12] + node _T_156 = bits(_T_148, 1, 1) @[CircuitMath.scala 30:8] + node _T_157 = mux(_T_154, UInt<2>("h02"), _T_156) @[CircuitMath.scala 32:10] + node _T_158 = mux(_T_152, UInt<2>("h03"), _T_157) @[CircuitMath.scala 32:10] + node _T_159 = bits(_T_149, 3, 3) @[CircuitMath.scala 32:12] + node _T_161 = bits(_T_149, 2, 2) @[CircuitMath.scala 32:12] + node _T_163 = bits(_T_149, 1, 1) @[CircuitMath.scala 30:8] + node _T_164 = mux(_T_161, UInt<2>("h02"), _T_163) @[CircuitMath.scala 32:10] + node _T_165 = mux(_T_159, UInt<2>("h03"), _T_164) @[CircuitMath.scala 32:10] + node _T_166 = mux(_T_151, _T_158, _T_165) @[CircuitMath.scala 38:21] + node _T_167 = cat(_T_151, _T_166) @[Cat.scala 30:58] + node _T_168 = mux(_T_127, _T_147, _T_167) @[CircuitMath.scala 38:21] + node _T_169 = cat(_T_127, _T_168) @[Cat.scala 30:58] + node _T_170 = bits(_T_121, 15, 8) @[CircuitMath.scala 35:17] + node _T_171 = bits(_T_121, 7, 0) @[CircuitMath.scala 36:17] + node _T_173 = neq(_T_170, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_174 = bits(_T_170, 7, 4) @[CircuitMath.scala 35:17] + node _T_175 = bits(_T_170, 3, 0) @[CircuitMath.scala 36:17] + node _T_177 = neq(_T_174, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_178 = bits(_T_174, 3, 3) @[CircuitMath.scala 32:12] + node _T_180 = bits(_T_174, 2, 2) @[CircuitMath.scala 32:12] + node _T_182 = bits(_T_174, 1, 1) @[CircuitMath.scala 30:8] + node _T_183 = mux(_T_180, UInt<2>("h02"), _T_182) @[CircuitMath.scala 32:10] + node _T_184 = mux(_T_178, UInt<2>("h03"), _T_183) @[CircuitMath.scala 32:10] + node _T_185 = bits(_T_175, 3, 3) @[CircuitMath.scala 32:12] + node _T_187 = bits(_T_175, 2, 2) @[CircuitMath.scala 32:12] + node _T_189 = bits(_T_175, 1, 1) @[CircuitMath.scala 30:8] + node _T_190 = mux(_T_187, UInt<2>("h02"), _T_189) @[CircuitMath.scala 32:10] + node _T_191 = mux(_T_185, UInt<2>("h03"), _T_190) @[CircuitMath.scala 32:10] + node _T_192 = mux(_T_177, _T_184, _T_191) @[CircuitMath.scala 38:21] + node _T_193 = cat(_T_177, _T_192) @[Cat.scala 30:58] + node _T_194 = bits(_T_171, 7, 4) @[CircuitMath.scala 35:17] + node _T_195 = bits(_T_171, 3, 0) @[CircuitMath.scala 36:17] + node _T_197 = neq(_T_194, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_198 = bits(_T_194, 3, 3) @[CircuitMath.scala 32:12] + node _T_200 = bits(_T_194, 2, 2) @[CircuitMath.scala 32:12] + node _T_202 = bits(_T_194, 1, 1) @[CircuitMath.scala 30:8] + node _T_203 = mux(_T_200, UInt<2>("h02"), _T_202) @[CircuitMath.scala 32:10] + node _T_204 = mux(_T_198, UInt<2>("h03"), _T_203) @[CircuitMath.scala 32:10] + node _T_205 = bits(_T_195, 3, 3) @[CircuitMath.scala 32:12] + node _T_207 = bits(_T_195, 2, 2) @[CircuitMath.scala 32:12] + node _T_209 = bits(_T_195, 1, 1) @[CircuitMath.scala 30:8] + node _T_210 = mux(_T_207, UInt<2>("h02"), _T_209) @[CircuitMath.scala 32:10] + node _T_211 = mux(_T_205, UInt<2>("h03"), _T_210) @[CircuitMath.scala 32:10] + node _T_212 = mux(_T_197, _T_204, _T_211) @[CircuitMath.scala 38:21] + node _T_213 = cat(_T_197, _T_212) @[Cat.scala 30:58] + node _T_214 = mux(_T_173, _T_193, _T_213) @[CircuitMath.scala 38:21] + node _T_215 = cat(_T_173, _T_214) @[Cat.scala 30:58] + node _T_216 = mux(_T_123, _T_169, _T_215) @[CircuitMath.scala 38:21] + node _T_217 = cat(_T_123, _T_216) @[Cat.scala 30:58] + node _T_218 = mux(_T_21, _T_119, _T_217) @[CircuitMath.scala 38:21] + node _T_219 = cat(_T_21, _T_218) @[Cat.scala 30:58] + node normCount = not(_T_219) @[INToRecFN.scala 57:21] + node _T_220 = dshl(absIn, normCount) @[INToRecFN.scala 58:27] + node normAbsIn = bits(_T_220, 63, 0) @[INToRecFN.scala 58:39] + node _T_222 = bits(normAbsIn, 11, 10) @[INToRecFN.scala 63:26] + node _T_223 = bits(normAbsIn, 9, 0) @[INToRecFN.scala 64:26] + node _T_225 = neq(_T_223, UInt<1>("h00")) @[INToRecFN.scala 64:55] + node roundBits = cat(_T_222, _T_225) @[Cat.scala 30:58] + node _T_226 = bits(roundBits, 1, 0) @[INToRecFN.scala 72:33] + node roundInexact = neq(_T_226, UInt<1>("h00")) @[INToRecFN.scala 72:40] + node _T_228 = eq(io.roundingMode, UInt<2>("h00")) @[INToRecFN.scala 74:30] + node _T_229 = bits(roundBits, 2, 1) @[INToRecFN.scala 75:22] + node _T_230 = not(_T_229) @[INToRecFN.scala 75:29] + node _T_232 = eq(_T_230, UInt<1>("h00")) @[INToRecFN.scala 75:29] + node _T_233 = bits(roundBits, 1, 0) @[INToRecFN.scala 75:46] + node _T_234 = not(_T_233) @[INToRecFN.scala 75:53] + node _T_236 = eq(_T_234, UInt<1>("h00")) @[INToRecFN.scala 75:53] + node _T_237 = or(_T_232, _T_236) @[INToRecFN.scala 75:34] + node _T_239 = mux(_T_228, _T_237, UInt<1>("h00")) @[INToRecFN.scala 74:12] + node _T_240 = eq(io.roundingMode, UInt<2>("h02")) @[INToRecFN.scala 78:30] + node _T_241 = and(sign, roundInexact) @[INToRecFN.scala 79:18] + node _T_243 = mux(_T_240, _T_241, UInt<1>("h00")) @[INToRecFN.scala 78:12] + node _T_244 = or(_T_239, _T_243) @[INToRecFN.scala 77:11] + node _T_245 = eq(io.roundingMode, UInt<2>("h03")) @[INToRecFN.scala 82:30] + node _T_247 = eq(sign, UInt<1>("h00")) @[INToRecFN.scala 83:13] + node _T_248 = and(_T_247, roundInexact) @[INToRecFN.scala 83:20] + node _T_250 = mux(_T_245, _T_248, UInt<1>("h00")) @[INToRecFN.scala 82:12] + node round = or(_T_244, _T_250) @[INToRecFN.scala 81:11] + node _T_252 = bits(normAbsIn, 63, 11) @[INToRecFN.scala 89:34] + node unroundedNorm = cat(UInt<1>("h00"), _T_252) @[Cat.scala 30:58] + node _T_255 = add(unroundedNorm, UInt<1>("h01")) @[INToRecFN.scala 94:48] + node _T_256 = tail(_T_255, 1) @[INToRecFN.scala 94:48] + node roundedNorm = mux(round, _T_256, unroundedNorm) @[INToRecFN.scala 94:26] + node _T_257 = not(normCount) @[INToRecFN.scala 97:24] + node unroundedExp = cat(UInt<4>("h00"), _T_257) @[Cat.scala 30:58] + node _T_260 = cat(UInt<1>("h00"), unroundedExp) @[Cat.scala 30:58] + node _T_261 = bits(roundedNorm, 53, 53) @[INToRecFN.scala 106:65] + node _T_262 = add(_T_260, _T_261) @[INToRecFN.scala 106:52] + node roundedExp = tail(_T_262, 1) @[INToRecFN.scala 106:52] + node _T_263 = bits(normAbsIn, 63, 63) @[INToRecFN.scala 112:22] + node _T_265 = bits(roundedExp, 10, 0) @[INToRecFN.scala 115:27] + node _T_266 = mux(UInt<1>("h00"), UInt<11>("h0400"), _T_265) @[INToRecFN.scala 113:16] + node expOut = cat(_T_263, _T_266) @[Cat.scala 30:58] + node overflow = or(UInt<1>("h00"), UInt<1>("h00")) @[INToRecFN.scala 119:39] + node inexact = or(roundInexact, overflow) @[INToRecFN.scala 120:32] + node _T_267 = bits(roundedNorm, 51, 0) @[INToRecFN.scala 122:44] + node _T_268 = cat(sign, expOut) @[Cat.scala 30:58] + node _T_269 = cat(_T_268, _T_267) @[Cat.scala 30:58] + io.out <= _T_269 @[INToRecFN.scala 122:12] + node _T_272 = cat(UInt<1>("h00"), inexact) @[Cat.scala 30:58] + node _T_273 = cat(UInt<2>("h00"), overflow) @[Cat.scala 30:58] + node _T_274 = cat(_T_273, _T_272) @[Cat.scala 30:58] + io.exceptionFlags <= _T_274 @[INToRecFN.scala 123:23] + + module RecFNToRecFN : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + node _T_10 = bits(io.in, 63, 52) @[rawFNFromRecFN.scala 50:21] + node _T_11 = bits(_T_10, 11, 9) @[rawFNFromRecFN.scala 51:29] + node _T_13 = eq(_T_11, UInt<1>("h00")) @[rawFNFromRecFN.scala 51:54] + node _T_14 = bits(_T_10, 11, 10) @[rawFNFromRecFN.scala 52:29] + node _T_16 = eq(_T_14, UInt<2>("h03")) @[rawFNFromRecFN.scala 52:54] + wire _T_24 : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} @[rawFNFromRecFN.scala 54:23] + _T_24 is invalid @[rawFNFromRecFN.scala 54:23] + node _T_31 = bits(io.in, 64, 64) @[rawFNFromRecFN.scala 55:23] + _T_24.sign <= _T_31 @[rawFNFromRecFN.scala 55:18] + node _T_32 = bits(_T_10, 9, 9) @[rawFNFromRecFN.scala 56:40] + node _T_33 = and(_T_16, _T_32) @[rawFNFromRecFN.scala 56:32] + _T_24.isNaN <= _T_33 @[rawFNFromRecFN.scala 56:19] + node _T_34 = bits(_T_10, 9, 9) @[rawFNFromRecFN.scala 57:40] + node _T_36 = eq(_T_34, UInt<1>("h00")) @[rawFNFromRecFN.scala 57:35] + node _T_37 = and(_T_16, _T_36) @[rawFNFromRecFN.scala 57:32] + _T_24.isInf <= _T_37 @[rawFNFromRecFN.scala 57:19] + _T_24.isZero <= _T_13 @[rawFNFromRecFN.scala 58:20] + node _T_38 = cvt(_T_10) @[rawFNFromRecFN.scala 59:25] + _T_24.sExp <= _T_38 @[rawFNFromRecFN.scala 59:18] + node _T_41 = eq(_T_13, UInt<1>("h00")) @[rawFNFromRecFN.scala 60:36] + node _T_42 = bits(io.in, 51, 0) @[rawFNFromRecFN.scala 60:48] + node _T_44 = cat(_T_42, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_45 = cat(UInt<1>("h00"), _T_41) @[Cat.scala 30:58] + node _T_46 = cat(_T_45, _T_44) @[Cat.scala 30:58] + _T_24.sig <= _T_46 @[rawFNFromRecFN.scala 60:17] + node _T_48 = add(_T_24.sExp, asSInt(UInt<12>("h0900"))) @[resizeRawFN.scala 49:31] + wire outRawFloat : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} @[resizeRawFN.scala 51:23] + outRawFloat is invalid @[resizeRawFN.scala 51:23] + outRawFloat.sign <= _T_24.sign @[resizeRawFN.scala 52:20] + outRawFloat.isNaN <= _T_24.isNaN @[resizeRawFN.scala 53:20] + outRawFloat.isInf <= _T_24.isInf @[resizeRawFN.scala 54:20] + outRawFloat.isZero <= _T_24.isZero @[resizeRawFN.scala 55:20] + node _T_63 = lt(_T_48, asSInt(UInt<1>("h00"))) @[resizeRawFN.scala 60:31] + node _T_64 = bits(_T_48, 12, 9) @[resizeRawFN.scala 61:33] + node _T_66 = neq(_T_64, UInt<1>("h00")) @[resizeRawFN.scala 61:65] + node _T_71 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12] + node _T_73 = cat(_T_71, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_74 = bits(_T_48, 8, 0) @[resizeRawFN.scala 63:33] + node _T_75 = mux(_T_66, _T_73, _T_74) @[resizeRawFN.scala 61:25] + node _T_76 = cat(_T_63, _T_75) @[Cat.scala 30:58] + node _T_77 = asSInt(_T_76) @[resizeRawFN.scala 65:20] + outRawFloat.sExp <= _T_77 @[resizeRawFN.scala 56:18] + node _T_78 = bits(_T_24.sig, 55, 30) @[resizeRawFN.scala 71:28] + node _T_79 = bits(_T_24.sig, 29, 0) @[resizeRawFN.scala 72:28] + node _T_81 = neq(_T_79, UInt<1>("h00")) @[resizeRawFN.scala 72:56] + node _T_82 = cat(_T_78, _T_81) @[Cat.scala 30:58] + outRawFloat.sig <= _T_82 @[resizeRawFN.scala 67:17] + node _T_83 = bits(outRawFloat.sig, 24, 24) @[RoundRawFNToRecFN.scala 61:57] + node _T_85 = eq(_T_83, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 61:49] + node invalidExc = and(outRawFloat.isNaN, _T_85) @[RoundRawFNToRecFN.scala 61:46] + inst RoundRawFNToRecFN of RoundRawFNToRecFN @[RecFNToRecFN.scala 102:19] + RoundRawFNToRecFN.io is invalid + RoundRawFNToRecFN.clock <= clock + RoundRawFNToRecFN.reset <= reset + RoundRawFNToRecFN.io.invalidExc <= invalidExc @[RecFNToRecFN.scala 103:41] + RoundRawFNToRecFN.io.infiniteExc <= UInt<1>("h00") @[RecFNToRecFN.scala 104:42] + RoundRawFNToRecFN.io.in <- outRawFloat @[RecFNToRecFN.scala 105:33] + RoundRawFNToRecFN.io.roundingMode <= io.roundingMode @[RecFNToRecFN.scala 106:43] + io.out <= RoundRawFNToRecFN.io.out @[RecFNToRecFN.scala 107:16] + io.exceptionFlags <= RoundRawFNToRecFN.io.exceptionFlags @[RecFNToRecFN.scala 108:27] + + module RecFNToRecFN_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<33>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + node _T_10 = bits(io.in, 31, 23) @[rawFNFromRecFN.scala 50:21] + node _T_11 = bits(_T_10, 8, 6) @[rawFNFromRecFN.scala 51:29] + node _T_13 = eq(_T_11, UInt<1>("h00")) @[rawFNFromRecFN.scala 51:54] + node _T_14 = bits(_T_10, 8, 7) @[rawFNFromRecFN.scala 52:29] + node _T_16 = eq(_T_14, UInt<2>("h03")) @[rawFNFromRecFN.scala 52:54] + wire _T_24 : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} @[rawFNFromRecFN.scala 54:23] + _T_24 is invalid @[rawFNFromRecFN.scala 54:23] + node _T_31 = bits(io.in, 32, 32) @[rawFNFromRecFN.scala 55:23] + _T_24.sign <= _T_31 @[rawFNFromRecFN.scala 55:18] + node _T_32 = bits(_T_10, 6, 6) @[rawFNFromRecFN.scala 56:40] + node _T_33 = and(_T_16, _T_32) @[rawFNFromRecFN.scala 56:32] + _T_24.isNaN <= _T_33 @[rawFNFromRecFN.scala 56:19] + node _T_34 = bits(_T_10, 6, 6) @[rawFNFromRecFN.scala 57:40] + node _T_36 = eq(_T_34, UInt<1>("h00")) @[rawFNFromRecFN.scala 57:35] + node _T_37 = and(_T_16, _T_36) @[rawFNFromRecFN.scala 57:32] + _T_24.isInf <= _T_37 @[rawFNFromRecFN.scala 57:19] + _T_24.isZero <= _T_13 @[rawFNFromRecFN.scala 58:20] + node _T_38 = cvt(_T_10) @[rawFNFromRecFN.scala 59:25] + _T_24.sExp <= _T_38 @[rawFNFromRecFN.scala 59:18] + node _T_41 = eq(_T_13, UInt<1>("h00")) @[rawFNFromRecFN.scala 60:36] + node _T_42 = bits(io.in, 22, 0) @[rawFNFromRecFN.scala 60:48] + node _T_44 = cat(_T_42, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_45 = cat(UInt<1>("h00"), _T_41) @[Cat.scala 30:58] + node _T_46 = cat(_T_45, _T_44) @[Cat.scala 30:58] + _T_24.sig <= _T_46 @[rawFNFromRecFN.scala 60:17] + node _T_48 = add(_T_24.sExp, asSInt(UInt<12>("h0700"))) @[resizeRawFN.scala 49:31] + wire outRawFloat : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} @[resizeRawFN.scala 51:23] + outRawFloat is invalid @[resizeRawFN.scala 51:23] + outRawFloat.sign <= _T_24.sign @[resizeRawFN.scala 52:20] + outRawFloat.isNaN <= _T_24.isNaN @[resizeRawFN.scala 53:20] + outRawFloat.isInf <= _T_24.isInf @[resizeRawFN.scala 54:20] + outRawFloat.isZero <= _T_24.isZero @[resizeRawFN.scala 55:20] + outRawFloat.sExp <= _T_48 @[resizeRawFN.scala 56:18] + node _T_62 = shl(_T_24.sig, 29) @[resizeRawFN.scala 69:24] + outRawFloat.sig <= _T_62 @[resizeRawFN.scala 67:17] + node _T_63 = bits(outRawFloat.sig, 53, 53) @[RoundRawFNToRecFN.scala 61:57] + node _T_65 = eq(_T_63, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 61:49] + node invalidExc = and(outRawFloat.isNaN, _T_65) @[RoundRawFNToRecFN.scala 61:46] + node _T_67 = eq(outRawFloat.isNaN, UInt<1>("h00")) @[RecFNToRecFN.scala 69:40] + node _T_68 = and(outRawFloat.sign, _T_67) @[RecFNToRecFN.scala 69:37] + node _T_69 = bits(outRawFloat.sExp, 11, 0) @[RecFNToRecFN.scala 71:30] + node _T_72 = mux(outRawFloat.isZero, UInt<12>("h0c00"), UInt<1>("h00")) @[RecFNToRecFN.scala 72:22] + node _T_73 = not(_T_72) @[RecFNToRecFN.scala 72:18] + node _T_74 = and(_T_69, _T_73) @[RecFNToRecFN.scala 71:47] + node _T_75 = or(outRawFloat.isZero, outRawFloat.isInf) @[RecFNToRecFN.scala 76:42] + node _T_78 = mux(_T_75, UInt<12>("h0200"), UInt<1>("h00")) @[RecFNToRecFN.scala 76:22] + node _T_79 = not(_T_78) @[RecFNToRecFN.scala 76:18] + node _T_80 = and(_T_74, _T_79) @[RecFNToRecFN.scala 75:21] + node _T_83 = mux(outRawFloat.isInf, UInt<12>("h0c00"), UInt<1>("h00")) @[RecFNToRecFN.scala 80:20] + node _T_84 = or(_T_80, _T_83) @[RecFNToRecFN.scala 79:22] + node _T_87 = mux(outRawFloat.isNaN, UInt<12>("h0e00"), UInt<1>("h00")) @[RecFNToRecFN.scala 84:20] + node _T_88 = or(_T_84, _T_87) @[RecFNToRecFN.scala 83:19] + node _T_90 = shl(UInt<1>("h01"), 51) @[RecFNToRecFN.scala 90:24] + node _T_91 = bits(outRawFloat.sig, 53, 2) @[RecFNToRecFN.scala 91:32] + node _T_92 = mux(outRawFloat.isNaN, _T_90, _T_91) @[RecFNToRecFN.scala 89:16] + node _T_93 = cat(_T_68, _T_88) @[Cat.scala 30:58] + node _T_94 = cat(_T_93, _T_92) @[Cat.scala 30:58] + io.out <= _T_94 @[RecFNToRecFN.scala 93:16] + node _T_96 = cat(invalidExc, UInt<4>("h00")) @[Cat.scala 30:58] + io.exceptionFlags <= _T_96 @[RecFNToRecFN.scala 94:27] + + module MulAddRecFN_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + inst mulAddRecFN_preMul of MulAddRecFN_preMul_1 @[MulAddRecFN.scala 598:15] + mulAddRecFN_preMul.io is invalid + mulAddRecFN_preMul.clock <= clock + mulAddRecFN_preMul.reset <= reset + inst mulAddRecFN_postMul of MulAddRecFN_postMul_1 @[MulAddRecFN.scala 600:15] + mulAddRecFN_postMul.io is invalid + mulAddRecFN_postMul.clock <= clock + mulAddRecFN_postMul.reset <= reset + mulAddRecFN_preMul.io.op <= io.op @[MulAddRecFN.scala 602:30] + mulAddRecFN_preMul.io.a <= io.a @[MulAddRecFN.scala 603:30] + mulAddRecFN_preMul.io.b <= io.b @[MulAddRecFN.scala 604:30] + mulAddRecFN_preMul.io.c <= io.c @[MulAddRecFN.scala 605:30] + mulAddRecFN_preMul.io.roundingMode <= io.roundingMode @[MulAddRecFN.scala 606:40] + mulAddRecFN_postMul.io.fromPreMul <- mulAddRecFN_preMul.io.toPostMul @[MulAddRecFN.scala 608:39] + node _T_16 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB) @[MulAddRecFN.scala 610:39] + node _T_18 = cat(UInt<1>("h00"), mulAddRecFN_preMul.io.mulAddC) @[Cat.scala 30:58] + node _T_19 = add(_T_16, _T_18) @[MulAddRecFN.scala 610:71] + node _T_20 = tail(_T_19, 1) @[MulAddRecFN.scala 610:71] + mulAddRecFN_postMul.io.mulAddResult <= _T_20 @[MulAddRecFN.scala 609:41] + io.out <= mulAddRecFN_postMul.io.out @[MulAddRecFN.scala 613:12] + io.exceptionFlags <= mulAddRecFN_postMul.io.exceptionFlags @[MulAddRecFN.scala 614:23] + + module DivSqrtRecF64_mulAddZ31 : + input clock : Clock + input reset : UInt<1> + output io : {inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>, usingMulAdd : UInt<4>, latchMulAddA_0 : UInt<1>, mulAddA_0 : UInt<54>, latchMulAddB_0 : UInt<1>, mulAddB_0 : UInt<54>, mulAddC_2 : UInt<105>, flip mulAddResult_3 : UInt<105>} + + io is invalid + io is invalid + reg valid_PA : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[DivSqrtRecF64_mulAddZ31.scala 78:30] + reg sqrtOp_PA : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 79:30] + reg sign_PA : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 80:30] + reg specialCodeB_PA : UInt<3>, clock @[DivSqrtRecF64_mulAddZ31.scala 82:30] + reg fractB_51_PA : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 83:30] + reg roundingMode_PA : UInt<2>, clock @[DivSqrtRecF64_mulAddZ31.scala 84:30] + reg specialCodeA_PA : UInt<3>, clock @[DivSqrtRecF64_mulAddZ31.scala 85:30] + reg fractA_51_PA : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 86:30] + reg exp_PA : UInt<14>, clock @[DivSqrtRecF64_mulAddZ31.scala 87:30] + reg fractB_other_PA : UInt<51>, clock @[DivSqrtRecF64_mulAddZ31.scala 88:30] + reg fractA_other_PA : UInt<51>, clock @[DivSqrtRecF64_mulAddZ31.scala 89:30] + reg valid_PB : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[DivSqrtRecF64_mulAddZ31.scala 91:30] + reg sqrtOp_PB : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 92:30] + reg sign_PB : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 93:30] + reg specialCodeA_PB : UInt<3>, clock @[DivSqrtRecF64_mulAddZ31.scala 95:30] + reg fractA_51_PB : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 96:30] + reg specialCodeB_PB : UInt<3>, clock @[DivSqrtRecF64_mulAddZ31.scala 97:30] + reg fractB_51_PB : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 98:30] + reg roundingMode_PB : UInt<2>, clock @[DivSqrtRecF64_mulAddZ31.scala 99:30] + reg exp_PB : UInt<14>, clock @[DivSqrtRecF64_mulAddZ31.scala 100:30] + reg fractA_0_PB : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 101:30] + reg fractB_other_PB : UInt<51>, clock @[DivSqrtRecF64_mulAddZ31.scala 102:30] + reg valid_PC : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[DivSqrtRecF64_mulAddZ31.scala 104:30] + reg sqrtOp_PC : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 105:30] + reg sign_PC : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 106:30] + reg specialCodeA_PC : UInt<3>, clock @[DivSqrtRecF64_mulAddZ31.scala 108:30] + reg fractA_51_PC : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 109:30] + reg specialCodeB_PC : UInt<3>, clock @[DivSqrtRecF64_mulAddZ31.scala 110:30] + reg fractB_51_PC : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 111:30] + reg roundingMode_PC : UInt<2>, clock @[DivSqrtRecF64_mulAddZ31.scala 112:30] + reg exp_PC : UInt<14>, clock @[DivSqrtRecF64_mulAddZ31.scala 113:30] + reg fractA_0_PC : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 114:30] + reg fractB_other_PC : UInt<51>, clock @[DivSqrtRecF64_mulAddZ31.scala 115:30] + reg cycleNum_A : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[DivSqrtRecF64_mulAddZ31.scala 117:30] + reg cycleNum_B : UInt<4>, clock with : (reset => (reset, UInt<4>("h00"))) @[DivSqrtRecF64_mulAddZ31.scala 118:30] + reg cycleNum_C : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[DivSqrtRecF64_mulAddZ31.scala 119:30] + reg cycleNum_E : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[DivSqrtRecF64_mulAddZ31.scala 120:30] + reg fractR0_A : UInt<9>, clock @[DivSqrtRecF64_mulAddZ31.scala 122:30] + reg hiSqrR0_A_sqrt : UInt<10>, clock @[DivSqrtRecF64_mulAddZ31.scala 124:30] + reg partNegSigma0_A : UInt<21>, clock @[DivSqrtRecF64_mulAddZ31.scala 125:30] + reg nextMulAdd9A_A : UInt<9>, clock @[DivSqrtRecF64_mulAddZ31.scala 126:30] + reg nextMulAdd9B_A : UInt<9>, clock @[DivSqrtRecF64_mulAddZ31.scala 127:30] + reg ER1_B_sqrt : UInt<17>, clock @[DivSqrtRecF64_mulAddZ31.scala 128:30] + reg ESqrR1_B_sqrt : UInt<32>, clock @[DivSqrtRecF64_mulAddZ31.scala 130:30] + reg sigX1_B : UInt<58>, clock @[DivSqrtRecF64_mulAddZ31.scala 131:30] + reg sqrSigma1_C : UInt<33>, clock @[DivSqrtRecF64_mulAddZ31.scala 132:30] + reg sigXN_C : UInt<58>, clock @[DivSqrtRecF64_mulAddZ31.scala 133:30] + reg u_C_sqrt : UInt<31>, clock @[DivSqrtRecF64_mulAddZ31.scala 134:30] + reg E_E_div : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 135:30] + reg sigT_E : UInt<53>, clock @[DivSqrtRecF64_mulAddZ31.scala 136:30] + reg extraT_E : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 137:30] + reg isNegRemT_E : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 138:30] + reg isZeroRemT_E : UInt<1>, clock @[DivSqrtRecF64_mulAddZ31.scala 139:30] + wire ready_PA : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 143:24] + ready_PA is invalid @[DivSqrtRecF64_mulAddZ31.scala 143:24] + wire ready_PB : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 144:24] + ready_PB is invalid @[DivSqrtRecF64_mulAddZ31.scala 144:24] + wire ready_PC : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 145:24] + ready_PC is invalid @[DivSqrtRecF64_mulAddZ31.scala 145:24] + wire leaving_PA : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 146:26] + leaving_PA is invalid @[DivSqrtRecF64_mulAddZ31.scala 146:26] + wire leaving_PB : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 147:26] + leaving_PB is invalid @[DivSqrtRecF64_mulAddZ31.scala 147:26] + wire leaving_PC : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 148:26] + leaving_PC is invalid @[DivSqrtRecF64_mulAddZ31.scala 148:26] + wire cyc_B10_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 150:28] + cyc_B10_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 150:28] + wire cyc_B9_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 151:28] + cyc_B9_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 151:28] + wire cyc_B8_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 152:28] + cyc_B8_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 152:28] + wire cyc_B7_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 153:28] + cyc_B7_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 153:28] + wire cyc_B6 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 155:22] + cyc_B6 is invalid @[DivSqrtRecF64_mulAddZ31.scala 155:22] + wire cyc_B5 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 156:22] + cyc_B5 is invalid @[DivSqrtRecF64_mulAddZ31.scala 156:22] + wire cyc_B4 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 157:22] + cyc_B4 is invalid @[DivSqrtRecF64_mulAddZ31.scala 157:22] + wire cyc_B3 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 158:22] + cyc_B3 is invalid @[DivSqrtRecF64_mulAddZ31.scala 158:22] + wire cyc_B2 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 159:22] + cyc_B2 is invalid @[DivSqrtRecF64_mulAddZ31.scala 159:22] + wire cyc_B1 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 160:22] + cyc_B1 is invalid @[DivSqrtRecF64_mulAddZ31.scala 160:22] + wire cyc_B6_div : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 162:26] + cyc_B6_div is invalid @[DivSqrtRecF64_mulAddZ31.scala 162:26] + wire cyc_B5_div : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 163:26] + cyc_B5_div is invalid @[DivSqrtRecF64_mulAddZ31.scala 163:26] + wire cyc_B4_div : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 164:26] + cyc_B4_div is invalid @[DivSqrtRecF64_mulAddZ31.scala 164:26] + wire cyc_B3_div : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 165:26] + cyc_B3_div is invalid @[DivSqrtRecF64_mulAddZ31.scala 165:26] + wire cyc_B2_div : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 166:26] + cyc_B2_div is invalid @[DivSqrtRecF64_mulAddZ31.scala 166:26] + wire cyc_B1_div : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 167:26] + cyc_B1_div is invalid @[DivSqrtRecF64_mulAddZ31.scala 167:26] + wire cyc_B6_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 169:27] + cyc_B6_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 169:27] + wire cyc_B5_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 170:27] + cyc_B5_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 170:27] + wire cyc_B4_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 171:27] + cyc_B4_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 171:27] + wire cyc_B3_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 172:27] + cyc_B3_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 172:27] + wire cyc_B2_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 173:27] + cyc_B2_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 173:27] + wire cyc_B1_sqrt : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 174:27] + cyc_B1_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 174:27] + wire cyc_C5 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 176:22] + cyc_C5 is invalid @[DivSqrtRecF64_mulAddZ31.scala 176:22] + wire cyc_C4 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 177:22] + cyc_C4 is invalid @[DivSqrtRecF64_mulAddZ31.scala 177:22] + wire cyc_C3 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 178:22] + cyc_C3 is invalid @[DivSqrtRecF64_mulAddZ31.scala 178:22] + wire cyc_C2 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 179:22] + cyc_C2 is invalid @[DivSqrtRecF64_mulAddZ31.scala 179:22] + wire cyc_C1 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 180:22] + cyc_C1 is invalid @[DivSqrtRecF64_mulAddZ31.scala 180:22] + wire cyc_E4 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 182:22] + cyc_E4 is invalid @[DivSqrtRecF64_mulAddZ31.scala 182:22] + wire cyc_E3 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 183:22] + cyc_E3 is invalid @[DivSqrtRecF64_mulAddZ31.scala 183:22] + wire cyc_E2 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 184:22] + cyc_E2 is invalid @[DivSqrtRecF64_mulAddZ31.scala 184:22] + wire cyc_E1 : UInt<1> @[DivSqrtRecF64_mulAddZ31.scala 185:22] + cyc_E1 is invalid @[DivSqrtRecF64_mulAddZ31.scala 185:22] + wire zSigma1_B4 : UInt @[DivSqrtRecF64_mulAddZ31.scala 187:34] + zSigma1_B4 is invalid @[DivSqrtRecF64_mulAddZ31.scala 187:34] + wire sigXNU_B3_CX : UInt @[DivSqrtRecF64_mulAddZ31.scala 188:34] + sigXNU_B3_CX is invalid @[DivSqrtRecF64_mulAddZ31.scala 188:34] + wire zComplSigT_C1_sqrt : UInt @[DivSqrtRecF64_mulAddZ31.scala 189:34] + zComplSigT_C1_sqrt is invalid @[DivSqrtRecF64_mulAddZ31.scala 189:34] + wire zComplSigT_C1 : UInt @[DivSqrtRecF64_mulAddZ31.scala 190:34] + zComplSigT_C1 is invalid @[DivSqrtRecF64_mulAddZ31.scala 190:34] + node _T_133 = eq(cyc_B7_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 197:21] + node _T_134 = and(ready_PA, _T_133) @[DivSqrtRecF64_mulAddZ31.scala 197:18] + node _T_136 = eq(cyc_B6_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 197:38] + node _T_137 = and(_T_134, _T_136) @[DivSqrtRecF64_mulAddZ31.scala 197:35] + node _T_139 = eq(cyc_B5_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 197:55] + node _T_140 = and(_T_137, _T_139) @[DivSqrtRecF64_mulAddZ31.scala 197:52] + node _T_142 = eq(cyc_B4_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 198:13] + node _T_143 = and(_T_140, _T_142) @[DivSqrtRecF64_mulAddZ31.scala 197:69] + node _T_145 = eq(cyc_B3, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 198:30] + node _T_146 = and(_T_143, _T_145) @[DivSqrtRecF64_mulAddZ31.scala 198:27] + node _T_148 = eq(cyc_B2, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 198:42] + node _T_149 = and(_T_146, _T_148) @[DivSqrtRecF64_mulAddZ31.scala 198:39] + node _T_151 = eq(cyc_B1_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 198:54] + node _T_152 = and(_T_149, _T_151) @[DivSqrtRecF64_mulAddZ31.scala 198:51] + node _T_154 = eq(cyc_C5, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 199:13] + node _T_155 = and(_T_152, _T_154) @[DivSqrtRecF64_mulAddZ31.scala 198:68] + node _T_157 = eq(cyc_C4, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 199:25] + node _T_158 = and(_T_155, _T_157) @[DivSqrtRecF64_mulAddZ31.scala 199:22] + io.inReady_div <= _T_158 @[DivSqrtRecF64_mulAddZ31.scala 195:20] + node _T_160 = eq(cyc_B6_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 201:21] + node _T_161 = and(ready_PA, _T_160) @[DivSqrtRecF64_mulAddZ31.scala 201:18] + node _T_163 = eq(cyc_B5_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 201:38] + node _T_164 = and(_T_161, _T_163) @[DivSqrtRecF64_mulAddZ31.scala 201:35] + node _T_166 = eq(cyc_B4_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 201:55] + node _T_167 = and(_T_164, _T_166) @[DivSqrtRecF64_mulAddZ31.scala 201:52] + node _T_169 = eq(cyc_B2_div, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 202:13] + node _T_170 = and(_T_167, _T_169) @[DivSqrtRecF64_mulAddZ31.scala 201:69] + node _T_172 = eq(cyc_B1_sqrt, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 202:29] + node _T_173 = and(_T_170, _T_172) @[DivSqrtRecF64_mulAddZ31.scala 202:26] + io.inReady_sqrt <= _T_173 @[DivSqrtRecF64_mulAddZ31.scala 200:21] + node _T_174 = and(io.inReady_div, io.inValid) @[DivSqrtRecF64_mulAddZ31.scala 203:38] + node _T_176 = eq(io.sqrtOp, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 203:55] + node cyc_S_div = and(_T_174, _T_176) @[DivSqrtRecF64_mulAddZ31.scala 203:52] + node _T_177 = and(io.inReady_sqrt, io.inValid) @[DivSqrtRecF64_mulAddZ31.scala 204:38] + node cyc_S_sqrt = and(_T_177, io.sqrtOp) @[DivSqrtRecF64_mulAddZ31.scala 204:52] + node cyc_S = or(cyc_S_div, cyc_S_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 205:27] + node signA_S = bits(io.a, 64, 64) @[DivSqrtRecF64_mulAddZ31.scala 207:24] + node expA_S = bits(io.a, 63, 52) @[DivSqrtRecF64_mulAddZ31.scala 208:24] + node fractA_S = bits(io.a, 51, 0) @[DivSqrtRecF64_mulAddZ31.scala 209:24] + node specialCodeA_S = bits(expA_S, 11, 9) @[DivSqrtRecF64_mulAddZ31.scala 210:32] + node isZeroA_S = eq(specialCodeA_S, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 211:40] + node _T_179 = bits(specialCodeA_S, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 212:39] + node isSpecialA_S = eq(_T_179, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 212:46] + node signB_S = bits(io.b, 64, 64) @[DivSqrtRecF64_mulAddZ31.scala 214:24] + node expB_S = bits(io.b, 63, 52) @[DivSqrtRecF64_mulAddZ31.scala 215:24] + node fractB_S = bits(io.b, 51, 0) @[DivSqrtRecF64_mulAddZ31.scala 216:24] + node specialCodeB_S = bits(expB_S, 11, 9) @[DivSqrtRecF64_mulAddZ31.scala 217:32] + node isZeroB_S = eq(specialCodeB_S, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 218:40] + node _T_182 = bits(specialCodeB_S, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 219:39] + node isSpecialB_S = eq(_T_182, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 219:46] + node _T_184 = xor(signA_S, signB_S) @[DivSqrtRecF64_mulAddZ31.scala 221:50] + node sign_S = mux(io.sqrtOp, signB_S, _T_184) @[DivSqrtRecF64_mulAddZ31.scala 221:21] + node _T_186 = eq(isSpecialA_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 224:9] + node _T_188 = eq(isSpecialB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 224:27] + node _T_189 = and(_T_186, _T_188) @[DivSqrtRecF64_mulAddZ31.scala 224:24] + node _T_191 = eq(isZeroA_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 224:45] + node _T_192 = and(_T_189, _T_191) @[DivSqrtRecF64_mulAddZ31.scala 224:42] + node _T_194 = eq(isZeroB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 224:60] + node normalCase_S_div = and(_T_192, _T_194) @[DivSqrtRecF64_mulAddZ31.scala 224:57] + node _T_196 = eq(isSpecialB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 225:29] + node _T_198 = eq(isZeroB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 225:47] + node _T_199 = and(_T_196, _T_198) @[DivSqrtRecF64_mulAddZ31.scala 225:44] + node _T_201 = eq(signB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 225:62] + node normalCase_S_sqrt = and(_T_199, _T_201) @[DivSqrtRecF64_mulAddZ31.scala 225:59] + node normalCase_S = mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) @[DivSqrtRecF64_mulAddZ31.scala 226:27] + node cyc_A4_div = and(cyc_S_div, normalCase_S_div) @[DivSqrtRecF64_mulAddZ31.scala 228:50] + node cyc_A7_sqrt = and(cyc_S_sqrt, normalCase_S_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 229:50] + node entering_PA_normalCase = or(cyc_A4_div, cyc_A7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 231:36] + node _T_203 = eq(ready_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 233:58] + node _T_204 = or(valid_PA, _T_203) @[DivSqrtRecF64_mulAddZ31.scala 233:55] + node _T_205 = and(cyc_S, _T_204) @[DivSqrtRecF64_mulAddZ31.scala 233:42] + node entering_PA = or(entering_PA_normalCase, _T_205) @[DivSqrtRecF64_mulAddZ31.scala 233:32] + node _T_207 = eq(normalCase_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 235:18] + node _T_208 = and(cyc_S, _T_207) @[DivSqrtRecF64_mulAddZ31.scala 235:15] + node _T_210 = eq(valid_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 235:36] + node _T_211 = and(_T_208, _T_210) @[DivSqrtRecF64_mulAddZ31.scala 235:33] + node _T_213 = eq(valid_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 236:29] + node _T_215 = eq(ready_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 236:43] + node _T_216 = and(_T_213, _T_215) @[DivSqrtRecF64_mulAddZ31.scala 236:40] + node _T_217 = or(leaving_PB, _T_216) @[DivSqrtRecF64_mulAddZ31.scala 236:25] + node entering_PB_S = and(_T_211, _T_217) @[DivSqrtRecF64_mulAddZ31.scala 235:47] + node _T_219 = eq(normalCase_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 238:18] + node _T_220 = and(cyc_S, _T_219) @[DivSqrtRecF64_mulAddZ31.scala 238:15] + node _T_222 = eq(valid_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 238:36] + node _T_223 = and(_T_220, _T_222) @[DivSqrtRecF64_mulAddZ31.scala 238:33] + node _T_225 = eq(valid_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 238:50] + node _T_226 = and(_T_223, _T_225) @[DivSqrtRecF64_mulAddZ31.scala 238:47] + node entering_PC_S = and(_T_226, ready_PC) @[DivSqrtRecF64_mulAddZ31.scala 238:61] + node _T_227 = or(entering_PA, leaving_PA) @[DivSqrtRecF64_mulAddZ31.scala 240:23] + when _T_227 : @[DivSqrtRecF64_mulAddZ31.scala 240:38] + valid_PA <= entering_PA @[DivSqrtRecF64_mulAddZ31.scala 241:18] + skip @[DivSqrtRecF64_mulAddZ31.scala 240:38] + when entering_PA : @[DivSqrtRecF64_mulAddZ31.scala 243:24] + sqrtOp_PA <= io.sqrtOp @[DivSqrtRecF64_mulAddZ31.scala 244:25] + sign_PA <= sign_S @[DivSqrtRecF64_mulAddZ31.scala 245:25] + specialCodeB_PA <= specialCodeB_S @[DivSqrtRecF64_mulAddZ31.scala 246:25] + node _T_228 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 247:36] + fractB_51_PA <= _T_228 @[DivSqrtRecF64_mulAddZ31.scala 247:25] + roundingMode_PA <= io.roundingMode @[DivSqrtRecF64_mulAddZ31.scala 248:25] + skip @[DivSqrtRecF64_mulAddZ31.scala 243:24] + node _T_230 = eq(io.sqrtOp, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 250:26] + node _T_231 = and(entering_PA, _T_230) @[DivSqrtRecF64_mulAddZ31.scala 250:23] + when _T_231 : @[DivSqrtRecF64_mulAddZ31.scala 250:39] + specialCodeA_PA <= specialCodeA_S @[DivSqrtRecF64_mulAddZ31.scala 251:25] + node _T_232 = bits(fractA_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 252:36] + fractA_51_PA <= _T_232 @[DivSqrtRecF64_mulAddZ31.scala 252:25] + skip @[DivSqrtRecF64_mulAddZ31.scala 250:39] + when entering_PA_normalCase : @[DivSqrtRecF64_mulAddZ31.scala 254:35] + node _T_233 = bits(expB_S, 11, 11) @[DivSqrtRecF64_mulAddZ31.scala 258:44] + node _T_234 = bits(_T_233, 0, 0) @[Bitwise.scala 71:15] + node _T_237 = mux(_T_234, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 71:12] + node _T_238 = bits(expB_S, 10, 0) @[DivSqrtRecF64_mulAddZ31.scala 258:58] + node _T_239 = not(_T_238) @[DivSqrtRecF64_mulAddZ31.scala 258:51] + node _T_240 = cat(_T_237, _T_239) @[Cat.scala 30:58] + node _T_241 = add(expA_S, _T_240) @[DivSqrtRecF64_mulAddZ31.scala 258:24] + node _T_242 = tail(_T_241, 1) @[DivSqrtRecF64_mulAddZ31.scala 258:24] + node _T_243 = mux(io.sqrtOp, expB_S, _T_242) @[DivSqrtRecF64_mulAddZ31.scala 256:16] + exp_PA <= _T_243 @[DivSqrtRecF64_mulAddZ31.scala 255:16] + node _T_244 = bits(fractB_S, 50, 0) @[DivSqrtRecF64_mulAddZ31.scala 260:36] + fractB_other_PA <= _T_244 @[DivSqrtRecF64_mulAddZ31.scala 260:25] + skip @[DivSqrtRecF64_mulAddZ31.scala 254:35] + when cyc_A4_div : @[DivSqrtRecF64_mulAddZ31.scala 262:39] + node _T_245 = bits(fractA_S, 50, 0) @[DivSqrtRecF64_mulAddZ31.scala 263:36] + fractA_other_PA <= _T_245 @[DivSqrtRecF64_mulAddZ31.scala 263:25] + skip @[DivSqrtRecF64_mulAddZ31.scala 262:39] + node isZeroA_PA = eq(specialCodeA_PA, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 266:42] + node _T_247 = bits(specialCodeA_PA, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 267:41] + node isSpecialA_PA = eq(_T_247, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 267:48] + node _T_250 = cat(UInt<1>("h01"), fractA_51_PA) @[Cat.scala 30:58] + node sigA_PA = cat(_T_250, fractA_other_PA) @[Cat.scala 30:58] + node isZeroB_PA = eq(specialCodeB_PA, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 270:42] + node _T_252 = bits(specialCodeB_PA, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 271:41] + node isSpecialB_PA = eq(_T_252, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 271:48] + node _T_255 = cat(UInt<1>("h01"), fractB_51_PA) @[Cat.scala 30:58] + node sigB_PA = cat(_T_255, fractB_other_PA) @[Cat.scala 30:58] + node _T_257 = eq(isSpecialB_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 276:13] + node _T_259 = eq(isZeroB_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 276:32] + node _T_260 = and(_T_257, _T_259) @[DivSqrtRecF64_mulAddZ31.scala 276:29] + node _T_262 = eq(sign_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 276:48] + node _T_263 = and(_T_260, _T_262) @[DivSqrtRecF64_mulAddZ31.scala 276:45] + node _T_265 = eq(isSpecialA_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 277:13] + node _T_267 = eq(isSpecialB_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 277:32] + node _T_268 = and(_T_265, _T_267) @[DivSqrtRecF64_mulAddZ31.scala 277:29] + node _T_270 = eq(isZeroA_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 277:51] + node _T_271 = and(_T_268, _T_270) @[DivSqrtRecF64_mulAddZ31.scala 277:48] + node _T_273 = eq(isZeroB_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 277:67] + node _T_274 = and(_T_271, _T_273) @[DivSqrtRecF64_mulAddZ31.scala 277:64] + node normalCase_PA = mux(sqrtOp_PA, _T_263, _T_274) @[DivSqrtRecF64_mulAddZ31.scala 275:12] + node valid_normalCase_leaving_PA = or(cyc_B4_div, cyc_B7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 280:50] + node valid_leaving_PA = mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB) @[DivSqrtRecF64_mulAddZ31.scala 282:12] + node _T_275 = and(valid_PA, valid_leaving_PA) @[DivSqrtRecF64_mulAddZ31.scala 283:28] + leaving_PA <= _T_275 @[DivSqrtRecF64_mulAddZ31.scala 283:16] + node _T_277 = eq(valid_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 284:17] + node _T_278 = or(_T_277, valid_leaving_PA) @[DivSqrtRecF64_mulAddZ31.scala 284:28] + ready_PA <= _T_278 @[DivSqrtRecF64_mulAddZ31.scala 284:14] + node _T_279 = and(valid_PA, normalCase_PA) @[DivSqrtRecF64_mulAddZ31.scala 287:18] + node entering_PB_normalCase = and(_T_279, valid_normalCase_leaving_PA) @[DivSqrtRecF64_mulAddZ31.scala 287:35] + node entering_PB = or(entering_PB_S, leaving_PA) @[DivSqrtRecF64_mulAddZ31.scala 288:37] + node _T_280 = or(entering_PB, leaving_PB) @[DivSqrtRecF64_mulAddZ31.scala 290:23] + when _T_280 : @[DivSqrtRecF64_mulAddZ31.scala 290:38] + valid_PB <= entering_PB @[DivSqrtRecF64_mulAddZ31.scala 291:18] + skip @[DivSqrtRecF64_mulAddZ31.scala 290:38] + when entering_PB : @[DivSqrtRecF64_mulAddZ31.scala 293:24] + node _T_281 = mux(valid_PA, sqrtOp_PA, io.sqrtOp) @[DivSqrtRecF64_mulAddZ31.scala 294:31] + sqrtOp_PB <= _T_281 @[DivSqrtRecF64_mulAddZ31.scala 294:25] + node _T_282 = mux(valid_PA, sign_PA, sign_S) @[DivSqrtRecF64_mulAddZ31.scala 295:31] + sign_PB <= _T_282 @[DivSqrtRecF64_mulAddZ31.scala 295:25] + node _T_283 = mux(valid_PA, specialCodeA_PA, specialCodeA_S) @[DivSqrtRecF64_mulAddZ31.scala 296:31] + specialCodeA_PB <= _T_283 @[DivSqrtRecF64_mulAddZ31.scala 296:25] + node _T_284 = bits(fractA_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 297:67] + node _T_285 = mux(valid_PA, fractA_51_PA, _T_284) @[DivSqrtRecF64_mulAddZ31.scala 297:31] + fractA_51_PB <= _T_285 @[DivSqrtRecF64_mulAddZ31.scala 297:25] + node _T_286 = mux(valid_PA, specialCodeB_PA, specialCodeB_S) @[DivSqrtRecF64_mulAddZ31.scala 298:31] + specialCodeB_PB <= _T_286 @[DivSqrtRecF64_mulAddZ31.scala 298:25] + node _T_287 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 299:67] + node _T_288 = mux(valid_PA, fractB_51_PA, _T_287) @[DivSqrtRecF64_mulAddZ31.scala 299:31] + fractB_51_PB <= _T_288 @[DivSqrtRecF64_mulAddZ31.scala 299:25] + node _T_289 = mux(valid_PA, roundingMode_PA, io.roundingMode) @[DivSqrtRecF64_mulAddZ31.scala 300:31] + roundingMode_PB <= _T_289 @[DivSqrtRecF64_mulAddZ31.scala 300:25] + skip @[DivSqrtRecF64_mulAddZ31.scala 293:24] + when entering_PB_normalCase : @[DivSqrtRecF64_mulAddZ31.scala 302:35] + exp_PB <= exp_PA @[DivSqrtRecF64_mulAddZ31.scala 303:25] + node _T_290 = bits(fractA_other_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 304:43] + fractA_0_PB <= _T_290 @[DivSqrtRecF64_mulAddZ31.scala 304:25] + fractB_other_PB <= fractB_other_PA @[DivSqrtRecF64_mulAddZ31.scala 305:25] + skip @[DivSqrtRecF64_mulAddZ31.scala 302:35] + node isZeroA_PB = eq(specialCodeA_PB, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 308:42] + node _T_292 = bits(specialCodeA_PB, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 309:41] + node isSpecialA_PB = eq(_T_292, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 309:48] + node isZeroB_PB = eq(specialCodeB_PB, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 310:42] + node _T_295 = bits(specialCodeB_PB, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 311:41] + node isSpecialB_PB = eq(_T_295, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 311:48] + node _T_298 = eq(isSpecialB_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 314:13] + node _T_300 = eq(isZeroB_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 314:32] + node _T_301 = and(_T_298, _T_300) @[DivSqrtRecF64_mulAddZ31.scala 314:29] + node _T_303 = eq(sign_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 314:48] + node _T_304 = and(_T_301, _T_303) @[DivSqrtRecF64_mulAddZ31.scala 314:45] + node _T_306 = eq(isSpecialA_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 315:13] + node _T_308 = eq(isSpecialB_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 315:32] + node _T_309 = and(_T_306, _T_308) @[DivSqrtRecF64_mulAddZ31.scala 315:29] + node _T_311 = eq(isZeroA_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 315:51] + node _T_312 = and(_T_309, _T_311) @[DivSqrtRecF64_mulAddZ31.scala 315:48] + node _T_314 = eq(isZeroB_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 315:67] + node _T_315 = and(_T_312, _T_314) @[DivSqrtRecF64_mulAddZ31.scala 315:64] + node normalCase_PB = mux(sqrtOp_PB, _T_304, _T_315) @[DivSqrtRecF64_mulAddZ31.scala 313:12] + node valid_leaving_PB = mux(normalCase_PB, cyc_C3, ready_PC) @[DivSqrtRecF64_mulAddZ31.scala 320:12] + node _T_316 = and(valid_PB, valid_leaving_PB) @[DivSqrtRecF64_mulAddZ31.scala 321:28] + leaving_PB <= _T_316 @[DivSqrtRecF64_mulAddZ31.scala 321:16] + node _T_318 = eq(valid_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 322:17] + node _T_319 = or(_T_318, valid_leaving_PB) @[DivSqrtRecF64_mulAddZ31.scala 322:28] + ready_PB <= _T_319 @[DivSqrtRecF64_mulAddZ31.scala 322:14] + node _T_320 = and(valid_PB, normalCase_PB) @[DivSqrtRecF64_mulAddZ31.scala 325:18] + node entering_PC_normalCase = and(_T_320, cyc_C3) @[DivSqrtRecF64_mulAddZ31.scala 325:35] + node entering_PC = or(entering_PC_S, leaving_PB) @[DivSqrtRecF64_mulAddZ31.scala 326:37] + node _T_321 = or(entering_PC, leaving_PC) @[DivSqrtRecF64_mulAddZ31.scala 328:23] + when _T_321 : @[DivSqrtRecF64_mulAddZ31.scala 328:38] + valid_PC <= entering_PC @[DivSqrtRecF64_mulAddZ31.scala 329:18] + skip @[DivSqrtRecF64_mulAddZ31.scala 328:38] + when entering_PC : @[DivSqrtRecF64_mulAddZ31.scala 331:24] + node _T_322 = mux(valid_PB, sqrtOp_PB, io.sqrtOp) @[DivSqrtRecF64_mulAddZ31.scala 332:31] + sqrtOp_PC <= _T_322 @[DivSqrtRecF64_mulAddZ31.scala 332:25] + node _T_323 = mux(valid_PB, sign_PB, sign_S) @[DivSqrtRecF64_mulAddZ31.scala 333:31] + sign_PC <= _T_323 @[DivSqrtRecF64_mulAddZ31.scala 333:25] + node _T_324 = mux(valid_PB, specialCodeA_PB, specialCodeA_S) @[DivSqrtRecF64_mulAddZ31.scala 334:31] + specialCodeA_PC <= _T_324 @[DivSqrtRecF64_mulAddZ31.scala 334:25] + node _T_325 = bits(fractA_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 335:67] + node _T_326 = mux(valid_PB, fractA_51_PB, _T_325) @[DivSqrtRecF64_mulAddZ31.scala 335:31] + fractA_51_PC <= _T_326 @[DivSqrtRecF64_mulAddZ31.scala 335:25] + node _T_327 = mux(valid_PB, specialCodeB_PB, specialCodeB_S) @[DivSqrtRecF64_mulAddZ31.scala 336:31] + specialCodeB_PC <= _T_327 @[DivSqrtRecF64_mulAddZ31.scala 336:25] + node _T_328 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 337:67] + node _T_329 = mux(valid_PB, fractB_51_PB, _T_328) @[DivSqrtRecF64_mulAddZ31.scala 337:31] + fractB_51_PC <= _T_329 @[DivSqrtRecF64_mulAddZ31.scala 337:25] + node _T_330 = mux(valid_PB, roundingMode_PB, io.roundingMode) @[DivSqrtRecF64_mulAddZ31.scala 338:31] + roundingMode_PC <= _T_330 @[DivSqrtRecF64_mulAddZ31.scala 338:25] + skip @[DivSqrtRecF64_mulAddZ31.scala 331:24] + when entering_PC_normalCase : @[DivSqrtRecF64_mulAddZ31.scala 340:35] + exp_PC <= exp_PB @[DivSqrtRecF64_mulAddZ31.scala 341:25] + fractA_0_PC <= fractA_0_PB @[DivSqrtRecF64_mulAddZ31.scala 342:25] + fractB_other_PC <= fractB_other_PB @[DivSqrtRecF64_mulAddZ31.scala 343:25] + skip @[DivSqrtRecF64_mulAddZ31.scala 340:35] + node isZeroA_PC = eq(specialCodeA_PC, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 346:42] + node _T_332 = bits(specialCodeA_PC, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 347:41] + node isSpecialA_PC = eq(_T_332, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 347:48] + node _T_334 = bits(specialCodeA_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 348:59] + node _T_336 = eq(_T_334, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 348:42] + node isInfA_PC = and(isSpecialA_PC, _T_336) @[DivSqrtRecF64_mulAddZ31.scala 348:39] + node _T_337 = bits(specialCodeA_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 349:59] + node isNaNA_PC = and(isSpecialA_PC, _T_337) @[DivSqrtRecF64_mulAddZ31.scala 349:39] + node _T_339 = eq(fractA_51_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 350:38] + node isSigNaNA_PC = and(isNaNA_PC, _T_339) @[DivSqrtRecF64_mulAddZ31.scala 350:35] + node isZeroB_PC = eq(specialCodeB_PC, UInt<3>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 352:42] + node _T_341 = bits(specialCodeB_PC, 2, 1) @[DivSqrtRecF64_mulAddZ31.scala 353:41] + node isSpecialB_PC = eq(_T_341, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 353:48] + node _T_343 = bits(specialCodeB_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 354:59] + node _T_345 = eq(_T_343, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 354:42] + node isInfB_PC = and(isSpecialB_PC, _T_345) @[DivSqrtRecF64_mulAddZ31.scala 354:39] + node _T_346 = bits(specialCodeB_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 355:59] + node isNaNB_PC = and(isSpecialB_PC, _T_346) @[DivSqrtRecF64_mulAddZ31.scala 355:39] + node _T_348 = eq(fractB_51_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 356:38] + node isSigNaNB_PC = and(isNaNB_PC, _T_348) @[DivSqrtRecF64_mulAddZ31.scala 356:35] + node _T_350 = cat(UInt<1>("h01"), fractB_51_PC) @[Cat.scala 30:58] + node sigB_PC = cat(_T_350, fractB_other_PC) @[Cat.scala 30:58] + node _T_352 = eq(isSpecialB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 360:24] + node _T_354 = eq(isZeroB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 360:43] + node _T_355 = and(_T_352, _T_354) @[DivSqrtRecF64_mulAddZ31.scala 360:40] + node _T_357 = eq(sign_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 360:59] + node _T_358 = and(_T_355, _T_357) @[DivSqrtRecF64_mulAddZ31.scala 360:56] + node _T_360 = eq(isSpecialA_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 361:13] + node _T_362 = eq(isSpecialB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 361:32] + node _T_363 = and(_T_360, _T_362) @[DivSqrtRecF64_mulAddZ31.scala 361:29] + node _T_365 = eq(isZeroA_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 361:51] + node _T_366 = and(_T_363, _T_365) @[DivSqrtRecF64_mulAddZ31.scala 361:48] + node _T_368 = eq(isZeroB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 361:67] + node _T_369 = and(_T_366, _T_368) @[DivSqrtRecF64_mulAddZ31.scala 361:64] + node normalCase_PC = mux(sqrtOp_PC, _T_358, _T_369) @[DivSqrtRecF64_mulAddZ31.scala 360:12] + node _T_371 = add(exp_PC, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 363:27] + node expP2_PC = tail(_T_371, 1) @[DivSqrtRecF64_mulAddZ31.scala 363:27] + node _T_372 = bits(exp_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 365:19] + node _T_373 = bits(expP2_PC, 13, 1) @[DivSqrtRecF64_mulAddZ31.scala 366:25] + node _T_375 = cat(_T_373, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_376 = bits(exp_PC, 13, 1) @[DivSqrtRecF64_mulAddZ31.scala 367:23] + node _T_378 = cat(_T_376, UInt<1>("h01")) @[Cat.scala 30:58] + node expP1_PC = mux(_T_372, _T_375, _T_378) @[DivSqrtRecF64_mulAddZ31.scala 365:12] + node roundingMode_near_even_PC = eq(roundingMode_PC, UInt<2>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 370:54] + node roundingMode_minMag_PC = eq(roundingMode_PC, UInt<2>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 371:54] + node roundingMode_min_PC = eq(roundingMode_PC, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 372:54] + node roundingMode_max_PC = eq(roundingMode_PC, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 373:54] + node roundMagUp_PC = mux(sign_PC, roundingMode_min_PC, roundingMode_max_PC) @[DivSqrtRecF64_mulAddZ31.scala 376:12] + node overflowY_roundMagUp_PC = or(roundingMode_near_even_PC, roundMagUp_PC) @[DivSqrtRecF64_mulAddZ31.scala 377:61] + node _T_380 = eq(roundMagUp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 378:27] + node _T_382 = eq(roundingMode_near_even_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 378:46] + node roundMagDown_PC = and(_T_380, _T_382) @[DivSqrtRecF64_mulAddZ31.scala 378:43] + node _T_384 = eq(normalCase_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 380:28] + node valid_leaving_PC = or(_T_384, cyc_E1) @[DivSqrtRecF64_mulAddZ31.scala 380:44] + node _T_385 = and(valid_PC, valid_leaving_PC) @[DivSqrtRecF64_mulAddZ31.scala 381:28] + leaving_PC <= _T_385 @[DivSqrtRecF64_mulAddZ31.scala 381:16] + node _T_387 = eq(valid_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 382:17] + node _T_388 = or(_T_387, valid_leaving_PC) @[DivSqrtRecF64_mulAddZ31.scala 382:28] + ready_PC <= _T_388 @[DivSqrtRecF64_mulAddZ31.scala 382:14] + node _T_390 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 383:39] + node _T_391 = and(leaving_PC, _T_390) @[DivSqrtRecF64_mulAddZ31.scala 383:36] + io.outValid_div <= _T_391 @[DivSqrtRecF64_mulAddZ31.scala 383:22] + node _T_392 = and(leaving_PC, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 384:36] + io.outValid_sqrt <= _T_392 @[DivSqrtRecF64_mulAddZ31.scala 384:22] + node _T_394 = neq(cycleNum_A, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 388:49] + node _T_395 = or(entering_PA_normalCase, _T_394) @[DivSqrtRecF64_mulAddZ31.scala 388:34] + when _T_395 : @[DivSqrtRecF64_mulAddZ31.scala 388:63] + node _T_398 = mux(cyc_A4_div, UInt<2>("h03"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 390:16] + node _T_401 = mux(cyc_A7_sqrt, UInt<3>("h06"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 391:16] + node _T_402 = or(_T_398, _T_401) @[DivSqrtRecF64_mulAddZ31.scala 390:74] + node _T_404 = eq(entering_PA_normalCase, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 392:17] + node _T_406 = sub(cycleNum_A, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 392:54] + node _T_407 = asUInt(_T_406) @[DivSqrtRecF64_mulAddZ31.scala 392:54] + node _T_408 = tail(_T_407, 1) @[DivSqrtRecF64_mulAddZ31.scala 392:54] + node _T_410 = mux(_T_404, _T_408, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 392:16] + node _T_411 = or(_T_402, _T_410) @[DivSqrtRecF64_mulAddZ31.scala 391:74] + cycleNum_A <= _T_411 @[DivSqrtRecF64_mulAddZ31.scala 389:20] + skip @[DivSqrtRecF64_mulAddZ31.scala 388:63] + node cyc_A6_sqrt = eq(cycleNum_A, UInt<3>("h06")) @[DivSqrtRecF64_mulAddZ31.scala 396:35] + node cyc_A5_sqrt = eq(cycleNum_A, UInt<3>("h05")) @[DivSqrtRecF64_mulAddZ31.scala 397:35] + node cyc_A4_sqrt = eq(cycleNum_A, UInt<3>("h04")) @[DivSqrtRecF64_mulAddZ31.scala 398:35] + node cyc_A4 = or(cyc_A4_sqrt, cyc_A4_div) @[DivSqrtRecF64_mulAddZ31.scala 402:30] + node cyc_A3 = eq(cycleNum_A, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 403:30] + node cyc_A2 = eq(cycleNum_A, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 404:30] + node cyc_A1 = eq(cycleNum_A, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 405:30] + node _T_419 = eq(sqrtOp_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 407:32] + node cyc_A3_div = and(cyc_A3, _T_419) @[DivSqrtRecF64_mulAddZ31.scala 407:29] + node _T_421 = eq(sqrtOp_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 408:32] + node cyc_A2_div = and(cyc_A2, _T_421) @[DivSqrtRecF64_mulAddZ31.scala 408:29] + node _T_423 = eq(sqrtOp_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 409:32] + node cyc_A1_div = and(cyc_A1, _T_423) @[DivSqrtRecF64_mulAddZ31.scala 409:29] + node cyc_A3_sqrt = and(cyc_A3, sqrtOp_PA) @[DivSqrtRecF64_mulAddZ31.scala 411:30] + node cyc_A2_sqrt = and(cyc_A2, sqrtOp_PA) @[DivSqrtRecF64_mulAddZ31.scala 412:30] + node cyc_A1_sqrt = and(cyc_A1, sqrtOp_PA) @[DivSqrtRecF64_mulAddZ31.scala 413:30] + node _T_425 = neq(cycleNum_B, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 415:33] + node _T_426 = or(cyc_A1, _T_425) @[DivSqrtRecF64_mulAddZ31.scala 415:18] + when _T_426 : @[DivSqrtRecF64_mulAddZ31.scala 415:47] + node _T_429 = mux(sqrtOp_PA, UInt<4>("h0a"), UInt<3>("h06")) @[DivSqrtRecF64_mulAddZ31.scala 418:20] + node _T_431 = sub(cycleNum_B, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 419:28] + node _T_432 = asUInt(_T_431) @[DivSqrtRecF64_mulAddZ31.scala 419:28] + node _T_433 = tail(_T_432, 1) @[DivSqrtRecF64_mulAddZ31.scala 419:28] + node _T_434 = mux(cyc_A1, _T_429, _T_433) @[DivSqrtRecF64_mulAddZ31.scala 417:16] + cycleNum_B <= _T_434 @[DivSqrtRecF64_mulAddZ31.scala 416:20] + skip @[DivSqrtRecF64_mulAddZ31.scala 415:47] + node _T_436 = eq(cycleNum_B, UInt<4>("h0a")) @[DivSqrtRecF64_mulAddZ31.scala 423:33] + cyc_B10_sqrt <= _T_436 @[DivSqrtRecF64_mulAddZ31.scala 423:18] + node _T_438 = eq(cycleNum_B, UInt<4>("h09")) @[DivSqrtRecF64_mulAddZ31.scala 424:33] + cyc_B9_sqrt <= _T_438 @[DivSqrtRecF64_mulAddZ31.scala 424:18] + node _T_440 = eq(cycleNum_B, UInt<4>("h08")) @[DivSqrtRecF64_mulAddZ31.scala 425:33] + cyc_B8_sqrt <= _T_440 @[DivSqrtRecF64_mulAddZ31.scala 425:18] + node _T_442 = eq(cycleNum_B, UInt<3>("h07")) @[DivSqrtRecF64_mulAddZ31.scala 426:33] + cyc_B7_sqrt <= _T_442 @[DivSqrtRecF64_mulAddZ31.scala 426:18] + node _T_444 = eq(cycleNum_B, UInt<3>("h06")) @[DivSqrtRecF64_mulAddZ31.scala 428:27] + cyc_B6 <= _T_444 @[DivSqrtRecF64_mulAddZ31.scala 428:12] + node _T_446 = eq(cycleNum_B, UInt<3>("h05")) @[DivSqrtRecF64_mulAddZ31.scala 429:27] + cyc_B5 <= _T_446 @[DivSqrtRecF64_mulAddZ31.scala 429:12] + node _T_448 = eq(cycleNum_B, UInt<3>("h04")) @[DivSqrtRecF64_mulAddZ31.scala 430:27] + cyc_B4 <= _T_448 @[DivSqrtRecF64_mulAddZ31.scala 430:12] + node _T_450 = eq(cycleNum_B, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 431:27] + cyc_B3 <= _T_450 @[DivSqrtRecF64_mulAddZ31.scala 431:12] + node _T_452 = eq(cycleNum_B, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 432:27] + cyc_B2 <= _T_452 @[DivSqrtRecF64_mulAddZ31.scala 432:12] + node _T_454 = eq(cycleNum_B, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 433:27] + cyc_B1 <= _T_454 @[DivSqrtRecF64_mulAddZ31.scala 433:12] + node _T_455 = and(cyc_B6, valid_PA) @[DivSqrtRecF64_mulAddZ31.scala 435:26] + node _T_457 = eq(sqrtOp_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 435:41] + node _T_458 = and(_T_455, _T_457) @[DivSqrtRecF64_mulAddZ31.scala 435:38] + cyc_B6_div <= _T_458 @[DivSqrtRecF64_mulAddZ31.scala 435:16] + node _T_459 = and(cyc_B5, valid_PA) @[DivSqrtRecF64_mulAddZ31.scala 436:26] + node _T_461 = eq(sqrtOp_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 436:41] + node _T_462 = and(_T_459, _T_461) @[DivSqrtRecF64_mulAddZ31.scala 436:38] + cyc_B5_div <= _T_462 @[DivSqrtRecF64_mulAddZ31.scala 436:16] + node _T_463 = and(cyc_B4, valid_PA) @[DivSqrtRecF64_mulAddZ31.scala 437:26] + node _T_465 = eq(sqrtOp_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 437:41] + node _T_466 = and(_T_463, _T_465) @[DivSqrtRecF64_mulAddZ31.scala 437:38] + cyc_B4_div <= _T_466 @[DivSqrtRecF64_mulAddZ31.scala 437:16] + node _T_468 = eq(sqrtOp_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 438:29] + node _T_469 = and(cyc_B3, _T_468) @[DivSqrtRecF64_mulAddZ31.scala 438:26] + cyc_B3_div <= _T_469 @[DivSqrtRecF64_mulAddZ31.scala 438:16] + node _T_471 = eq(sqrtOp_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 439:29] + node _T_472 = and(cyc_B2, _T_471) @[DivSqrtRecF64_mulAddZ31.scala 439:26] + cyc_B2_div <= _T_472 @[DivSqrtRecF64_mulAddZ31.scala 439:16] + node _T_474 = eq(sqrtOp_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 440:29] + node _T_475 = and(cyc_B1, _T_474) @[DivSqrtRecF64_mulAddZ31.scala 440:26] + cyc_B1_div <= _T_475 @[DivSqrtRecF64_mulAddZ31.scala 440:16] + node _T_476 = and(cyc_B6, valid_PB) @[DivSqrtRecF64_mulAddZ31.scala 442:27] + node _T_477 = and(_T_476, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 442:39] + cyc_B6_sqrt <= _T_477 @[DivSqrtRecF64_mulAddZ31.scala 442:17] + node _T_478 = and(cyc_B5, valid_PB) @[DivSqrtRecF64_mulAddZ31.scala 443:27] + node _T_479 = and(_T_478, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 443:39] + cyc_B5_sqrt <= _T_479 @[DivSqrtRecF64_mulAddZ31.scala 443:17] + node _T_480 = and(cyc_B4, valid_PB) @[DivSqrtRecF64_mulAddZ31.scala 444:27] + node _T_481 = and(_T_480, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 444:39] + cyc_B4_sqrt <= _T_481 @[DivSqrtRecF64_mulAddZ31.scala 444:17] + node _T_482 = and(cyc_B3, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 445:27] + cyc_B3_sqrt <= _T_482 @[DivSqrtRecF64_mulAddZ31.scala 445:17] + node _T_483 = and(cyc_B2, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 446:27] + cyc_B2_sqrt <= _T_483 @[DivSqrtRecF64_mulAddZ31.scala 446:17] + node _T_484 = and(cyc_B1, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 447:27] + cyc_B1_sqrt <= _T_484 @[DivSqrtRecF64_mulAddZ31.scala 447:17] + node _T_486 = neq(cycleNum_C, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 449:33] + node _T_487 = or(cyc_B1, _T_486) @[DivSqrtRecF64_mulAddZ31.scala 449:18] + when _T_487 : @[DivSqrtRecF64_mulAddZ31.scala 449:47] + node _T_490 = mux(sqrtOp_PB, UInt<3>("h06"), UInt<3>("h05")) @[DivSqrtRecF64_mulAddZ31.scala 451:28] + node _T_492 = sub(cycleNum_C, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 451:70] + node _T_493 = asUInt(_T_492) @[DivSqrtRecF64_mulAddZ31.scala 451:70] + node _T_494 = tail(_T_493, 1) @[DivSqrtRecF64_mulAddZ31.scala 451:70] + node _T_495 = mux(cyc_B1, _T_490, _T_494) @[DivSqrtRecF64_mulAddZ31.scala 451:16] + cycleNum_C <= _T_495 @[DivSqrtRecF64_mulAddZ31.scala 450:20] + skip @[DivSqrtRecF64_mulAddZ31.scala 449:47] + node cyc_C6_sqrt = eq(cycleNum_C, UInt<3>("h06")) @[DivSqrtRecF64_mulAddZ31.scala 454:35] + node _T_498 = eq(cycleNum_C, UInt<3>("h05")) @[DivSqrtRecF64_mulAddZ31.scala 456:27] + cyc_C5 <= _T_498 @[DivSqrtRecF64_mulAddZ31.scala 456:12] + node _T_500 = eq(cycleNum_C, UInt<3>("h04")) @[DivSqrtRecF64_mulAddZ31.scala 457:27] + cyc_C4 <= _T_500 @[DivSqrtRecF64_mulAddZ31.scala 457:12] + node _T_502 = eq(cycleNum_C, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 458:27] + cyc_C3 <= _T_502 @[DivSqrtRecF64_mulAddZ31.scala 458:12] + node _T_504 = eq(cycleNum_C, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 459:27] + cyc_C2 <= _T_504 @[DivSqrtRecF64_mulAddZ31.scala 459:12] + node _T_506 = eq(cycleNum_C, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 460:27] + cyc_C1 <= _T_506 @[DivSqrtRecF64_mulAddZ31.scala 460:12] + node _T_508 = eq(sqrtOp_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 462:32] + node cyc_C5_div = and(cyc_C5, _T_508) @[DivSqrtRecF64_mulAddZ31.scala 462:29] + node _T_510 = eq(sqrtOp_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 463:32] + node cyc_C4_div = and(cyc_C4, _T_510) @[DivSqrtRecF64_mulAddZ31.scala 463:29] + node _T_512 = eq(sqrtOp_PB, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 464:32] + node cyc_C3_div = and(cyc_C3, _T_512) @[DivSqrtRecF64_mulAddZ31.scala 464:29] + node _T_514 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 465:32] + node cyc_C2_div = and(cyc_C2, _T_514) @[DivSqrtRecF64_mulAddZ31.scala 465:29] + node _T_516 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 466:32] + node cyc_C1_div = and(cyc_C1, _T_516) @[DivSqrtRecF64_mulAddZ31.scala 466:29] + node cyc_C5_sqrt = and(cyc_C5, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 468:30] + node cyc_C4_sqrt = and(cyc_C4, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 469:30] + node cyc_C3_sqrt = and(cyc_C3, sqrtOp_PB) @[DivSqrtRecF64_mulAddZ31.scala 470:30] + node cyc_C2_sqrt = and(cyc_C2, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 471:30] + node cyc_C1_sqrt = and(cyc_C1, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 472:30] + node _T_518 = neq(cycleNum_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 474:33] + node _T_519 = or(cyc_C1, _T_518) @[DivSqrtRecF64_mulAddZ31.scala 474:18] + when _T_519 : @[DivSqrtRecF64_mulAddZ31.scala 474:47] + node _T_522 = sub(cycleNum_E, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 475:55] + node _T_523 = asUInt(_T_522) @[DivSqrtRecF64_mulAddZ31.scala 475:55] + node _T_524 = tail(_T_523, 1) @[DivSqrtRecF64_mulAddZ31.scala 475:55] + node _T_525 = mux(cyc_C1, UInt<3>("h04"), _T_524) @[DivSqrtRecF64_mulAddZ31.scala 475:26] + cycleNum_E <= _T_525 @[DivSqrtRecF64_mulAddZ31.scala 475:20] + skip @[DivSqrtRecF64_mulAddZ31.scala 474:47] + node _T_527 = eq(cycleNum_E, UInt<3>("h04")) @[DivSqrtRecF64_mulAddZ31.scala 478:27] + cyc_E4 <= _T_527 @[DivSqrtRecF64_mulAddZ31.scala 478:12] + node _T_529 = eq(cycleNum_E, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 479:27] + cyc_E3 <= _T_529 @[DivSqrtRecF64_mulAddZ31.scala 479:12] + node _T_531 = eq(cycleNum_E, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 480:27] + cyc_E2 <= _T_531 @[DivSqrtRecF64_mulAddZ31.scala 480:12] + node _T_533 = eq(cycleNum_E, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 481:27] + cyc_E1 <= _T_533 @[DivSqrtRecF64_mulAddZ31.scala 481:12] + node _T_535 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 483:32] + node cyc_E4_div = and(cyc_E4, _T_535) @[DivSqrtRecF64_mulAddZ31.scala 483:29] + node _T_537 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 484:32] + node cyc_E3_div = and(cyc_E3, _T_537) @[DivSqrtRecF64_mulAddZ31.scala 484:29] + node _T_539 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 485:32] + node cyc_E2_div = and(cyc_E2, _T_539) @[DivSqrtRecF64_mulAddZ31.scala 485:29] + node _T_541 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 486:32] + node cyc_E1_div = and(cyc_E1, _T_541) @[DivSqrtRecF64_mulAddZ31.scala 486:29] + node cyc_E4_sqrt = and(cyc_E4, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 488:30] + node cyc_E3_sqrt = and(cyc_E3, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 489:30] + node cyc_E2_sqrt = and(cyc_E2, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 490:30] + node cyc_E1_sqrt = and(cyc_E1, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 491:30] + node zFractB_A4_div = mux(cyc_A4_div, fractB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 496:29] + node _T_543 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 498:53] + node _T_545 = eq(_T_543, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 498:62] + node zLinPiece_0_A4_div = and(cyc_A4_div, _T_545) @[DivSqrtRecF64_mulAddZ31.scala 498:41] + node _T_546 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 499:53] + node _T_548 = eq(_T_546, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 499:62] + node zLinPiece_1_A4_div = and(cyc_A4_div, _T_548) @[DivSqrtRecF64_mulAddZ31.scala 499:41] + node _T_549 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 500:53] + node _T_551 = eq(_T_549, UInt<2>("h02")) @[DivSqrtRecF64_mulAddZ31.scala 500:62] + node zLinPiece_2_A4_div = and(cyc_A4_div, _T_551) @[DivSqrtRecF64_mulAddZ31.scala 500:41] + node _T_552 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 501:53] + node _T_554 = eq(_T_552, UInt<2>("h03")) @[DivSqrtRecF64_mulAddZ31.scala 501:62] + node zLinPiece_3_A4_div = and(cyc_A4_div, _T_554) @[DivSqrtRecF64_mulAddZ31.scala 501:41] + node _T_555 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 502:53] + node _T_557 = eq(_T_555, UInt<3>("h04")) @[DivSqrtRecF64_mulAddZ31.scala 502:62] + node zLinPiece_4_A4_div = and(cyc_A4_div, _T_557) @[DivSqrtRecF64_mulAddZ31.scala 502:41] + node _T_558 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 503:53] + node _T_560 = eq(_T_558, UInt<3>("h05")) @[DivSqrtRecF64_mulAddZ31.scala 503:62] + node zLinPiece_5_A4_div = and(cyc_A4_div, _T_560) @[DivSqrtRecF64_mulAddZ31.scala 503:41] + node _T_561 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 504:53] + node _T_563 = eq(_T_561, UInt<3>("h06")) @[DivSqrtRecF64_mulAddZ31.scala 504:62] + node zLinPiece_6_A4_div = and(cyc_A4_div, _T_563) @[DivSqrtRecF64_mulAddZ31.scala 504:41] + node _T_564 = bits(fractB_S, 51, 49) @[DivSqrtRecF64_mulAddZ31.scala 505:53] + node _T_566 = eq(_T_564, UInt<3>("h07")) @[DivSqrtRecF64_mulAddZ31.scala 505:62] + node zLinPiece_7_A4_div = and(cyc_A4_div, _T_566) @[DivSqrtRecF64_mulAddZ31.scala 505:41] + node _T_569 = mux(zLinPiece_0_A4_div, UInt<9>("h01c7"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 507:12] + node _T_572 = mux(zLinPiece_1_A4_div, UInt<9>("h016c"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 508:12] + node _T_573 = or(_T_569, _T_572) @[DivSqrtRecF64_mulAddZ31.scala 507:59] + node _T_576 = mux(zLinPiece_2_A4_div, UInt<9>("h012a"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 509:12] + node _T_577 = or(_T_573, _T_576) @[DivSqrtRecF64_mulAddZ31.scala 508:59] + node _T_580 = mux(zLinPiece_3_A4_div, UInt<9>("h0f8"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 510:12] + node _T_581 = or(_T_577, _T_580) @[DivSqrtRecF64_mulAddZ31.scala 509:59] + node _T_584 = mux(zLinPiece_4_A4_div, UInt<9>("h0d2"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 511:12] + node _T_585 = or(_T_581, _T_584) @[DivSqrtRecF64_mulAddZ31.scala 510:59] + node _T_588 = mux(zLinPiece_5_A4_div, UInt<9>("h0b4"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 512:12] + node _T_589 = or(_T_585, _T_588) @[DivSqrtRecF64_mulAddZ31.scala 511:59] + node _T_592 = mux(zLinPiece_6_A4_div, UInt<9>("h09c"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 513:12] + node _T_593 = or(_T_589, _T_592) @[DivSqrtRecF64_mulAddZ31.scala 512:59] + node _T_596 = mux(zLinPiece_7_A4_div, UInt<9>("h089"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 514:12] + node zK1_A4_div = or(_T_593, _T_596) @[DivSqrtRecF64_mulAddZ31.scala 513:59] + node _T_598 = not(UInt<12>("h0fe3")) @[DivSqrtRecF64_mulAddZ31.scala 516:33] + node _T_600 = mux(zLinPiece_0_A4_div, _T_598, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 516:12] + node _T_602 = not(UInt<12>("h0c5d")) @[DivSqrtRecF64_mulAddZ31.scala 517:33] + node _T_604 = mux(zLinPiece_1_A4_div, _T_602, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 517:12] + node _T_605 = or(_T_600, _T_604) @[DivSqrtRecF64_mulAddZ31.scala 516:61] + node _T_607 = not(UInt<12>("h098a")) @[DivSqrtRecF64_mulAddZ31.scala 518:33] + node _T_609 = mux(zLinPiece_2_A4_div, _T_607, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 518:12] + node _T_610 = or(_T_605, _T_609) @[DivSqrtRecF64_mulAddZ31.scala 517:61] + node _T_612 = not(UInt<12>("h0739")) @[DivSqrtRecF64_mulAddZ31.scala 519:33] + node _T_614 = mux(zLinPiece_3_A4_div, _T_612, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 519:12] + node _T_615 = or(_T_610, _T_614) @[DivSqrtRecF64_mulAddZ31.scala 518:61] + node _T_617 = not(UInt<12>("h054b")) @[DivSqrtRecF64_mulAddZ31.scala 520:33] + node _T_619 = mux(zLinPiece_4_A4_div, _T_617, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 520:12] + node _T_620 = or(_T_615, _T_619) @[DivSqrtRecF64_mulAddZ31.scala 519:61] + node _T_622 = not(UInt<12>("h03a9")) @[DivSqrtRecF64_mulAddZ31.scala 521:33] + node _T_624 = mux(zLinPiece_5_A4_div, _T_622, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 521:12] + node _T_625 = or(_T_620, _T_624) @[DivSqrtRecF64_mulAddZ31.scala 520:61] + node _T_627 = not(UInt<12>("h0242")) @[DivSqrtRecF64_mulAddZ31.scala 522:33] + node _T_629 = mux(zLinPiece_6_A4_div, _T_627, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 522:12] + node _T_630 = or(_T_625, _T_629) @[DivSqrtRecF64_mulAddZ31.scala 521:61] + node _T_632 = not(UInt<12>("h010b")) @[DivSqrtRecF64_mulAddZ31.scala 523:33] + node _T_634 = mux(zLinPiece_7_A4_div, _T_632, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 523:12] + node zComplFractK0_A4_div = or(_T_630, _T_634) @[DivSqrtRecF64_mulAddZ31.scala 522:61] + node zFractB_A7_sqrt = mux(cyc_A7_sqrt, fractB_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 525:30] + node _T_636 = bits(expB_S, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 527:55] + node _T_638 = eq(_T_636, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 527:47] + node _T_639 = and(cyc_A7_sqrt, _T_638) @[DivSqrtRecF64_mulAddZ31.scala 527:44] + node _T_640 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 527:72] + node _T_642 = eq(_T_640, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 527:62] + node zQuadPiece_0_A7_sqrt = and(_T_639, _T_642) @[DivSqrtRecF64_mulAddZ31.scala 527:59] + node _T_643 = bits(expB_S, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 528:55] + node _T_645 = eq(_T_643, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 528:47] + node _T_646 = and(cyc_A7_sqrt, _T_645) @[DivSqrtRecF64_mulAddZ31.scala 528:44] + node _T_647 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 528:72] + node zQuadPiece_1_A7_sqrt = and(_T_646, _T_647) @[DivSqrtRecF64_mulAddZ31.scala 528:59] + node _T_648 = bits(expB_S, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 529:55] + node _T_649 = and(cyc_A7_sqrt, _T_648) @[DivSqrtRecF64_mulAddZ31.scala 529:44] + node _T_650 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 529:72] + node _T_652 = eq(_T_650, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 529:62] + node zQuadPiece_2_A7_sqrt = and(_T_649, _T_652) @[DivSqrtRecF64_mulAddZ31.scala 529:59] + node _T_653 = bits(expB_S, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 530:55] + node _T_654 = and(cyc_A7_sqrt, _T_653) @[DivSqrtRecF64_mulAddZ31.scala 530:44] + node _T_655 = bits(fractB_S, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 530:72] + node zQuadPiece_3_A7_sqrt = and(_T_654, _T_655) @[DivSqrtRecF64_mulAddZ31.scala 530:59] + node _T_658 = mux(zQuadPiece_0_A7_sqrt, UInt<9>("h01c8"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 532:12] + node _T_661 = mux(zQuadPiece_1_A7_sqrt, UInt<9>("h0c1"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 533:12] + node _T_662 = or(_T_658, _T_661) @[DivSqrtRecF64_mulAddZ31.scala 532:61] + node _T_665 = mux(zQuadPiece_2_A7_sqrt, UInt<9>("h0143"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 534:12] + node _T_666 = or(_T_662, _T_665) @[DivSqrtRecF64_mulAddZ31.scala 533:61] + node _T_669 = mux(zQuadPiece_3_A7_sqrt, UInt<9>("h089"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 535:12] + node zK2_A7_sqrt = or(_T_666, _T_669) @[DivSqrtRecF64_mulAddZ31.scala 534:61] + node _T_671 = not(UInt<10>("h03d0")) @[DivSqrtRecF64_mulAddZ31.scala 537:35] + node _T_673 = mux(zQuadPiece_0_A7_sqrt, _T_671, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 537:12] + node _T_675 = not(UInt<10>("h0220")) @[DivSqrtRecF64_mulAddZ31.scala 538:35] + node _T_677 = mux(zQuadPiece_1_A7_sqrt, _T_675, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 538:12] + node _T_678 = or(_T_673, _T_677) @[DivSqrtRecF64_mulAddZ31.scala 537:63] + node _T_680 = not(UInt<10>("h02b2")) @[DivSqrtRecF64_mulAddZ31.scala 539:35] + node _T_682 = mux(zQuadPiece_2_A7_sqrt, _T_680, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 539:12] + node _T_683 = or(_T_678, _T_682) @[DivSqrtRecF64_mulAddZ31.scala 538:63] + node _T_685 = not(UInt<10>("h0181")) @[DivSqrtRecF64_mulAddZ31.scala 540:35] + node _T_687 = mux(zQuadPiece_3_A7_sqrt, _T_685, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 540:12] + node zComplK1_A7_sqrt = or(_T_683, _T_687) @[DivSqrtRecF64_mulAddZ31.scala 539:63] + node _T_688 = bits(exp_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 542:55] + node _T_690 = eq(_T_688, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 542:47] + node _T_691 = and(cyc_A6_sqrt, _T_690) @[DivSqrtRecF64_mulAddZ31.scala 542:44] + node _T_692 = bits(sigB_PA, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 542:71] + node _T_694 = eq(_T_692, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 542:62] + node zQuadPiece_0_A6_sqrt = and(_T_691, _T_694) @[DivSqrtRecF64_mulAddZ31.scala 542:59] + node _T_695 = bits(exp_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 543:55] + node _T_697 = eq(_T_695, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 543:47] + node _T_698 = and(cyc_A6_sqrt, _T_697) @[DivSqrtRecF64_mulAddZ31.scala 543:44] + node _T_699 = bits(sigB_PA, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 543:71] + node zQuadPiece_1_A6_sqrt = and(_T_698, _T_699) @[DivSqrtRecF64_mulAddZ31.scala 543:59] + node _T_700 = bits(exp_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 544:55] + node _T_701 = and(cyc_A6_sqrt, _T_700) @[DivSqrtRecF64_mulAddZ31.scala 544:44] + node _T_702 = bits(sigB_PA, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 544:71] + node _T_704 = eq(_T_702, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 544:62] + node zQuadPiece_2_A6_sqrt = and(_T_701, _T_704) @[DivSqrtRecF64_mulAddZ31.scala 544:59] + node _T_705 = bits(exp_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 545:55] + node _T_706 = and(cyc_A6_sqrt, _T_705) @[DivSqrtRecF64_mulAddZ31.scala 545:44] + node _T_707 = bits(sigB_PA, 51, 51) @[DivSqrtRecF64_mulAddZ31.scala 545:71] + node zQuadPiece_3_A6_sqrt = and(_T_706, _T_707) @[DivSqrtRecF64_mulAddZ31.scala 545:59] + node _T_709 = not(UInt<13>("h01fe5")) @[DivSqrtRecF64_mulAddZ31.scala 547:35] + node _T_711 = mux(zQuadPiece_0_A6_sqrt, _T_709, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 547:12] + node _T_713 = not(UInt<13>("h01435")) @[DivSqrtRecF64_mulAddZ31.scala 548:35] + node _T_715 = mux(zQuadPiece_1_A6_sqrt, _T_713, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 548:12] + node _T_716 = or(_T_711, _T_715) @[DivSqrtRecF64_mulAddZ31.scala 547:64] + node _T_718 = not(UInt<13>("h0d2c")) @[DivSqrtRecF64_mulAddZ31.scala 549:35] + node _T_720 = mux(zQuadPiece_2_A6_sqrt, _T_718, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 549:12] + node _T_721 = or(_T_716, _T_720) @[DivSqrtRecF64_mulAddZ31.scala 548:64] + node _T_723 = not(UInt<13>("h04e8")) @[DivSqrtRecF64_mulAddZ31.scala 550:35] + node _T_725 = mux(zQuadPiece_3_A6_sqrt, _T_723, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 550:12] + node zComplFractK0_A6_sqrt = or(_T_721, _T_725) @[DivSqrtRecF64_mulAddZ31.scala 549:64] + node _T_726 = bits(zFractB_A4_div, 48, 40) @[DivSqrtRecF64_mulAddZ31.scala 553:23] + node _T_727 = or(_T_726, zK2_A7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 553:32] + node _T_729 = eq(cyc_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 554:17] + node _T_731 = mux(_T_729, nextMulAdd9A_A, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 554:16] + node mulAdd9A_A = or(_T_727, _T_731) @[DivSqrtRecF64_mulAddZ31.scala 553:46] + node _T_732 = bits(zFractB_A7_sqrt, 50, 42) @[DivSqrtRecF64_mulAddZ31.scala 556:37] + node _T_733 = or(zK1_A4_div, _T_732) @[DivSqrtRecF64_mulAddZ31.scala 556:20] + node _T_735 = eq(cyc_S, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 557:17] + node _T_737 = mux(_T_735, nextMulAdd9B_A, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 557:16] + node mulAdd9B_A = or(_T_733, _T_737) @[DivSqrtRecF64_mulAddZ31.scala 556:46] + node _T_738 = bits(cyc_A7_sqrt, 0, 0) @[Bitwise.scala 71:15] + node _T_741 = mux(_T_738, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 71:12] + node _T_742 = cat(zComplK1_A7_sqrt, _T_741) @[Cat.scala 30:58] + node _T_743 = bits(cyc_A6_sqrt, 0, 0) @[Bitwise.scala 71:15] + node _T_746 = mux(_T_743, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 71:12] + node _T_747 = cat(cyc_A6_sqrt, zComplFractK0_A6_sqrt) @[Cat.scala 30:58] + node _T_748 = cat(_T_747, _T_746) @[Cat.scala 30:58] + node _T_749 = or(_T_742, _T_748) @[DivSqrtRecF64_mulAddZ31.scala 559:71] + node _T_750 = bits(cyc_A4_div, 0, 0) @[Bitwise.scala 71:15] + node _T_753 = mux(_T_750, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 71:12] + node _T_754 = cat(cyc_A4_div, zComplFractK0_A4_div) @[Cat.scala 30:58] + node _T_755 = cat(_T_754, _T_753) @[Cat.scala 30:58] + node _T_756 = or(_T_749, _T_755) @[DivSqrtRecF64_mulAddZ31.scala 560:71] + node _T_758 = shl(fractR0_A, 10) @[DivSqrtRecF64_mulAddZ31.scala 563:54] + node _T_759 = add(UInt<20>("h040000"), _T_758) @[DivSqrtRecF64_mulAddZ31.scala 563:42] + node _T_760 = tail(_T_759, 1) @[DivSqrtRecF64_mulAddZ31.scala 563:42] + node _T_762 = mux(cyc_A5_sqrt, _T_760, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 563:12] + node _T_763 = or(_T_756, _T_762) @[DivSqrtRecF64_mulAddZ31.scala 561:71] + node _T_764 = bits(hiSqrR0_A_sqrt, 9, 9) @[DivSqrtRecF64_mulAddZ31.scala 564:44] + node _T_766 = eq(_T_764, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 564:28] + node _T_767 = and(cyc_A4_sqrt, _T_766) @[DivSqrtRecF64_mulAddZ31.scala 564:25] + node _T_770 = mux(_T_767, UInt<11>("h0400"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 564:12] + node _T_771 = or(_T_763, _T_770) @[DivSqrtRecF64_mulAddZ31.scala 563:70] + node _T_772 = bits(hiSqrR0_A_sqrt, 9, 9) @[DivSqrtRecF64_mulAddZ31.scala 565:43] + node _T_773 = and(cyc_A4_sqrt, _T_772) @[DivSqrtRecF64_mulAddZ31.scala 565:26] + node _T_774 = or(_T_773, cyc_A3_div) @[DivSqrtRecF64_mulAddZ31.scala 565:48] + node _T_775 = bits(sigB_PA, 46, 26) @[DivSqrtRecF64_mulAddZ31.scala 566:20] + node _T_777 = add(_T_775, UInt<11>("h0400")) @[DivSqrtRecF64_mulAddZ31.scala 566:29] + node _T_778 = tail(_T_777, 1) @[DivSqrtRecF64_mulAddZ31.scala 566:29] + node _T_780 = mux(_T_774, _T_778, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 565:12] + node _T_781 = or(_T_771, _T_780) @[DivSqrtRecF64_mulAddZ31.scala 564:71] + node _T_782 = or(cyc_A3_sqrt, cyc_A2) @[DivSqrtRecF64_mulAddZ31.scala 569:25] + node _T_784 = mux(_T_782, partNegSigma0_A, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 569:12] + node _T_785 = or(_T_781, _T_784) @[DivSqrtRecF64_mulAddZ31.scala 568:11] + node _T_786 = shl(fractR0_A, 16) @[DivSqrtRecF64_mulAddZ31.scala 570:45] + node _T_788 = mux(cyc_A1_sqrt, _T_786, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 570:12] + node _T_789 = or(_T_785, _T_788) @[DivSqrtRecF64_mulAddZ31.scala 569:62] + node _T_790 = shl(fractR0_A, 15) @[DivSqrtRecF64_mulAddZ31.scala 571:45] + node _T_792 = mux(cyc_A1_div, _T_790, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 571:12] + node mulAdd9C_A = or(_T_789, _T_792) @[DivSqrtRecF64_mulAddZ31.scala 570:62] + node _T_793 = mul(mulAdd9A_A, mulAdd9B_A) @[DivSqrtRecF64_mulAddZ31.scala 573:20] + node _T_795 = bits(mulAdd9C_A, 17, 0) @[DivSqrtRecF64_mulAddZ31.scala 573:61] + node _T_796 = cat(UInt<1>("h00"), _T_795) @[Cat.scala 30:58] + node _T_797 = add(_T_793, _T_796) @[DivSqrtRecF64_mulAddZ31.scala 573:33] + node loMulAdd9Out_A = tail(_T_797, 1) @[DivSqrtRecF64_mulAddZ31.scala 573:33] + node _T_798 = bits(loMulAdd9Out_A, 18, 18) @[DivSqrtRecF64_mulAddZ31.scala 575:31] + node _T_799 = bits(mulAdd9C_A, 24, 18) @[DivSqrtRecF64_mulAddZ31.scala 576:27] + node _T_801 = add(_T_799, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 576:36] + node _T_802 = tail(_T_801, 1) @[DivSqrtRecF64_mulAddZ31.scala 576:36] + node _T_803 = bits(mulAdd9C_A, 24, 18) @[DivSqrtRecF64_mulAddZ31.scala 577:27] + node _T_804 = mux(_T_798, _T_802, _T_803) @[DivSqrtRecF64_mulAddZ31.scala 575:16] + node _T_805 = bits(loMulAdd9Out_A, 17, 0) @[DivSqrtRecF64_mulAddZ31.scala 579:27] + node mulAdd9Out_A = cat(_T_804, _T_805) @[Cat.scala 30:58] + node _T_806 = bits(mulAdd9Out_A, 19, 19) @[DivSqrtRecF64_mulAddZ31.scala 583:40] + node _T_807 = and(cyc_A6_sqrt, _T_806) @[DivSqrtRecF64_mulAddZ31.scala 583:25] + node _T_808 = not(mulAdd9Out_A) @[DivSqrtRecF64_mulAddZ31.scala 584:13] + node _T_809 = shr(_T_808, 10) @[DivSqrtRecF64_mulAddZ31.scala 584:26] + node _T_811 = mux(_T_807, _T_809, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 583:12] + node zFractR0_A6_sqrt = bits(_T_811, 8, 0) @[DivSqrtRecF64_mulAddZ31.scala 586:10] + node _T_812 = bits(exp_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 590:35] + node _T_813 = shl(mulAdd9Out_A, 1) @[DivSqrtRecF64_mulAddZ31.scala 590:52] + node sqrR0_A5_sqrt = mux(_T_812, _T_813, mulAdd9Out_A) @[DivSqrtRecF64_mulAddZ31.scala 590:28] + node _T_814 = bits(mulAdd9Out_A, 20, 20) @[DivSqrtRecF64_mulAddZ31.scala 592:39] + node _T_815 = and(cyc_A4_div, _T_814) @[DivSqrtRecF64_mulAddZ31.scala 592:24] + node _T_816 = not(mulAdd9Out_A) @[DivSqrtRecF64_mulAddZ31.scala 593:13] + node _T_817 = shr(_T_816, 11) @[DivSqrtRecF64_mulAddZ31.scala 593:26] + node _T_819 = mux(_T_815, _T_817, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 592:12] + node zFractR0_A4_div = bits(_T_819, 8, 0) @[DivSqrtRecF64_mulAddZ31.scala 595:10] + node _T_820 = bits(mulAdd9Out_A, 11, 11) @[DivSqrtRecF64_mulAddZ31.scala 598:35] + node _T_821 = and(cyc_A2, _T_820) @[DivSqrtRecF64_mulAddZ31.scala 598:20] + node _T_822 = not(mulAdd9Out_A) @[DivSqrtRecF64_mulAddZ31.scala 598:41] + node _T_823 = shr(_T_822, 2) @[DivSqrtRecF64_mulAddZ31.scala 598:54] + node _T_825 = mux(_T_821, _T_823, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 598:12] + node zSigma0_A2 = bits(_T_825, 8, 0) @[DivSqrtRecF64_mulAddZ31.scala 598:67] + node _T_826 = shr(mulAdd9Out_A, 10) @[DivSqrtRecF64_mulAddZ31.scala 601:36] + node _T_827 = shr(mulAdd9Out_A, 9) @[DivSqrtRecF64_mulAddZ31.scala 601:54] + node _T_828 = mux(sqrtOp_PA, _T_826, _T_827) @[DivSqrtRecF64_mulAddZ31.scala 601:12] + node fractR1_A1 = bits(_T_828, 14, 0) @[DivSqrtRecF64_mulAddZ31.scala 601:58] + node r1_A1 = cat(UInt<1>("h01"), fractR1_A1) @[Cat.scala 30:58] + node _T_830 = bits(exp_PA, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 603:33] + node _T_831 = shl(r1_A1, 1) @[DivSqrtRecF64_mulAddZ31.scala 603:43] + node ER1_A1_sqrt = mux(_T_830, _T_831, r1_A1) @[DivSqrtRecF64_mulAddZ31.scala 603:26] + node _T_832 = or(cyc_A6_sqrt, cyc_A4_div) @[DivSqrtRecF64_mulAddZ31.scala 605:23] + when _T_832 : @[DivSqrtRecF64_mulAddZ31.scala 605:38] + node _T_833 = or(zFractR0_A6_sqrt, zFractR0_A4_div) @[DivSqrtRecF64_mulAddZ31.scala 606:39] + fractR0_A <= _T_833 @[DivSqrtRecF64_mulAddZ31.scala 606:19] + skip @[DivSqrtRecF64_mulAddZ31.scala 605:38] + when cyc_A5_sqrt : @[DivSqrtRecF64_mulAddZ31.scala 609:24] + node _T_834 = shr(sqrR0_A5_sqrt, 10) @[DivSqrtRecF64_mulAddZ31.scala 610:40] + hiSqrR0_A_sqrt <= _T_834 @[DivSqrtRecF64_mulAddZ31.scala 610:24] + skip @[DivSqrtRecF64_mulAddZ31.scala 609:24] + node _T_835 = or(cyc_A4_sqrt, cyc_A3) @[DivSqrtRecF64_mulAddZ31.scala 613:23] + when _T_835 : @[DivSqrtRecF64_mulAddZ31.scala 613:34] + node _T_836 = shr(mulAdd9Out_A, 9) @[DivSqrtRecF64_mulAddZ31.scala 616:56] + node _T_837 = mux(cyc_A4_sqrt, mulAdd9Out_A, _T_836) @[DivSqrtRecF64_mulAddZ31.scala 616:16] + node _T_838 = bits(_T_837, 20, 0) @[DivSqrtRecF64_mulAddZ31.scala 616:60] + partNegSigma0_A <= _T_838 @[DivSqrtRecF64_mulAddZ31.scala 615:25] + skip @[DivSqrtRecF64_mulAddZ31.scala 613:34] + node _T_839 = or(cyc_A7_sqrt, cyc_A6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 620:21] + node _T_840 = or(_T_839, cyc_A5_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 620:36] + node _T_841 = or(_T_840, cyc_A4) @[DivSqrtRecF64_mulAddZ31.scala 620:51] + node _T_842 = or(_T_841, cyc_A3) @[DivSqrtRecF64_mulAddZ31.scala 620:61] + node _T_843 = or(_T_842, cyc_A2) @[DivSqrtRecF64_mulAddZ31.scala 620:71] + when _T_843 : @[DivSqrtRecF64_mulAddZ31.scala 621:7] + node _T_844 = not(mulAdd9Out_A) @[DivSqrtRecF64_mulAddZ31.scala 623:40] + node _T_845 = shr(_T_844, 11) @[DivSqrtRecF64_mulAddZ31.scala 623:53] + node _T_847 = mux(cyc_A7_sqrt, _T_845, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 623:16] + node _T_848 = or(_T_847, zFractR0_A6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 623:68] + node _T_849 = bits(sigB_PA, 43, 35) @[DivSqrtRecF64_mulAddZ31.scala 625:47] + node _T_851 = mux(cyc_A4_sqrt, _T_849, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 625:16] + node _T_852 = or(_T_848, _T_851) @[DivSqrtRecF64_mulAddZ31.scala 624:68] + node _T_853 = bits(zFractB_A4_div, 43, 35) @[DivSqrtRecF64_mulAddZ31.scala 626:27] + node _T_854 = or(_T_852, _T_853) @[DivSqrtRecF64_mulAddZ31.scala 625:68] + node _T_855 = or(cyc_A5_sqrt, cyc_A3) @[DivSqrtRecF64_mulAddZ31.scala 627:29] + node _T_856 = bits(sigB_PA, 52, 44) @[DivSqrtRecF64_mulAddZ31.scala 627:47] + node _T_858 = mux(_T_855, _T_856, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 627:16] + node _T_859 = or(_T_854, _T_858) @[DivSqrtRecF64_mulAddZ31.scala 626:68] + node _T_860 = or(_T_859, zSigma0_A2) @[DivSqrtRecF64_mulAddZ31.scala 627:68] + nextMulAdd9A_A <= _T_860 @[DivSqrtRecF64_mulAddZ31.scala 622:24] + skip @[DivSqrtRecF64_mulAddZ31.scala 621:7] + node _T_861 = or(cyc_A7_sqrt, cyc_A6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 630:23] + node _T_862 = or(_T_861, cyc_A5_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 630:38] + node _T_863 = or(_T_862, cyc_A4) @[DivSqrtRecF64_mulAddZ31.scala 630:53] + node _T_864 = or(_T_863, cyc_A2) @[DivSqrtRecF64_mulAddZ31.scala 630:63] + when _T_864 : @[DivSqrtRecF64_mulAddZ31.scala 630:74] + node _T_865 = bits(zFractB_A7_sqrt, 50, 42) @[DivSqrtRecF64_mulAddZ31.scala 632:28] + node _T_866 = or(_T_865, zFractR0_A6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 632:73] + node _T_867 = bits(sqrR0_A5_sqrt, 9, 1) @[DivSqrtRecF64_mulAddZ31.scala 634:43] + node _T_869 = mux(cyc_A5_sqrt, _T_867, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 634:16] + node _T_870 = or(_T_866, _T_869) @[DivSqrtRecF64_mulAddZ31.scala 633:73] + node _T_871 = or(_T_870, zFractR0_A4_div) @[DivSqrtRecF64_mulAddZ31.scala 634:73] + node _T_872 = bits(hiSqrR0_A_sqrt, 8, 0) @[DivSqrtRecF64_mulAddZ31.scala 636:44] + node _T_874 = mux(cyc_A4_sqrt, _T_872, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 636:16] + node _T_875 = or(_T_871, _T_874) @[DivSqrtRecF64_mulAddZ31.scala 635:73] + node _T_877 = bits(fractR0_A, 8, 1) @[DivSqrtRecF64_mulAddZ31.scala 637:55] + node _T_878 = cat(UInt<1>("h01"), _T_877) @[Cat.scala 30:58] + node _T_880 = mux(cyc_A2, _T_878, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 637:16] + node _T_881 = or(_T_875, _T_880) @[DivSqrtRecF64_mulAddZ31.scala 636:73] + nextMulAdd9B_A <= _T_881 @[DivSqrtRecF64_mulAddZ31.scala 631:24] + skip @[DivSqrtRecF64_mulAddZ31.scala 630:74] + when cyc_A1_sqrt : @[DivSqrtRecF64_mulAddZ31.scala 640:24] + ER1_B_sqrt <= ER1_A1_sqrt @[DivSqrtRecF64_mulAddZ31.scala 641:20] + skip @[DivSqrtRecF64_mulAddZ31.scala 640:24] + node _T_882 = or(cyc_A1, cyc_B7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 647:16] + node _T_883 = or(_T_882, cyc_B6_div) @[DivSqrtRecF64_mulAddZ31.scala 647:31] + node _T_884 = or(_T_883, cyc_B4) @[DivSqrtRecF64_mulAddZ31.scala 647:45] + node _T_885 = or(_T_884, cyc_B3) @[DivSqrtRecF64_mulAddZ31.scala 647:55] + node _T_886 = or(_T_885, cyc_C6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 647:65] + node _T_887 = or(_T_886, cyc_C4) @[DivSqrtRecF64_mulAddZ31.scala 648:25] + node _T_888 = or(_T_887, cyc_C1) @[DivSqrtRecF64_mulAddZ31.scala 648:35] + io.latchMulAddA_0 <= _T_888 @[DivSqrtRecF64_mulAddZ31.scala 646:23] + node _T_889 = shl(ER1_A1_sqrt, 36) @[DivSqrtRecF64_mulAddZ31.scala 650:51] + node _T_891 = mux(cyc_A1_sqrt, _T_889, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 650:12] + node _T_892 = or(cyc_B7_sqrt, cyc_A1_div) @[DivSqrtRecF64_mulAddZ31.scala 651:25] + node _T_894 = mux(_T_892, sigB_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 651:12] + node _T_895 = or(_T_891, _T_894) @[DivSqrtRecF64_mulAddZ31.scala 650:67] + node _T_897 = mux(cyc_B6_div, sigA_PA, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 652:12] + node _T_898 = or(_T_895, _T_897) @[DivSqrtRecF64_mulAddZ31.scala 651:67] + node _T_899 = bits(zSigma1_B4, 45, 12) @[DivSqrtRecF64_mulAddZ31.scala 653:19] + node _T_900 = or(_T_898, _T_899) @[DivSqrtRecF64_mulAddZ31.scala 652:67] + node _T_901 = or(cyc_B3, cyc_C6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 655:20] + node _T_902 = bits(sigXNU_B3_CX, 57, 12) @[DivSqrtRecF64_mulAddZ31.scala 655:48] + node _T_904 = mux(_T_901, _T_902, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 655:12] + node _T_905 = or(_T_900, _T_904) @[DivSqrtRecF64_mulAddZ31.scala 653:67] + node _T_906 = bits(sigXN_C, 57, 25) @[DivSqrtRecF64_mulAddZ31.scala 656:43] + node _T_907 = shl(_T_906, 13) @[DivSqrtRecF64_mulAddZ31.scala 656:51] + node _T_909 = mux(cyc_C4_div, _T_907, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 656:12] + node _T_910 = or(_T_905, _T_909) @[DivSqrtRecF64_mulAddZ31.scala 655:67] + node _T_911 = shl(u_C_sqrt, 15) @[DivSqrtRecF64_mulAddZ31.scala 657:44] + node _T_913 = mux(cyc_C4_sqrt, _T_911, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 657:12] + node _T_914 = or(_T_910, _T_913) @[DivSqrtRecF64_mulAddZ31.scala 656:67] + node _T_916 = mux(cyc_C1_div, sigB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 658:12] + node _T_917 = or(_T_914, _T_916) @[DivSqrtRecF64_mulAddZ31.scala 657:67] + node _T_918 = or(_T_917, zComplSigT_C1_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 658:67] + io.mulAddA_0 <= _T_918 @[DivSqrtRecF64_mulAddZ31.scala 649:18] + node _T_919 = or(cyc_A1, cyc_B7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 661:16] + node _T_920 = or(_T_919, cyc_B6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 661:31] + node _T_921 = or(_T_920, cyc_B4) @[DivSqrtRecF64_mulAddZ31.scala 661:46] + node _T_922 = or(_T_921, cyc_C6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 661:56] + node _T_923 = or(_T_922, cyc_C4) @[DivSqrtRecF64_mulAddZ31.scala 662:25] + node _T_924 = or(_T_923, cyc_C1) @[DivSqrtRecF64_mulAddZ31.scala 662:35] + io.latchMulAddB_0 <= _T_924 @[DivSqrtRecF64_mulAddZ31.scala 660:23] + node _T_925 = shl(r1_A1, 36) @[DivSqrtRecF64_mulAddZ31.scala 664:31] + node _T_927 = mux(cyc_A1, _T_925, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 664:12] + node _T_928 = shl(ESqrR1_B_sqrt, 19) @[DivSqrtRecF64_mulAddZ31.scala 665:39] + node _T_930 = mux(cyc_B7_sqrt, _T_928, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 665:12] + node _T_931 = or(_T_927, _T_930) @[DivSqrtRecF64_mulAddZ31.scala 664:55] + node _T_932 = shl(ER1_B_sqrt, 36) @[DivSqrtRecF64_mulAddZ31.scala 666:36] + node _T_934 = mux(cyc_B6_sqrt, _T_932, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 666:12] + node _T_935 = or(_T_931, _T_934) @[DivSqrtRecF64_mulAddZ31.scala 665:55] + node _T_936 = or(_T_935, zSigma1_B4) @[DivSqrtRecF64_mulAddZ31.scala 666:55] + node _T_937 = bits(sqrSigma1_C, 30, 1) @[DivSqrtRecF64_mulAddZ31.scala 668:37] + node _T_939 = mux(cyc_C6_sqrt, _T_937, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 668:12] + node _T_940 = or(_T_936, _T_939) @[DivSqrtRecF64_mulAddZ31.scala 667:55] + node _T_942 = mux(cyc_C4, sqrSigma1_C, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 669:12] + node _T_943 = or(_T_940, _T_942) @[DivSqrtRecF64_mulAddZ31.scala 668:55] + node _T_944 = or(_T_943, zComplSigT_C1) @[DivSqrtRecF64_mulAddZ31.scala 669:55] + io.mulAddB_0 <= _T_944 @[DivSqrtRecF64_mulAddZ31.scala 663:18] + node _T_945 = or(cyc_A4, cyc_A3_div) @[DivSqrtRecF64_mulAddZ31.scala 672:20] + node _T_946 = or(_T_945, cyc_A1_div) @[DivSqrtRecF64_mulAddZ31.scala 672:34] + node _T_947 = or(_T_946, cyc_B10_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 672:48] + node _T_948 = or(_T_947, cyc_B9_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 673:30] + node _T_949 = or(_T_948, cyc_B7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 673:45] + node _T_950 = or(_T_949, cyc_B6) @[DivSqrtRecF64_mulAddZ31.scala 673:60] + node _T_951 = or(_T_950, cyc_B5_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 673:70] + node _T_952 = or(_T_951, cyc_B3_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 674:29] + node _T_953 = or(_T_952, cyc_B2_div) @[DivSqrtRecF64_mulAddZ31.scala 674:44] + node _T_954 = or(_T_953, cyc_B1_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 674:58] + node _T_955 = or(_T_954, cyc_C4) @[DivSqrtRecF64_mulAddZ31.scala 674:73] + node _T_956 = or(cyc_A3, cyc_A2_div) @[DivSqrtRecF64_mulAddZ31.scala 676:20] + node _T_957 = or(_T_956, cyc_B9_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 676:34] + node _T_958 = or(_T_957, cyc_B8_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 677:29] + node _T_959 = or(_T_958, cyc_B6) @[DivSqrtRecF64_mulAddZ31.scala 677:44] + node _T_960 = or(_T_959, cyc_B5) @[DivSqrtRecF64_mulAddZ31.scala 677:54] + node _T_961 = or(_T_960, cyc_B4_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 677:64] + node _T_962 = or(_T_961, cyc_B2_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 678:29] + node _T_963 = or(_T_962, cyc_B1_div) @[DivSqrtRecF64_mulAddZ31.scala 678:44] + node _T_964 = or(_T_963, cyc_C6_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 678:58] + node _T_965 = or(_T_964, cyc_C3) @[DivSqrtRecF64_mulAddZ31.scala 678:73] + node _T_966 = or(cyc_A2, cyc_A1_div) @[DivSqrtRecF64_mulAddZ31.scala 680:20] + node _T_967 = or(_T_966, cyc_B8_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 680:34] + node _T_968 = or(_T_967, cyc_B7_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 681:29] + node _T_969 = or(_T_968, cyc_B5) @[DivSqrtRecF64_mulAddZ31.scala 681:44] + node _T_970 = or(_T_969, cyc_B4) @[DivSqrtRecF64_mulAddZ31.scala 681:54] + node _T_971 = or(_T_970, cyc_B3_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 681:64] + node _T_972 = or(_T_971, cyc_B1_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 682:29] + node _T_973 = or(_T_972, cyc_C5) @[DivSqrtRecF64_mulAddZ31.scala 682:44] + node _T_974 = or(_T_973, cyc_C2) @[DivSqrtRecF64_mulAddZ31.scala 682:54] + node _T_975 = or(io.latchMulAddA_0, cyc_B6) @[DivSqrtRecF64_mulAddZ31.scala 684:31] + node _T_976 = or(_T_975, cyc_B2_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 684:41] + node _T_977 = cat(_T_974, _T_976) @[Cat.scala 30:58] + node _T_978 = cat(_T_955, _T_965) @[Cat.scala 30:58] + node _T_979 = cat(_T_978, _T_977) @[Cat.scala 30:58] + io.usingMulAdd <= _T_979 @[DivSqrtRecF64_mulAddZ31.scala 671:20] + node _T_980 = shl(sigX1_B, 47) @[DivSqrtRecF64_mulAddZ31.scala 688:45] + node _T_982 = mux(cyc_B1, _T_980, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 688:12] + node _T_983 = shl(sigX1_B, 46) @[DivSqrtRecF64_mulAddZ31.scala 689:45] + node _T_985 = mux(cyc_C6_sqrt, _T_983, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 689:12] + node _T_986 = or(_T_982, _T_985) @[DivSqrtRecF64_mulAddZ31.scala 688:64] + node _T_987 = or(cyc_C4_sqrt, cyc_C2) @[DivSqrtRecF64_mulAddZ31.scala 690:25] + node _T_988 = shl(sigXN_C, 47) @[DivSqrtRecF64_mulAddZ31.scala 690:45] + node _T_990 = mux(_T_987, _T_988, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 690:12] + node _T_991 = or(_T_986, _T_990) @[DivSqrtRecF64_mulAddZ31.scala 689:64] + node _T_993 = eq(E_E_div, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 691:27] + node _T_994 = and(cyc_E3_div, _T_993) @[DivSqrtRecF64_mulAddZ31.scala 691:24] + node _T_995 = shl(fractA_0_PC, 53) @[DivSqrtRecF64_mulAddZ31.scala 691:49] + node _T_997 = mux(_T_994, _T_995, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 691:12] + node _T_998 = or(_T_991, _T_997) @[DivSqrtRecF64_mulAddZ31.scala 690:64] + node _T_999 = bits(exp_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 693:24] + node _T_1000 = bits(sigB_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 694:29] + node _T_1002 = cat(_T_1000, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_1003 = bits(sigB_PC, 1, 1) @[DivSqrtRecF64_mulAddZ31.scala 695:29] + node _T_1004 = bits(sigB_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 695:42] + node _T_1005 = xor(_T_1003, _T_1004) @[DivSqrtRecF64_mulAddZ31.scala 695:33] + node _T_1006 = bits(sigB_PC, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 695:54] + node _T_1007 = cat(_T_1005, _T_1006) @[Cat.scala 30:58] + node _T_1008 = mux(_T_999, _T_1002, _T_1007) @[DivSqrtRecF64_mulAddZ31.scala 693:17] + node _T_1010 = eq(extraT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 696:22] + node _T_1012 = cat(_T_1010, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_1013 = xor(_T_1008, _T_1012) @[DivSqrtRecF64_mulAddZ31.scala 696:16] + node _T_1014 = shl(_T_1013, 54) @[DivSqrtRecF64_mulAddZ31.scala 697:14] + node _T_1016 = mux(cyc_E3_sqrt, _T_1014, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 692:12] + node _T_1017 = or(_T_998, _T_1016) @[DivSqrtRecF64_mulAddZ31.scala 691:64] + io.mulAddC_2 <= _T_1017 @[DivSqrtRecF64_mulAddZ31.scala 687:18] + node ESqrR1_B8_sqrt = bits(io.mulAddResult_3, 103, 72) @[DivSqrtRecF64_mulAddZ31.scala 701:43] + node _T_1018 = bits(io.mulAddResult_3, 90, 45) @[DivSqrtRecF64_mulAddZ31.scala 702:49] + node _T_1019 = not(_T_1018) @[DivSqrtRecF64_mulAddZ31.scala 702:31] + node _T_1021 = mux(cyc_B4, _T_1019, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 702:22] + zSigma1_B4 <= _T_1021 @[DivSqrtRecF64_mulAddZ31.scala 702:16] + node sqrSigma1_B1 = bits(io.mulAddResult_3, 79, 47) @[DivSqrtRecF64_mulAddZ31.scala 703:41] + node _T_1022 = bits(io.mulAddResult_3, 104, 47) @[DivSqrtRecF64_mulAddZ31.scala 704:38] + sigXNU_B3_CX <= _T_1022 @[DivSqrtRecF64_mulAddZ31.scala 704:18] + node _T_1023 = bits(io.mulAddResult_3, 104, 104) @[DivSqrtRecF64_mulAddZ31.scala 705:39] + node E_C1_div = eq(_T_1023, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 705:20] + node _T_1026 = eq(E_C1_div, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 707:28] + node _T_1027 = and(cyc_C1_div, _T_1026) @[DivSqrtRecF64_mulAddZ31.scala 707:25] + node _T_1028 = or(_T_1027, cyc_C1_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 707:40] + node _T_1029 = bits(io.mulAddResult_3, 104, 51) @[DivSqrtRecF64_mulAddZ31.scala 708:31] + node _T_1030 = not(_T_1029) @[DivSqrtRecF64_mulAddZ31.scala 708:13] + node _T_1032 = mux(_T_1028, _T_1030, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 707:12] + node _T_1033 = and(cyc_C1_div, E_C1_div) @[DivSqrtRecF64_mulAddZ31.scala 711:24] + node _T_1035 = bits(io.mulAddResult_3, 102, 50) @[DivSqrtRecF64_mulAddZ31.scala 712:47] + node _T_1036 = not(_T_1035) @[DivSqrtRecF64_mulAddZ31.scala 712:29] + node _T_1037 = cat(UInt<1>("h00"), _T_1036) @[Cat.scala 30:58] + node _T_1039 = mux(_T_1033, _T_1037, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 711:12] + node _T_1040 = or(_T_1032, _T_1039) @[DivSqrtRecF64_mulAddZ31.scala 710:11] + zComplSigT_C1 <= _T_1040 @[DivSqrtRecF64_mulAddZ31.scala 706:19] + node _T_1041 = bits(io.mulAddResult_3, 104, 51) @[DivSqrtRecF64_mulAddZ31.scala 716:44] + node _T_1042 = not(_T_1041) @[DivSqrtRecF64_mulAddZ31.scala 716:26] + node _T_1044 = mux(cyc_C1_sqrt, _T_1042, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 716:12] + zComplSigT_C1_sqrt <= _T_1044 @[DivSqrtRecF64_mulAddZ31.scala 715:24] + node sigT_C1 = not(zComplSigT_C1) @[DivSqrtRecF64_mulAddZ31.scala 720:19] + node remT_E2 = bits(io.mulAddResult_3, 55, 0) @[DivSqrtRecF64_mulAddZ31.scala 721:36] + when cyc_B8_sqrt : @[DivSqrtRecF64_mulAddZ31.scala 723:24] + ESqrR1_B_sqrt <= ESqrR1_B8_sqrt @[DivSqrtRecF64_mulAddZ31.scala 724:23] + skip @[DivSqrtRecF64_mulAddZ31.scala 723:24] + when cyc_B3 : @[DivSqrtRecF64_mulAddZ31.scala 726:19] + sigX1_B <= sigXNU_B3_CX @[DivSqrtRecF64_mulAddZ31.scala 727:17] + skip @[DivSqrtRecF64_mulAddZ31.scala 726:19] + when cyc_B1 : @[DivSqrtRecF64_mulAddZ31.scala 729:19] + sqrSigma1_C <= sqrSigma1_B1 @[DivSqrtRecF64_mulAddZ31.scala 730:21] + skip @[DivSqrtRecF64_mulAddZ31.scala 729:19] + node _T_1045 = or(cyc_C6_sqrt, cyc_C5_div) @[DivSqrtRecF64_mulAddZ31.scala 733:23] + node _T_1046 = or(_T_1045, cyc_C3_sqrt) @[DivSqrtRecF64_mulAddZ31.scala 733:37] + when _T_1046 : @[DivSqrtRecF64_mulAddZ31.scala 733:53] + sigXN_C <= sigXNU_B3_CX @[DivSqrtRecF64_mulAddZ31.scala 734:17] + skip @[DivSqrtRecF64_mulAddZ31.scala 733:53] + when cyc_C5_sqrt : @[DivSqrtRecF64_mulAddZ31.scala 736:24] + node _T_1047 = bits(sigXNU_B3_CX, 56, 26) @[DivSqrtRecF64_mulAddZ31.scala 737:33] + u_C_sqrt <= _T_1047 @[DivSqrtRecF64_mulAddZ31.scala 737:18] + skip @[DivSqrtRecF64_mulAddZ31.scala 736:24] + when cyc_C1 : @[DivSqrtRecF64_mulAddZ31.scala 739:19] + E_E_div <= E_C1_div @[DivSqrtRecF64_mulAddZ31.scala 740:18] + node _T_1048 = bits(sigT_C1, 53, 1) @[DivSqrtRecF64_mulAddZ31.scala 741:28] + sigT_E <= _T_1048 @[DivSqrtRecF64_mulAddZ31.scala 741:18] + node _T_1049 = bits(sigT_C1, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 742:28] + extraT_E <= _T_1049 @[DivSqrtRecF64_mulAddZ31.scala 742:18] + skip @[DivSqrtRecF64_mulAddZ31.scala 739:19] + when cyc_E2 : @[DivSqrtRecF64_mulAddZ31.scala 745:19] + node _T_1050 = bits(remT_E2, 55, 55) @[DivSqrtRecF64_mulAddZ31.scala 746:47] + node _T_1051 = bits(remT_E2, 53, 53) @[DivSqrtRecF64_mulAddZ31.scala 746:61] + node _T_1052 = mux(sqrtOp_PC, _T_1050, _T_1051) @[DivSqrtRecF64_mulAddZ31.scala 746:27] + isNegRemT_E <= _T_1052 @[DivSqrtRecF64_mulAddZ31.scala 746:21] + node _T_1053 = bits(remT_E2, 53, 0) @[DivSqrtRecF64_mulAddZ31.scala 748:21] + node _T_1055 = eq(_T_1053, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 748:29] + node _T_1057 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 749:18] + node _T_1058 = bits(remT_E2, 55, 54) @[DivSqrtRecF64_mulAddZ31.scala 749:41] + node _T_1060 = eq(_T_1058, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 749:50] + node _T_1061 = or(_T_1057, _T_1060) @[DivSqrtRecF64_mulAddZ31.scala 749:30] + node _T_1062 = and(_T_1055, _T_1061) @[DivSqrtRecF64_mulAddZ31.scala 748:42] + isZeroRemT_E <= _T_1062 @[DivSqrtRecF64_mulAddZ31.scala 747:22] + skip @[DivSqrtRecF64_mulAddZ31.scala 745:19] + node _T_1064 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 755:13] + node _T_1065 = and(_T_1064, E_E_div) @[DivSqrtRecF64_mulAddZ31.scala 755:25] + node _T_1067 = mux(_T_1065, exp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 755:12] + node _T_1069 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 756:13] + node _T_1071 = eq(E_E_div, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 756:28] + node _T_1072 = and(_T_1069, _T_1071) @[DivSqrtRecF64_mulAddZ31.scala 756:25] + node _T_1074 = mux(_T_1072, expP1_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 756:12] + node _T_1075 = or(_T_1067, _T_1074) @[DivSqrtRecF64_mulAddZ31.scala 755:76] + node _T_1076 = shr(exp_PC, 1) @[DivSqrtRecF64_mulAddZ31.scala 757:42] + node _T_1078 = add(_T_1076, UInt<12>("h0400")) @[DivSqrtRecF64_mulAddZ31.scala 757:47] + node _T_1079 = tail(_T_1078, 1) @[DivSqrtRecF64_mulAddZ31.scala 757:47] + node _T_1081 = mux(sqrtOp_PC, _T_1079, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 757:12] + node sExpX_E = or(_T_1075, _T_1081) @[DivSqrtRecF64_mulAddZ31.scala 756:76] + node posExpX_E = bits(sExpX_E, 12, 0) @[DivSqrtRecF64_mulAddZ31.scala 759:28] + node _T_1082 = not(posExpX_E) @[primitives.scala 50:21] + node _T_1083 = bits(_T_1082, 12, 12) @[primitives.scala 56:25] + node _T_1084 = bits(_T_1082, 11, 0) @[primitives.scala 57:26] + node _T_1085 = bits(_T_1084, 11, 11) @[primitives.scala 56:25] + node _T_1086 = bits(_T_1084, 10, 0) @[primitives.scala 57:26] + node _T_1087 = bits(_T_1086, 10, 10) @[primitives.scala 56:25] + node _T_1088 = bits(_T_1086, 9, 0) @[primitives.scala 57:26] + node _T_1089 = bits(_T_1088, 9, 9) @[primitives.scala 56:25] + node _T_1090 = bits(_T_1088, 8, 0) @[primitives.scala 57:26] + node _T_1092 = bits(_T_1090, 8, 8) @[primitives.scala 56:25] + node _T_1093 = bits(_T_1090, 7, 0) @[primitives.scala 57:26] + node _T_1095 = bits(_T_1093, 7, 7) @[primitives.scala 56:25] + node _T_1096 = bits(_T_1093, 6, 0) @[primitives.scala 57:26] + node _T_1098 = bits(_T_1096, 6, 6) @[primitives.scala 56:25] + node _T_1099 = bits(_T_1096, 5, 0) @[primitives.scala 57:26] + node _T_1102 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_1099) @[primitives.scala 68:52] + node _T_1103 = bits(_T_1102, 63, 14) @[primitives.scala 69:26] + node _T_1104 = bits(_T_1103, 31, 0) @[Bitwise.scala 108:18] + node _T_1107 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 101:47] + node _T_1108 = xor(UInt<32>("h0ffffffff"), _T_1107) @[Bitwise.scala 101:21] + node _T_1109 = shr(_T_1104, 16) @[Bitwise.scala 102:21] + node _T_1110 = and(_T_1109, _T_1108) @[Bitwise.scala 102:31] + node _T_1111 = bits(_T_1104, 15, 0) @[Bitwise.scala 102:46] + node _T_1112 = shl(_T_1111, 16) @[Bitwise.scala 102:65] + node _T_1113 = not(_T_1108) @[Bitwise.scala 102:77] + node _T_1114 = and(_T_1112, _T_1113) @[Bitwise.scala 102:75] + node _T_1115 = or(_T_1110, _T_1114) @[Bitwise.scala 102:39] + node _T_1116 = bits(_T_1108, 23, 0) @[Bitwise.scala 101:28] + node _T_1117 = shl(_T_1116, 8) @[Bitwise.scala 101:47] + node _T_1118 = xor(_T_1108, _T_1117) @[Bitwise.scala 101:21] + node _T_1119 = shr(_T_1115, 8) @[Bitwise.scala 102:21] + node _T_1120 = and(_T_1119, _T_1118) @[Bitwise.scala 102:31] + node _T_1121 = bits(_T_1115, 23, 0) @[Bitwise.scala 102:46] + node _T_1122 = shl(_T_1121, 8) @[Bitwise.scala 102:65] + node _T_1123 = not(_T_1118) @[Bitwise.scala 102:77] + node _T_1124 = and(_T_1122, _T_1123) @[Bitwise.scala 102:75] + node _T_1125 = or(_T_1120, _T_1124) @[Bitwise.scala 102:39] + node _T_1126 = bits(_T_1118, 27, 0) @[Bitwise.scala 101:28] + node _T_1127 = shl(_T_1126, 4) @[Bitwise.scala 101:47] + node _T_1128 = xor(_T_1118, _T_1127) @[Bitwise.scala 101:21] + node _T_1129 = shr(_T_1125, 4) @[Bitwise.scala 102:21] + node _T_1130 = and(_T_1129, _T_1128) @[Bitwise.scala 102:31] + node _T_1131 = bits(_T_1125, 27, 0) @[Bitwise.scala 102:46] + node _T_1132 = shl(_T_1131, 4) @[Bitwise.scala 102:65] + node _T_1133 = not(_T_1128) @[Bitwise.scala 102:77] + node _T_1134 = and(_T_1132, _T_1133) @[Bitwise.scala 102:75] + node _T_1135 = or(_T_1130, _T_1134) @[Bitwise.scala 102:39] + node _T_1136 = bits(_T_1128, 29, 0) @[Bitwise.scala 101:28] + node _T_1137 = shl(_T_1136, 2) @[Bitwise.scala 101:47] + node _T_1138 = xor(_T_1128, _T_1137) @[Bitwise.scala 101:21] + node _T_1139 = shr(_T_1135, 2) @[Bitwise.scala 102:21] + node _T_1140 = and(_T_1139, _T_1138) @[Bitwise.scala 102:31] + node _T_1141 = bits(_T_1135, 29, 0) @[Bitwise.scala 102:46] + node _T_1142 = shl(_T_1141, 2) @[Bitwise.scala 102:65] + node _T_1143 = not(_T_1138) @[Bitwise.scala 102:77] + node _T_1144 = and(_T_1142, _T_1143) @[Bitwise.scala 102:75] + node _T_1145 = or(_T_1140, _T_1144) @[Bitwise.scala 102:39] + node _T_1146 = bits(_T_1138, 30, 0) @[Bitwise.scala 101:28] + node _T_1147 = shl(_T_1146, 1) @[Bitwise.scala 101:47] + node _T_1148 = xor(_T_1138, _T_1147) @[Bitwise.scala 101:21] + node _T_1149 = shr(_T_1145, 1) @[Bitwise.scala 102:21] + node _T_1150 = and(_T_1149, _T_1148) @[Bitwise.scala 102:31] + node _T_1151 = bits(_T_1145, 30, 0) @[Bitwise.scala 102:46] + node _T_1152 = shl(_T_1151, 1) @[Bitwise.scala 102:65] + node _T_1153 = not(_T_1148) @[Bitwise.scala 102:77] + node _T_1154 = and(_T_1152, _T_1153) @[Bitwise.scala 102:75] + node _T_1155 = or(_T_1150, _T_1154) @[Bitwise.scala 102:39] + node _T_1156 = bits(_T_1103, 49, 32) @[Bitwise.scala 108:44] + node _T_1157 = bits(_T_1156, 15, 0) @[Bitwise.scala 108:18] + node _T_1160 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 101:47] + node _T_1161 = xor(UInt<16>("h0ffff"), _T_1160) @[Bitwise.scala 101:21] + node _T_1162 = shr(_T_1157, 8) @[Bitwise.scala 102:21] + node _T_1163 = and(_T_1162, _T_1161) @[Bitwise.scala 102:31] + node _T_1164 = bits(_T_1157, 7, 0) @[Bitwise.scala 102:46] + node _T_1165 = shl(_T_1164, 8) @[Bitwise.scala 102:65] + node _T_1166 = not(_T_1161) @[Bitwise.scala 102:77] + node _T_1167 = and(_T_1165, _T_1166) @[Bitwise.scala 102:75] + node _T_1168 = or(_T_1163, _T_1167) @[Bitwise.scala 102:39] + node _T_1169 = bits(_T_1161, 11, 0) @[Bitwise.scala 101:28] + node _T_1170 = shl(_T_1169, 4) @[Bitwise.scala 101:47] + node _T_1171 = xor(_T_1161, _T_1170) @[Bitwise.scala 101:21] + node _T_1172 = shr(_T_1168, 4) @[Bitwise.scala 102:21] + node _T_1173 = and(_T_1172, _T_1171) @[Bitwise.scala 102:31] + node _T_1174 = bits(_T_1168, 11, 0) @[Bitwise.scala 102:46] + node _T_1175 = shl(_T_1174, 4) @[Bitwise.scala 102:65] + node _T_1176 = not(_T_1171) @[Bitwise.scala 102:77] + node _T_1177 = and(_T_1175, _T_1176) @[Bitwise.scala 102:75] + node _T_1178 = or(_T_1173, _T_1177) @[Bitwise.scala 102:39] + node _T_1179 = bits(_T_1171, 13, 0) @[Bitwise.scala 101:28] + node _T_1180 = shl(_T_1179, 2) @[Bitwise.scala 101:47] + node _T_1181 = xor(_T_1171, _T_1180) @[Bitwise.scala 101:21] + node _T_1182 = shr(_T_1178, 2) @[Bitwise.scala 102:21] + node _T_1183 = and(_T_1182, _T_1181) @[Bitwise.scala 102:31] + node _T_1184 = bits(_T_1178, 13, 0) @[Bitwise.scala 102:46] + node _T_1185 = shl(_T_1184, 2) @[Bitwise.scala 102:65] + node _T_1186 = not(_T_1181) @[Bitwise.scala 102:77] + node _T_1187 = and(_T_1185, _T_1186) @[Bitwise.scala 102:75] + node _T_1188 = or(_T_1183, _T_1187) @[Bitwise.scala 102:39] + node _T_1189 = bits(_T_1181, 14, 0) @[Bitwise.scala 101:28] + node _T_1190 = shl(_T_1189, 1) @[Bitwise.scala 101:47] + node _T_1191 = xor(_T_1181, _T_1190) @[Bitwise.scala 101:21] + node _T_1192 = shr(_T_1188, 1) @[Bitwise.scala 102:21] + node _T_1193 = and(_T_1192, _T_1191) @[Bitwise.scala 102:31] + node _T_1194 = bits(_T_1188, 14, 0) @[Bitwise.scala 102:46] + node _T_1195 = shl(_T_1194, 1) @[Bitwise.scala 102:65] + node _T_1196 = not(_T_1191) @[Bitwise.scala 102:77] + node _T_1197 = and(_T_1195, _T_1196) @[Bitwise.scala 102:75] + node _T_1198 = or(_T_1193, _T_1197) @[Bitwise.scala 102:39] + node _T_1199 = bits(_T_1156, 17, 16) @[Bitwise.scala 108:44] + node _T_1200 = bits(_T_1199, 0, 0) @[Bitwise.scala 108:18] + node _T_1201 = bits(_T_1199, 1, 1) @[Bitwise.scala 108:44] + node _T_1202 = cat(_T_1200, _T_1201) @[Cat.scala 30:58] + node _T_1203 = cat(_T_1198, _T_1202) @[Cat.scala 30:58] + node _T_1204 = cat(_T_1155, _T_1203) @[Cat.scala 30:58] + node _T_1205 = not(_T_1204) @[primitives.scala 65:36] + node _T_1206 = mux(_T_1098, UInt<1>("h00"), _T_1205) @[primitives.scala 65:21] + node _T_1207 = not(_T_1206) @[primitives.scala 65:17] + node _T_1208 = not(_T_1207) @[primitives.scala 65:36] + node _T_1209 = mux(_T_1095, UInt<1>("h00"), _T_1208) @[primitives.scala 65:21] + node _T_1210 = not(_T_1209) @[primitives.scala 65:17] + node _T_1211 = not(_T_1210) @[primitives.scala 65:36] + node _T_1212 = mux(_T_1092, UInt<1>("h00"), _T_1211) @[primitives.scala 65:21] + node _T_1213 = not(_T_1212) @[primitives.scala 65:17] + node _T_1214 = not(_T_1213) @[primitives.scala 65:36] + node _T_1215 = mux(_T_1089, UInt<1>("h00"), _T_1214) @[primitives.scala 65:21] + node _T_1216 = not(_T_1215) @[primitives.scala 65:17] + node _T_1218 = cat(_T_1216, UInt<3>("h07")) @[Cat.scala 30:58] + node _T_1219 = bits(_T_1088, 9, 9) @[primitives.scala 56:25] + node _T_1220 = bits(_T_1088, 8, 0) @[primitives.scala 57:26] + node _T_1221 = bits(_T_1220, 8, 8) @[primitives.scala 56:25] + node _T_1222 = bits(_T_1220, 7, 0) @[primitives.scala 57:26] + node _T_1223 = bits(_T_1222, 7, 7) @[primitives.scala 56:25] + node _T_1224 = bits(_T_1222, 6, 0) @[primitives.scala 57:26] + node _T_1225 = bits(_T_1224, 6, 6) @[primitives.scala 56:25] + node _T_1226 = bits(_T_1224, 5, 0) @[primitives.scala 57:26] + node _T_1228 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_1226) @[primitives.scala 68:52] + node _T_1229 = bits(_T_1228, 2, 0) @[primitives.scala 69:26] + node _T_1230 = bits(_T_1229, 1, 0) @[Bitwise.scala 108:18] + node _T_1231 = bits(_T_1230, 0, 0) @[Bitwise.scala 108:18] + node _T_1232 = bits(_T_1230, 1, 1) @[Bitwise.scala 108:44] + node _T_1233 = cat(_T_1231, _T_1232) @[Cat.scala 30:58] + node _T_1234 = bits(_T_1229, 2, 2) @[Bitwise.scala 108:44] + node _T_1235 = cat(_T_1233, _T_1234) @[Cat.scala 30:58] + node _T_1237 = mux(_T_1225, _T_1235, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_1239 = mux(_T_1223, _T_1237, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_1241 = mux(_T_1221, _T_1239, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_1243 = mux(_T_1219, _T_1241, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_1244 = mux(_T_1087, _T_1218, _T_1243) @[primitives.scala 61:20] + node _T_1246 = mux(_T_1085, _T_1244, UInt<1>("h00")) @[primitives.scala 59:20] + node roundMask_E = mux(_T_1083, _T_1246, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_1249 = cat(UInt<1>("h00"), roundMask_E) @[Cat.scala 30:58] + node _T_1250 = not(_T_1249) @[DivSqrtRecF64_mulAddZ31.scala 763:9] + node _T_1252 = cat(roundMask_E, UInt<1>("h01")) @[Cat.scala 30:58] + node incrPosMask_E = and(_T_1250, _T_1252) @[DivSqrtRecF64_mulAddZ31.scala 763:39] + node _T_1253 = shr(incrPosMask_E, 1) @[DivSqrtRecF64_mulAddZ31.scala 765:51] + node _T_1254 = and(sigT_E, _T_1253) @[DivSqrtRecF64_mulAddZ31.scala 765:36] + node hiRoundPosBitT_E = neq(_T_1254, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 765:56] + node _T_1256 = shr(roundMask_E, 1) @[DivSqrtRecF64_mulAddZ31.scala 766:55] + node _T_1257 = and(sigT_E, _T_1256) @[DivSqrtRecF64_mulAddZ31.scala 766:42] + node all0sHiRoundExtraT_E = eq(_T_1257, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 766:60] + node _T_1259 = not(sigT_E) @[DivSqrtRecF64_mulAddZ31.scala 767:34] + node _T_1260 = shr(roundMask_E, 1) @[DivSqrtRecF64_mulAddZ31.scala 767:55] + node _T_1261 = and(_T_1259, _T_1260) @[DivSqrtRecF64_mulAddZ31.scala 767:42] + node all1sHiRoundExtraT_E = eq(_T_1261, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 767:60] + node _T_1263 = bits(roundMask_E, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 769:23] + node _T_1265 = eq(_T_1263, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 769:10] + node _T_1266 = or(_T_1265, hiRoundPosBitT_E) @[DivSqrtRecF64_mulAddZ31.scala 769:27] + node all1sHiRoundT_E = and(_T_1266, all1sHiRoundExtraT_E) @[DivSqrtRecF64_mulAddZ31.scala 769:48] + node _T_1268 = add(UInt<54>("h00"), sigT_E) @[DivSqrtRecF64_mulAddZ31.scala 773:33] + node _T_1269 = tail(_T_1268, 1) @[DivSqrtRecF64_mulAddZ31.scala 773:33] + node _T_1270 = add(_T_1269, roundMagUp_PC) @[DivSqrtRecF64_mulAddZ31.scala 773:42] + node sigAdjT_E = tail(_T_1270, 1) @[DivSqrtRecF64_mulAddZ31.scala 773:42] + node _T_1272 = not(roundMask_E) @[DivSqrtRecF64_mulAddZ31.scala 774:47] + node _T_1273 = cat(UInt<1>("h01"), _T_1272) @[Cat.scala 30:58] + node sigY0_E = and(sigAdjT_E, _T_1273) @[DivSqrtRecF64_mulAddZ31.scala 774:29] + node _T_1275 = cat(UInt<1>("h00"), roundMask_E) @[Cat.scala 30:58] + node _T_1276 = or(sigAdjT_E, _T_1275) @[DivSqrtRecF64_mulAddZ31.scala 775:30] + node _T_1278 = add(_T_1276, UInt<1>("h01")) @[DivSqrtRecF64_mulAddZ31.scala 775:62] + node sigY1_E = tail(_T_1278, 1) @[DivSqrtRecF64_mulAddZ31.scala 775:62] + node _T_1280 = eq(isNegRemT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 783:24] + node _T_1282 = eq(isZeroRemT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 783:41] + node _T_1283 = and(_T_1280, _T_1282) @[DivSqrtRecF64_mulAddZ31.scala 783:38] + node trueLtX_E1 = mux(sqrtOp_PC, _T_1283, isNegRemT_E) @[DivSqrtRecF64_mulAddZ31.scala 783:12] + node _T_1284 = bits(roundMask_E, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 793:25] + node _T_1286 = eq(trueLtX_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 793:32] + node _T_1287 = and(_T_1284, _T_1286) @[DivSqrtRecF64_mulAddZ31.scala 793:29] + node _T_1288 = and(_T_1287, all1sHiRoundExtraT_E) @[DivSqrtRecF64_mulAddZ31.scala 793:45] + node _T_1289 = and(_T_1288, extraT_E) @[DivSqrtRecF64_mulAddZ31.scala 793:69] + node hiRoundPosBit_E1 = xor(hiRoundPosBitT_E, _T_1289) @[DivSqrtRecF64_mulAddZ31.scala 792:26] + node _T_1291 = eq(isZeroRemT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 795:28] + node _T_1293 = eq(extraT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 795:44] + node _T_1294 = or(_T_1291, _T_1293) @[DivSqrtRecF64_mulAddZ31.scala 795:41] + node _T_1296 = eq(all1sHiRoundExtraT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 795:58] + node anyRoundExtra_E1 = or(_T_1294, _T_1296) @[DivSqrtRecF64_mulAddZ31.scala 795:55] + node _T_1297 = and(roundingMode_near_even_PC, hiRoundPosBit_E1) @[DivSqrtRecF64_mulAddZ31.scala 797:39] + node _T_1299 = eq(anyRoundExtra_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 798:17] + node _T_1300 = and(_T_1297, _T_1299) @[DivSqrtRecF64_mulAddZ31.scala 797:59] + node roundEvenMask_E1 = mux(_T_1300, incrPosMask_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 797:12] + node _T_1302 = and(roundMagDown_PC, extraT_E) @[DivSqrtRecF64_mulAddZ31.scala 804:30] + node _T_1304 = eq(trueLtX_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 804:45] + node _T_1305 = and(_T_1302, _T_1304) @[DivSqrtRecF64_mulAddZ31.scala 804:42] + node _T_1306 = and(_T_1305, all1sHiRoundT_E) @[DivSqrtRecF64_mulAddZ31.scala 804:58] + node _T_1308 = eq(trueLtX_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 806:32] + node _T_1309 = and(extraT_E, _T_1308) @[DivSqrtRecF64_mulAddZ31.scala 806:29] + node _T_1311 = eq(isZeroRemT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 806:48] + node _T_1312 = and(_T_1309, _T_1311) @[DivSqrtRecF64_mulAddZ31.scala 806:45] + node _T_1314 = eq(all1sHiRoundT_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 807:23] + node _T_1315 = or(_T_1312, _T_1314) @[DivSqrtRecF64_mulAddZ31.scala 806:62] + node _T_1316 = and(roundMagUp_PC, _T_1315) @[DivSqrtRecF64_mulAddZ31.scala 805:28] + node _T_1317 = or(_T_1306, _T_1316) @[DivSqrtRecF64_mulAddZ31.scala 804:78] + node _T_1319 = eq(trueLtX_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 810:37] + node _T_1320 = or(extraT_E, _T_1319) @[DivSqrtRecF64_mulAddZ31.scala 810:34] + node _T_1321 = bits(roundMask_E, 0, 0) @[DivSqrtRecF64_mulAddZ31.scala 810:67] + node _T_1323 = eq(_T_1321, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 810:54] + node _T_1324 = and(_T_1320, _T_1323) @[DivSqrtRecF64_mulAddZ31.scala 810:51] + node _T_1325 = or(hiRoundPosBitT_E, _T_1324) @[DivSqrtRecF64_mulAddZ31.scala 809:36] + node _T_1327 = eq(trueLtX_E1, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 811:36] + node _T_1328 = and(extraT_E, _T_1327) @[DivSqrtRecF64_mulAddZ31.scala 811:33] + node _T_1329 = and(_T_1328, all1sHiRoundExtraT_E) @[DivSqrtRecF64_mulAddZ31.scala 811:49] + node _T_1330 = or(_T_1325, _T_1329) @[DivSqrtRecF64_mulAddZ31.scala 810:72] + node _T_1331 = and(roundingMode_near_even_PC, _T_1330) @[DivSqrtRecF64_mulAddZ31.scala 808:40] + node _T_1332 = or(_T_1317, _T_1331) @[DivSqrtRecF64_mulAddZ31.scala 807:43] + node _T_1333 = mux(_T_1332, sigY1_E, sigY0_E) @[DivSqrtRecF64_mulAddZ31.scala 804:12] + node _T_1334 = not(roundEvenMask_E1) @[DivSqrtRecF64_mulAddZ31.scala 814:13] + node sigY_E1 = and(_T_1333, _T_1334) @[DivSqrtRecF64_mulAddZ31.scala 814:11] + node fractY_E1 = bits(sigY_E1, 51, 0) @[DivSqrtRecF64_mulAddZ31.scala 815:28] + node inexactY_E1 = or(hiRoundPosBit_E1, anyRoundExtra_E1) @[DivSqrtRecF64_mulAddZ31.scala 816:40] + node _T_1335 = bits(sigY_E1, 53, 53) @[DivSqrtRecF64_mulAddZ31.scala 818:22] + node _T_1337 = eq(_T_1335, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 818:13] + node _T_1339 = mux(_T_1337, sExpX_E, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 818:12] + node _T_1340 = bits(sigY_E1, 53, 53) @[DivSqrtRecF64_mulAddZ31.scala 819:20] + node _T_1342 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 819:28] + node _T_1343 = and(_T_1340, _T_1342) @[DivSqrtRecF64_mulAddZ31.scala 819:25] + node _T_1344 = and(_T_1343, E_E_div) @[DivSqrtRecF64_mulAddZ31.scala 819:40] + node _T_1346 = mux(_T_1344, expP1_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 819:12] + node _T_1347 = or(_T_1339, _T_1346) @[DivSqrtRecF64_mulAddZ31.scala 818:73] + node _T_1348 = bits(sigY_E1, 53, 53) @[DivSqrtRecF64_mulAddZ31.scala 820:20] + node _T_1350 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 820:28] + node _T_1351 = and(_T_1348, _T_1350) @[DivSqrtRecF64_mulAddZ31.scala 820:25] + node _T_1353 = eq(E_E_div, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 820:43] + node _T_1354 = and(_T_1351, _T_1353) @[DivSqrtRecF64_mulAddZ31.scala 820:40] + node _T_1356 = mux(_T_1354, expP2_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 820:12] + node _T_1357 = or(_T_1347, _T_1356) @[DivSqrtRecF64_mulAddZ31.scala 819:73] + node _T_1358 = bits(sigY_E1, 53, 53) @[DivSqrtRecF64_mulAddZ31.scala 821:20] + node _T_1359 = and(_T_1358, sqrtOp_PC) @[DivSqrtRecF64_mulAddZ31.scala 821:25] + node _T_1360 = shr(expP2_PC, 1) @[DivSqrtRecF64_mulAddZ31.scala 822:22] + node _T_1362 = add(_T_1360, UInt<12>("h0400")) @[DivSqrtRecF64_mulAddZ31.scala 822:27] + node _T_1363 = tail(_T_1362, 1) @[DivSqrtRecF64_mulAddZ31.scala 822:27] + node _T_1365 = mux(_T_1359, _T_1363, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 821:12] + node sExpY_E1 = or(_T_1357, _T_1365) @[DivSqrtRecF64_mulAddZ31.scala 820:73] + node expY_E1 = bits(sExpY_E1, 11, 0) @[DivSqrtRecF64_mulAddZ31.scala 825:27] + node _T_1366 = bits(sExpY_E1, 13, 13) @[DivSqrtRecF64_mulAddZ31.scala 827:34] + node _T_1368 = eq(_T_1366, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 827:24] + node _T_1370 = bits(sExpY_E1, 12, 10) @[DivSqrtRecF64_mulAddZ31.scala 827:70] + node _T_1371 = leq(UInt<3>("h03"), _T_1370) @[DivSqrtRecF64_mulAddZ31.scala 827:59] + node overflowY_E1 = and(_T_1368, _T_1371) @[DivSqrtRecF64_mulAddZ31.scala 827:39] + node _T_1372 = bits(sExpY_E1, 13, 13) @[DivSqrtRecF64_mulAddZ31.scala 830:17] + node _T_1373 = bits(sExpY_E1, 12, 0) @[DivSqrtRecF64_mulAddZ31.scala 830:34] + node _T_1375 = lt(_T_1373, UInt<13>("h03ce")) @[DivSqrtRecF64_mulAddZ31.scala 830:42] + node totalUnderflowY_E1 = or(_T_1372, _T_1375) @[DivSqrtRecF64_mulAddZ31.scala 830:22] + node _T_1377 = leq(posExpX_E, UInt<13>("h0401")) @[DivSqrtRecF64_mulAddZ31.scala 833:25] + node _T_1378 = and(_T_1377, inexactY_E1) @[DivSqrtRecF64_mulAddZ31.scala 833:56] + node underflowY_E1 = or(totalUnderflowY_E1, _T_1378) @[DivSqrtRecF64_mulAddZ31.scala 832:28] + node _T_1380 = eq(isNaNB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 839:13] + node _T_1382 = eq(isZeroB_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 839:28] + node _T_1383 = and(_T_1380, _T_1382) @[DivSqrtRecF64_mulAddZ31.scala 839:25] + node _T_1384 = and(_T_1383, sign_PC) @[DivSqrtRecF64_mulAddZ31.scala 839:41] + node _T_1385 = and(isZeroA_PC, isZeroB_PC) @[DivSqrtRecF64_mulAddZ31.scala 840:25] + node _T_1386 = and(isInfA_PC, isInfB_PC) @[DivSqrtRecF64_mulAddZ31.scala 840:54] + node _T_1387 = or(_T_1385, _T_1386) @[DivSqrtRecF64_mulAddZ31.scala 840:40] + node notSigNaN_invalid_PC = mux(sqrtOp_PC, _T_1384, _T_1387) @[DivSqrtRecF64_mulAddZ31.scala 838:12] + node _T_1389 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 843:10] + node _T_1390 = and(_T_1389, isSigNaNA_PC) @[DivSqrtRecF64_mulAddZ31.scala 843:22] + node _T_1391 = or(_T_1390, isSigNaNB_PC) @[DivSqrtRecF64_mulAddZ31.scala 843:39] + node invalid_PC = or(_T_1391, notSigNaN_invalid_PC) @[DivSqrtRecF64_mulAddZ31.scala 843:55] + node _T_1393 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 845:9] + node _T_1395 = eq(isSpecialA_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 845:24] + node _T_1396 = and(_T_1393, _T_1395) @[DivSqrtRecF64_mulAddZ31.scala 845:21] + node _T_1398 = eq(isZeroA_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 845:43] + node _T_1399 = and(_T_1396, _T_1398) @[DivSqrtRecF64_mulAddZ31.scala 845:40] + node infinity_PC = and(_T_1399, isZeroB_PC) @[DivSqrtRecF64_mulAddZ31.scala 845:56] + node overflow_E1 = and(normalCase_PC, overflowY_E1) @[DivSqrtRecF64_mulAddZ31.scala 847:37] + node underflow_E1 = and(normalCase_PC, underflowY_E1) @[DivSqrtRecF64_mulAddZ31.scala 848:38] + node _T_1400 = or(overflow_E1, underflow_E1) @[DivSqrtRecF64_mulAddZ31.scala 852:21] + node _T_1401 = and(normalCase_PC, inexactY_E1) @[DivSqrtRecF64_mulAddZ31.scala 852:55] + node inexact_E1 = or(_T_1400, _T_1401) @[DivSqrtRecF64_mulAddZ31.scala 852:37] + node _T_1402 = or(isZeroA_PC, isInfB_PC) @[DivSqrtRecF64_mulAddZ31.scala 857:24] + node _T_1404 = eq(roundMagUp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 857:63] + node _T_1405 = and(totalUnderflowY_E1, _T_1404) @[DivSqrtRecF64_mulAddZ31.scala 857:60] + node _T_1406 = or(_T_1402, _T_1405) @[DivSqrtRecF64_mulAddZ31.scala 857:37] + node notSpecial_isZeroOut_E1 = mux(sqrtOp_PC, isZeroB_PC, _T_1406) @[DivSqrtRecF64_mulAddZ31.scala 855:12] + node _T_1407 = and(normalCase_PC, totalUnderflowY_E1) @[DivSqrtRecF64_mulAddZ31.scala 860:23] + node pegMinFiniteMagOut_E1 = and(_T_1407, roundMagUp_PC) @[DivSqrtRecF64_mulAddZ31.scala 860:45] + node _T_1409 = eq(overflowY_roundMagUp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 861:48] + node pegMaxFiniteMagOut_E1 = and(overflow_E1, _T_1409) @[DivSqrtRecF64_mulAddZ31.scala 861:45] + node _T_1410 = or(isInfA_PC, isZeroB_PC) @[DivSqrtRecF64_mulAddZ31.scala 865:23] + node _T_1411 = and(overflow_E1, overflowY_roundMagUp_PC) @[DivSqrtRecF64_mulAddZ31.scala 865:53] + node _T_1412 = or(_T_1410, _T_1411) @[DivSqrtRecF64_mulAddZ31.scala 865:37] + node notNaN_isInfOut_E1 = mux(sqrtOp_PC, isInfB_PC, _T_1412) @[DivSqrtRecF64_mulAddZ31.scala 863:12] + node _T_1414 = eq(sqrtOp_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 868:10] + node _T_1415 = and(_T_1414, isNaNA_PC) @[DivSqrtRecF64_mulAddZ31.scala 868:22] + node _T_1416 = or(_T_1415, isNaNB_PC) @[DivSqrtRecF64_mulAddZ31.scala 868:36] + node isNaNOut_PC = or(_T_1416, notSigNaN_invalid_PC) @[DivSqrtRecF64_mulAddZ31.scala 868:49] + node _T_1418 = eq(isNaNOut_PC, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 871:9] + node _T_1419 = and(isZeroB_PC, sign_PC) @[DivSqrtRecF64_mulAddZ31.scala 871:52] + node _T_1420 = mux(sqrtOp_PC, _T_1419, sign_PC) @[DivSqrtRecF64_mulAddZ31.scala 871:29] + node signOut_PC = and(_T_1418, _T_1420) @[DivSqrtRecF64_mulAddZ31.scala 871:23] + node _T_1422 = not(UInt<12>("h01ff")) @[DivSqrtRecF64_mulAddZ31.scala 875:19] + node _T_1424 = mux(notSpecial_isZeroOut_E1, _T_1422, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 874:18] + node _T_1425 = not(_T_1424) @[DivSqrtRecF64_mulAddZ31.scala 874:14] + node _T_1426 = and(expY_E1, _T_1425) @[DivSqrtRecF64_mulAddZ31.scala 873:18] + node _T_1428 = not(UInt<12>("h03ce")) @[DivSqrtRecF64_mulAddZ31.scala 879:19] + node _T_1430 = mux(pegMinFiniteMagOut_E1, _T_1428, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 878:18] + node _T_1431 = not(_T_1430) @[DivSqrtRecF64_mulAddZ31.scala 878:14] + node _T_1432 = and(_T_1426, _T_1431) @[DivSqrtRecF64_mulAddZ31.scala 877:16] + node _T_1434 = not(UInt<12>("h0bff")) @[DivSqrtRecF64_mulAddZ31.scala 883:19] + node _T_1436 = mux(pegMaxFiniteMagOut_E1, _T_1434, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 882:18] + node _T_1437 = not(_T_1436) @[DivSqrtRecF64_mulAddZ31.scala 882:14] + node _T_1438 = and(_T_1432, _T_1437) @[DivSqrtRecF64_mulAddZ31.scala 881:16] + node _T_1440 = not(UInt<12>("h0dff")) @[DivSqrtRecF64_mulAddZ31.scala 887:19] + node _T_1442 = mux(notNaN_isInfOut_E1, _T_1440, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 886:18] + node _T_1443 = not(_T_1442) @[DivSqrtRecF64_mulAddZ31.scala 886:14] + node _T_1444 = and(_T_1438, _T_1443) @[DivSqrtRecF64_mulAddZ31.scala 885:16] + node _T_1447 = mux(pegMinFiniteMagOut_E1, UInt<12>("h03ce"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 890:16] + node _T_1448 = or(_T_1444, _T_1447) @[DivSqrtRecF64_mulAddZ31.scala 889:17] + node _T_1451 = mux(pegMaxFiniteMagOut_E1, UInt<12>("h0bff"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 891:16] + node _T_1452 = or(_T_1448, _T_1451) @[DivSqrtRecF64_mulAddZ31.scala 890:76] + node _T_1455 = mux(notNaN_isInfOut_E1, UInt<12>("h0c00"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 892:16] + node _T_1456 = or(_T_1452, _T_1455) @[DivSqrtRecF64_mulAddZ31.scala 891:76] + node _T_1459 = mux(isNaNOut_PC, UInt<12>("h0e00"), UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 893:16] + node expOut_E1 = or(_T_1456, _T_1459) @[DivSqrtRecF64_mulAddZ31.scala 892:76] + node _T_1460 = or(notSpecial_isZeroOut_E1, totalUnderflowY_E1) @[DivSqrtRecF64_mulAddZ31.scala 895:37] + node _T_1461 = or(_T_1460, isNaNOut_PC) @[DivSqrtRecF64_mulAddZ31.scala 895:59] + node _T_1463 = shl(UInt<1>("h01"), 51) @[DivSqrtRecF64_mulAddZ31.scala 896:37] + node _T_1465 = mux(isNaNOut_PC, _T_1463, UInt<1>("h00")) @[DivSqrtRecF64_mulAddZ31.scala 896:16] + node _T_1466 = mux(_T_1461, _T_1465, fractY_E1) @[DivSqrtRecF64_mulAddZ31.scala 895:12] + node _T_1467 = bits(pegMaxFiniteMagOut_E1, 0, 0) @[Bitwise.scala 71:15] + node _T_1470 = mux(_T_1467, UInt<52>("h0fffffffffffff"), UInt<52>("h00")) @[Bitwise.scala 71:12] + node fractOut_E1 = or(_T_1466, _T_1470) @[DivSqrtRecF64_mulAddZ31.scala 898:11] + node _T_1471 = cat(signOut_PC, expOut_E1) @[Cat.scala 30:58] + node _T_1472 = cat(_T_1471, fractOut_E1) @[Cat.scala 30:58] + io.out <= _T_1472 @[DivSqrtRecF64_mulAddZ31.scala 900:12] + node _T_1473 = cat(underflow_E1, inexact_E1) @[Cat.scala 30:58] + node _T_1474 = cat(invalid_PC, infinity_PC) @[Cat.scala 30:58] + node _T_1475 = cat(_T_1474, overflow_E1) @[Cat.scala 30:58] + node _T_1476 = cat(_T_1475, _T_1473) @[Cat.scala 30:58] + io.exceptionFlags <= _T_1476 @[DivSqrtRecF64_mulAddZ31.scala 902:23] + + module Mul54 : + input clock : Clock + input reset : UInt<1> + output io : {flip val_s0 : UInt<1>, flip latch_a_s0 : UInt<1>, flip a_s0 : UInt<54>, flip latch_b_s0 : UInt<1>, flip b_s0 : UInt<54>, flip c_s2 : UInt<105>, result_s3 : UInt<105>} + + io is invalid + io is invalid + reg val_s1 : UInt<1>, clock @[DivSqrtRecF64.scala 96:21] + reg val_s2 : UInt<1>, clock @[DivSqrtRecF64.scala 97:21] + reg reg_a_s1 : UInt<54>, clock @[DivSqrtRecF64.scala 98:23] + reg reg_b_s1 : UInt<54>, clock @[DivSqrtRecF64.scala 99:23] + reg reg_a_s2 : UInt<54>, clock @[DivSqrtRecF64.scala 100:23] + reg reg_b_s2 : UInt<54>, clock @[DivSqrtRecF64.scala 101:23] + reg reg_result_s3 : UInt<105>, clock @[DivSqrtRecF64.scala 102:28] + val_s1 <= io.val_s0 @[DivSqrtRecF64.scala 104:12] + val_s2 <= val_s1 @[DivSqrtRecF64.scala 105:12] + when io.val_s0 : @[DivSqrtRecF64.scala 107:22] + when io.latch_a_s0 : @[DivSqrtRecF64.scala 108:30] + reg_a_s1 <= io.a_s0 @[DivSqrtRecF64.scala 109:22] + skip @[DivSqrtRecF64.scala 108:30] + when io.latch_b_s0 : @[DivSqrtRecF64.scala 111:30] + reg_b_s1 <= io.b_s0 @[DivSqrtRecF64.scala 112:22] + skip @[DivSqrtRecF64.scala 111:30] + skip @[DivSqrtRecF64.scala 107:22] + when val_s1 : @[DivSqrtRecF64.scala 116:19] + reg_a_s2 <= reg_a_s1 @[DivSqrtRecF64.scala 117:18] + reg_b_s2 <= reg_b_s1 @[DivSqrtRecF64.scala 118:18] + skip @[DivSqrtRecF64.scala 116:19] + when val_s2 : @[DivSqrtRecF64.scala 121:19] + node _T_23 = mul(reg_a_s2, reg_b_s2) @[DivSqrtRecF64.scala 122:36] + node _T_24 = bits(_T_23, 104, 0) @[DivSqrtRecF64.scala 122:47] + node _T_25 = add(_T_24, io.c_s2) @[DivSqrtRecF64.scala 122:55] + node _T_26 = tail(_T_25, 1) @[DivSqrtRecF64.scala 122:55] + reg_result_s3 <= _T_26 @[DivSqrtRecF64.scala 122:23] + skip @[DivSqrtRecF64.scala 121:19] + io.result_s3 <= reg_result_s3 @[DivSqrtRecF64.scala 125:18] + + module RoundRawFNToRecFN_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + node roundingMode_nearest_even = eq(io.roundingMode, UInt<2>("h00")) @[RoundRawFNToRecFN.scala 88:54] + node roundingMode_minMag = eq(io.roundingMode, UInt<2>("h01")) @[RoundRawFNToRecFN.scala 89:54] + node roundingMode_min = eq(io.roundingMode, UInt<2>("h02")) @[RoundRawFNToRecFN.scala 90:54] + node roundingMode_max = eq(io.roundingMode, UInt<2>("h03")) @[RoundRawFNToRecFN.scala 91:54] + node _T_26 = and(roundingMode_min, io.in.sign) @[RoundRawFNToRecFN.scala 94:27] + node _T_28 = eq(io.in.sign, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 94:66] + node _T_29 = and(roundingMode_max, _T_28) @[RoundRawFNToRecFN.scala 94:63] + node roundMagUp = or(_T_26, _T_29) @[RoundRawFNToRecFN.scala 94:42] + node doShiftSigDown1 = bits(io.in.sig, 26, 26) @[RoundRawFNToRecFN.scala 98:36] + node isNegExp = lt(io.in.sExp, asSInt(UInt<1>("h00"))) @[RoundRawFNToRecFN.scala 99:32] + node _T_31 = bits(isNegExp, 0, 0) @[Bitwise.scala 71:15] + node _T_34 = mux(_T_31, UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 71:12] + node _T_35 = bits(io.in.sExp, 8, 0) @[RoundRawFNToRecFN.scala 103:31] + node _T_36 = not(_T_35) @[primitives.scala 50:21] + node _T_37 = bits(_T_36, 8, 8) @[primitives.scala 56:25] + node _T_38 = bits(_T_36, 7, 0) @[primitives.scala 57:26] + node _T_39 = bits(_T_38, 7, 7) @[primitives.scala 56:25] + node _T_40 = bits(_T_38, 6, 0) @[primitives.scala 57:26] + node _T_41 = bits(_T_40, 6, 6) @[primitives.scala 56:25] + node _T_42 = bits(_T_40, 5, 0) @[primitives.scala 57:26] + node _T_45 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_42) @[primitives.scala 68:52] + node _T_46 = bits(_T_45, 63, 42) @[primitives.scala 69:26] + node _T_47 = bits(_T_46, 15, 0) @[Bitwise.scala 108:18] + node _T_50 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 101:47] + node _T_51 = xor(UInt<16>("h0ffff"), _T_50) @[Bitwise.scala 101:21] + node _T_52 = shr(_T_47, 8) @[Bitwise.scala 102:21] + node _T_53 = and(_T_52, _T_51) @[Bitwise.scala 102:31] + node _T_54 = bits(_T_47, 7, 0) @[Bitwise.scala 102:46] + node _T_55 = shl(_T_54, 8) @[Bitwise.scala 102:65] + node _T_56 = not(_T_51) @[Bitwise.scala 102:77] + node _T_57 = and(_T_55, _T_56) @[Bitwise.scala 102:75] + node _T_58 = or(_T_53, _T_57) @[Bitwise.scala 102:39] + node _T_59 = bits(_T_51, 11, 0) @[Bitwise.scala 101:28] + node _T_60 = shl(_T_59, 4) @[Bitwise.scala 101:47] + node _T_61 = xor(_T_51, _T_60) @[Bitwise.scala 101:21] + node _T_62 = shr(_T_58, 4) @[Bitwise.scala 102:21] + node _T_63 = and(_T_62, _T_61) @[Bitwise.scala 102:31] + node _T_64 = bits(_T_58, 11, 0) @[Bitwise.scala 102:46] + node _T_65 = shl(_T_64, 4) @[Bitwise.scala 102:65] + node _T_66 = not(_T_61) @[Bitwise.scala 102:77] + node _T_67 = and(_T_65, _T_66) @[Bitwise.scala 102:75] + node _T_68 = or(_T_63, _T_67) @[Bitwise.scala 102:39] + node _T_69 = bits(_T_61, 13, 0) @[Bitwise.scala 101:28] + node _T_70 = shl(_T_69, 2) @[Bitwise.scala 101:47] + node _T_71 = xor(_T_61, _T_70) @[Bitwise.scala 101:21] + node _T_72 = shr(_T_68, 2) @[Bitwise.scala 102:21] + node _T_73 = and(_T_72, _T_71) @[Bitwise.scala 102:31] + node _T_74 = bits(_T_68, 13, 0) @[Bitwise.scala 102:46] + node _T_75 = shl(_T_74, 2) @[Bitwise.scala 102:65] + node _T_76 = not(_T_71) @[Bitwise.scala 102:77] + node _T_77 = and(_T_75, _T_76) @[Bitwise.scala 102:75] + node _T_78 = or(_T_73, _T_77) @[Bitwise.scala 102:39] + node _T_79 = bits(_T_71, 14, 0) @[Bitwise.scala 101:28] + node _T_80 = shl(_T_79, 1) @[Bitwise.scala 101:47] + node _T_81 = xor(_T_71, _T_80) @[Bitwise.scala 101:21] + node _T_82 = shr(_T_78, 1) @[Bitwise.scala 102:21] + node _T_83 = and(_T_82, _T_81) @[Bitwise.scala 102:31] + node _T_84 = bits(_T_78, 14, 0) @[Bitwise.scala 102:46] + node _T_85 = shl(_T_84, 1) @[Bitwise.scala 102:65] + node _T_86 = not(_T_81) @[Bitwise.scala 102:77] + node _T_87 = and(_T_85, _T_86) @[Bitwise.scala 102:75] + node _T_88 = or(_T_83, _T_87) @[Bitwise.scala 102:39] + node _T_89 = bits(_T_46, 21, 16) @[Bitwise.scala 108:44] + node _T_90 = bits(_T_89, 3, 0) @[Bitwise.scala 108:18] + node _T_91 = bits(_T_90, 1, 0) @[Bitwise.scala 108:18] + node _T_92 = bits(_T_91, 0, 0) @[Bitwise.scala 108:18] + node _T_93 = bits(_T_91, 1, 1) @[Bitwise.scala 108:44] + node _T_94 = cat(_T_92, _T_93) @[Cat.scala 30:58] + node _T_95 = bits(_T_90, 3, 2) @[Bitwise.scala 108:44] + node _T_96 = bits(_T_95, 0, 0) @[Bitwise.scala 108:18] + node _T_97 = bits(_T_95, 1, 1) @[Bitwise.scala 108:44] + node _T_98 = cat(_T_96, _T_97) @[Cat.scala 30:58] + node _T_99 = cat(_T_94, _T_98) @[Cat.scala 30:58] + node _T_100 = bits(_T_89, 5, 4) @[Bitwise.scala 108:44] + node _T_101 = bits(_T_100, 0, 0) @[Bitwise.scala 108:18] + node _T_102 = bits(_T_100, 1, 1) @[Bitwise.scala 108:44] + node _T_103 = cat(_T_101, _T_102) @[Cat.scala 30:58] + node _T_104 = cat(_T_99, _T_103) @[Cat.scala 30:58] + node _T_105 = cat(_T_88, _T_104) @[Cat.scala 30:58] + node _T_106 = not(_T_105) @[primitives.scala 65:36] + node _T_107 = mux(_T_41, UInt<1>("h00"), _T_106) @[primitives.scala 65:21] + node _T_108 = not(_T_107) @[primitives.scala 65:17] + node _T_110 = cat(_T_108, UInt<3>("h07")) @[Cat.scala 30:58] + node _T_111 = bits(_T_40, 6, 6) @[primitives.scala 56:25] + node _T_112 = bits(_T_40, 5, 0) @[primitives.scala 57:26] + node _T_114 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_112) @[primitives.scala 68:52] + node _T_115 = bits(_T_114, 2, 0) @[primitives.scala 69:26] + node _T_116 = bits(_T_115, 1, 0) @[Bitwise.scala 108:18] + node _T_117 = bits(_T_116, 0, 0) @[Bitwise.scala 108:18] + node _T_118 = bits(_T_116, 1, 1) @[Bitwise.scala 108:44] + node _T_119 = cat(_T_117, _T_118) @[Cat.scala 30:58] + node _T_120 = bits(_T_115, 2, 2) @[Bitwise.scala 108:44] + node _T_121 = cat(_T_119, _T_120) @[Cat.scala 30:58] + node _T_123 = mux(_T_111, _T_121, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_124 = mux(_T_39, _T_110, _T_123) @[primitives.scala 61:20] + node _T_126 = mux(_T_37, _T_124, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_127 = or(_T_34, _T_126) @[RoundRawFNToRecFN.scala 101:42] + node _T_128 = or(_T_127, doShiftSigDown1) @[RoundRawFNToRecFN.scala 106:19] + node roundMask = cat(_T_128, UInt<2>("h03")) @[Cat.scala 30:58] + node _T_130 = cat(isNegExp, roundMask) @[Cat.scala 30:58] + node shiftedRoundMask = shr(_T_130, 1) @[RoundRawFNToRecFN.scala 109:52] + node _T_131 = not(shiftedRoundMask) @[RoundRawFNToRecFN.scala 110:24] + node roundPosMask = and(_T_131, roundMask) @[RoundRawFNToRecFN.scala 110:42] + node _T_132 = and(io.in.sig, roundPosMask) @[RoundRawFNToRecFN.scala 111:34] + node roundPosBit = neq(_T_132, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 111:50] + node _T_134 = and(io.in.sig, shiftedRoundMask) @[RoundRawFNToRecFN.scala 112:36] + node anyRoundExtra = neq(_T_134, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 112:56] + node anyRound = or(roundPosBit, anyRoundExtra) @[RoundRawFNToRecFN.scala 113:32] + node _T_136 = and(roundingMode_nearest_even, roundPosBit) @[RoundRawFNToRecFN.scala 116:40] + node _T_137 = and(roundMagUp, anyRound) @[RoundRawFNToRecFN.scala 117:29] + node _T_138 = or(_T_136, _T_137) @[RoundRawFNToRecFN.scala 116:56] + node _T_139 = or(io.in.sig, roundMask) @[RoundRawFNToRecFN.scala 118:26] + node _T_140 = shr(_T_139, 2) @[RoundRawFNToRecFN.scala 118:38] + node _T_142 = add(_T_140, UInt<1>("h01")) @[RoundRawFNToRecFN.scala 118:43] + node _T_143 = and(roundingMode_nearest_even, roundPosBit) @[RoundRawFNToRecFN.scala 119:48] + node _T_145 = eq(anyRoundExtra, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 120:26] + node _T_146 = and(_T_143, _T_145) @[RoundRawFNToRecFN.scala 119:63] + node _T_147 = shr(roundMask, 1) @[RoundRawFNToRecFN.scala 121:31] + node _T_149 = mux(_T_146, _T_147, UInt<26>("h00")) @[RoundRawFNToRecFN.scala 119:21] + node _T_150 = not(_T_149) @[RoundRawFNToRecFN.scala 119:17] + node _T_151 = and(_T_142, _T_150) @[RoundRawFNToRecFN.scala 118:55] + node _T_152 = not(roundMask) @[RoundRawFNToRecFN.scala 124:26] + node _T_153 = and(io.in.sig, _T_152) @[RoundRawFNToRecFN.scala 124:24] + node _T_154 = shr(_T_153, 2) @[RoundRawFNToRecFN.scala 124:37] + node roundedSig = mux(_T_138, _T_151, _T_154) @[RoundRawFNToRecFN.scala 116:12] + node _T_155 = shr(roundedSig, 24) @[RoundRawFNToRecFN.scala 127:48] + node _T_156 = cvt(_T_155) @[RoundRawFNToRecFN.scala 127:60] + node sRoundedExp = add(io.in.sExp, _T_156) @[RoundRawFNToRecFN.scala 127:34] + node common_expOut = bits(sRoundedExp, 8, 0) @[RoundRawFNToRecFN.scala 129:36] + node _T_157 = bits(roundedSig, 23, 1) @[RoundRawFNToRecFN.scala 132:23] + node _T_158 = bits(roundedSig, 22, 0) @[RoundRawFNToRecFN.scala 133:23] + node common_fractOut = mux(doShiftSigDown1, _T_157, _T_158) @[RoundRawFNToRecFN.scala 131:12] + node _T_159 = shr(sRoundedExp, 7) @[RoundRawFNToRecFN.scala 136:39] + node common_overflow = geq(_T_159, asSInt(UInt<3>("h03"))) @[RoundRawFNToRecFN.scala 136:56] + node common_totalUnderflow = lt(sRoundedExp, asSInt(UInt<8>("h06b"))) @[RoundRawFNToRecFN.scala 138:46] + node _T_164 = mux(doShiftSigDown1, asSInt(UInt<9>("h081")), asSInt(UInt<9>("h082"))) @[RoundRawFNToRecFN.scala 142:21] + node _T_165 = lt(io.in.sExp, _T_164) @[RoundRawFNToRecFN.scala 141:25] + node common_underflow = and(anyRound, _T_165) @[RoundRawFNToRecFN.scala 140:18] + node isNaNOut = or(io.invalidExc, io.in.isNaN) @[RoundRawFNToRecFN.scala 147:34] + node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) @[RoundRawFNToRecFN.scala 148:49] + node _T_167 = eq(isNaNOut, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 149:22] + node _T_169 = eq(notNaN_isSpecialInfOut, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 149:36] + node _T_170 = and(_T_167, _T_169) @[RoundRawFNToRecFN.scala 149:33] + node _T_172 = eq(io.in.isZero, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 149:64] + node commonCase = and(_T_170, _T_172) @[RoundRawFNToRecFN.scala 149:61] + node overflow = and(commonCase, common_overflow) @[RoundRawFNToRecFN.scala 150:32] + node underflow = and(commonCase, common_underflow) @[RoundRawFNToRecFN.scala 151:32] + node _T_173 = and(commonCase, anyRound) @[RoundRawFNToRecFN.scala 152:43] + node inexact = or(overflow, _T_173) @[RoundRawFNToRecFN.scala 152:28] + node overflow_roundMagUp = or(roundingMode_nearest_even, roundMagUp) @[RoundRawFNToRecFN.scala 154:57] + node _T_174 = and(commonCase, common_totalUnderflow) @[RoundRawFNToRecFN.scala 155:42] + node pegMinNonzeroMagOut = and(_T_174, roundMagUp) @[RoundRawFNToRecFN.scala 155:67] + node _T_175 = and(commonCase, overflow) @[RoundRawFNToRecFN.scala 156:41] + node _T_177 = eq(overflow_roundMagUp, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 156:56] + node pegMaxFiniteMagOut = and(_T_175, _T_177) @[RoundRawFNToRecFN.scala 156:53] + node _T_178 = and(overflow, overflow_roundMagUp) @[RoundRawFNToRecFN.scala 158:45] + node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _T_178) @[RoundRawFNToRecFN.scala 158:32] + node signOut = mux(isNaNOut, UInt<1>("h00"), io.in.sign) @[RoundRawFNToRecFN.scala 160:22] + node _T_180 = or(io.in.isZero, common_totalUnderflow) @[RoundRawFNToRecFN.scala 163:32] + node _T_183 = mux(_T_180, UInt<9>("h01c0"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 163:18] + node _T_184 = not(_T_183) @[RoundRawFNToRecFN.scala 163:14] + node _T_185 = and(common_expOut, _T_184) @[RoundRawFNToRecFN.scala 162:24] + node _T_187 = not(UInt<9>("h06b")) @[RoundRawFNToRecFN.scala 168:19] + node _T_189 = mux(pegMinNonzeroMagOut, _T_187, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 167:18] + node _T_190 = not(_T_189) @[RoundRawFNToRecFN.scala 167:14] + node _T_191 = and(_T_185, _T_190) @[RoundRawFNToRecFN.scala 166:17] + node _T_194 = mux(pegMaxFiniteMagOut, UInt<9>("h080"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 171:18] + node _T_195 = not(_T_194) @[RoundRawFNToRecFN.scala 171:14] + node _T_196 = and(_T_191, _T_195) @[RoundRawFNToRecFN.scala 170:17] + node _T_199 = mux(notNaN_isInfOut, UInt<9>("h040"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 175:18] + node _T_200 = not(_T_199) @[RoundRawFNToRecFN.scala 175:14] + node _T_201 = and(_T_196, _T_200) @[RoundRawFNToRecFN.scala 174:17] + node _T_204 = mux(pegMinNonzeroMagOut, UInt<9>("h06b"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 179:16] + node _T_205 = or(_T_201, _T_204) @[RoundRawFNToRecFN.scala 178:18] + node _T_208 = mux(pegMaxFiniteMagOut, UInt<9>("h017f"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 183:16] + node _T_209 = or(_T_205, _T_208) @[RoundRawFNToRecFN.scala 182:15] + node _T_212 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 187:16] + node _T_213 = or(_T_209, _T_212) @[RoundRawFNToRecFN.scala 186:15] + node _T_216 = mux(isNaNOut, UInt<9>("h01c0"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 188:16] + node expOut = or(_T_213, _T_216) @[RoundRawFNToRecFN.scala 187:71] + node _T_217 = or(common_totalUnderflow, isNaNOut) @[RoundRawFNToRecFN.scala 190:35] + node _T_219 = shl(UInt<1>("h01"), 22) @[RoundRawFNToRecFN.scala 191:34] + node _T_221 = mux(isNaNOut, _T_219, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 191:16] + node _T_222 = mux(_T_217, _T_221, common_fractOut) @[RoundRawFNToRecFN.scala 190:12] + node _T_223 = bits(pegMaxFiniteMagOut, 0, 0) @[Bitwise.scala 71:15] + node _T_226 = mux(_T_223, UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 71:12] + node fractOut = or(_T_222, _T_226) @[RoundRawFNToRecFN.scala 193:11] + node _T_227 = cat(signOut, expOut) @[Cat.scala 30:58] + node _T_228 = cat(_T_227, fractOut) @[Cat.scala 30:58] + io.out <= _T_228 @[RoundRawFNToRecFN.scala 196:12] + node _T_229 = cat(underflow, inexact) @[Cat.scala 30:58] + node _T_230 = cat(io.invalidExc, io.infiniteExc) @[Cat.scala 30:58] + node _T_231 = cat(_T_230, overflow) @[Cat.scala 30:58] + node _T_232 = cat(_T_231, _T_229) @[Cat.scala 30:58] + io.exceptionFlags <= _T_232 @[RoundRawFNToRecFN.scala 197:23] + + module MulAddRecFN_preMul : + input clock : Clock + input reset : UInt<1> + output io : {flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<2>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<7>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<26>, sExpSum : UInt<11>, roundingMode : UInt<2>}} + + io is invalid + io is invalid + node signA = bits(io.a, 32, 32) @[MulAddRecFN.scala 102:22] + node expA = bits(io.a, 31, 23) @[MulAddRecFN.scala 103:22] + node fractA = bits(io.a, 22, 0) @[MulAddRecFN.scala 104:22] + node _T_52 = bits(expA, 8, 6) @[MulAddRecFN.scala 105:24] + node isZeroA = eq(_T_52, UInt<1>("h00")) @[MulAddRecFN.scala 105:49] + node _T_55 = eq(isZeroA, UInt<1>("h00")) @[MulAddRecFN.scala 106:20] + node sigA = cat(_T_55, fractA) @[Cat.scala 30:58] + node signB = bits(io.b, 32, 32) @[MulAddRecFN.scala 108:22] + node expB = bits(io.b, 31, 23) @[MulAddRecFN.scala 109:22] + node fractB = bits(io.b, 22, 0) @[MulAddRecFN.scala 110:22] + node _T_56 = bits(expB, 8, 6) @[MulAddRecFN.scala 111:24] + node isZeroB = eq(_T_56, UInt<1>("h00")) @[MulAddRecFN.scala 111:49] + node _T_59 = eq(isZeroB, UInt<1>("h00")) @[MulAddRecFN.scala 112:20] + node sigB = cat(_T_59, fractB) @[Cat.scala 30:58] + node _T_60 = bits(io.c, 32, 32) @[MulAddRecFN.scala 114:23] + node _T_61 = bits(io.op, 0, 0) @[MulAddRecFN.scala 114:52] + node opSignC = xor(_T_60, _T_61) @[MulAddRecFN.scala 114:45] + node expC = bits(io.c, 31, 23) @[MulAddRecFN.scala 115:22] + node fractC = bits(io.c, 22, 0) @[MulAddRecFN.scala 116:22] + node _T_62 = bits(expC, 8, 6) @[MulAddRecFN.scala 117:24] + node isZeroC = eq(_T_62, UInt<1>("h00")) @[MulAddRecFN.scala 117:49] + node _T_65 = eq(isZeroC, UInt<1>("h00")) @[MulAddRecFN.scala 118:20] + node sigC = cat(_T_65, fractC) @[Cat.scala 30:58] + node _T_66 = xor(signA, signB) @[MulAddRecFN.scala 122:26] + node _T_67 = bits(io.op, 1, 1) @[MulAddRecFN.scala 122:41] + node signProd = xor(_T_66, _T_67) @[MulAddRecFN.scala 122:34] + node isZeroProd = or(isZeroA, isZeroB) @[MulAddRecFN.scala 123:30] + node _T_68 = bits(expB, 8, 8) @[MulAddRecFN.scala 125:34] + node _T_70 = eq(_T_68, UInt<1>("h00")) @[MulAddRecFN.scala 125:28] + node _T_71 = bits(_T_70, 0, 0) @[Bitwise.scala 71:15] + node _T_74 = mux(_T_71, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 71:12] + node _T_75 = bits(expB, 7, 0) @[MulAddRecFN.scala 125:51] + node _T_76 = cat(_T_74, _T_75) @[Cat.scala 30:58] + node _T_77 = add(expA, _T_76) @[MulAddRecFN.scala 125:14] + node _T_78 = tail(_T_77, 1) @[MulAddRecFN.scala 125:14] + node _T_80 = add(_T_78, UInt<5>("h01b")) @[MulAddRecFN.scala 125:70] + node sExpAlignedProd = tail(_T_80, 1) @[MulAddRecFN.scala 125:70] + node doSubMags = xor(signProd, opSignC) @[MulAddRecFN.scala 130:30] + node _T_81 = sub(sExpAlignedProd, expC) @[MulAddRecFN.scala 132:42] + node _T_82 = asUInt(_T_81) @[MulAddRecFN.scala 132:42] + node sNatCAlignDist = tail(_T_82, 1) @[MulAddRecFN.scala 132:42] + node _T_83 = bits(sNatCAlignDist, 10, 10) @[MulAddRecFN.scala 133:56] + node CAlignDist_floor = or(isZeroProd, _T_83) @[MulAddRecFN.scala 133:39] + node _T_84 = bits(sNatCAlignDist, 9, 0) @[MulAddRecFN.scala 135:44] + node _T_86 = eq(_T_84, UInt<1>("h00")) @[MulAddRecFN.scala 135:62] + node CAlignDist_0 = or(CAlignDist_floor, _T_86) @[MulAddRecFN.scala 135:26] + node _T_88 = eq(isZeroC, UInt<1>("h00")) @[MulAddRecFN.scala 137:9] + node _T_89 = bits(sNatCAlignDist, 9, 0) @[MulAddRecFN.scala 139:33] + node _T_91 = lt(_T_89, UInt<5>("h019")) @[MulAddRecFN.scala 139:51] + node _T_92 = or(CAlignDist_floor, _T_91) @[MulAddRecFN.scala 138:31] + node isCDominant = and(_T_88, _T_92) @[MulAddRecFN.scala 137:19] + node _T_94 = bits(sNatCAlignDist, 9, 0) @[MulAddRecFN.scala 143:31] + node _T_96 = lt(_T_94, UInt<7>("h04a")) @[MulAddRecFN.scala 143:49] + node _T_97 = bits(sNatCAlignDist, 6, 0) @[MulAddRecFN.scala 144:31] + node _T_99 = mux(_T_96, _T_97, UInt<7>("h04a")) @[MulAddRecFN.scala 143:16] + node CAlignDist = mux(CAlignDist_floor, UInt<1>("h00"), _T_99) @[MulAddRecFN.scala 141:12] + node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) @[MulAddRecFN.scala 148:22] + node _T_100 = bits(CAlignDist, 6, 6) @[primitives.scala 56:25] + node _T_101 = bits(CAlignDist, 5, 0) @[primitives.scala 57:26] + node _T_103 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_101) @[primitives.scala 68:52] + node _T_104 = bits(_T_103, 63, 54) @[primitives.scala 69:26] + node _T_105 = bits(_T_104, 7, 0) @[Bitwise.scala 108:18] + node _T_108 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 101:47] + node _T_109 = xor(UInt<8>("h0ff"), _T_108) @[Bitwise.scala 101:21] + node _T_110 = shr(_T_105, 4) @[Bitwise.scala 102:21] + node _T_111 = and(_T_110, _T_109) @[Bitwise.scala 102:31] + node _T_112 = bits(_T_105, 3, 0) @[Bitwise.scala 102:46] + node _T_113 = shl(_T_112, 4) @[Bitwise.scala 102:65] + node _T_114 = not(_T_109) @[Bitwise.scala 102:77] + node _T_115 = and(_T_113, _T_114) @[Bitwise.scala 102:75] + node _T_116 = or(_T_111, _T_115) @[Bitwise.scala 102:39] + node _T_117 = bits(_T_109, 5, 0) @[Bitwise.scala 101:28] + node _T_118 = shl(_T_117, 2) @[Bitwise.scala 101:47] + node _T_119 = xor(_T_109, _T_118) @[Bitwise.scala 101:21] + node _T_120 = shr(_T_116, 2) @[Bitwise.scala 102:21] + node _T_121 = and(_T_120, _T_119) @[Bitwise.scala 102:31] + node _T_122 = bits(_T_116, 5, 0) @[Bitwise.scala 102:46] + node _T_123 = shl(_T_122, 2) @[Bitwise.scala 102:65] + node _T_124 = not(_T_119) @[Bitwise.scala 102:77] + node _T_125 = and(_T_123, _T_124) @[Bitwise.scala 102:75] + node _T_126 = or(_T_121, _T_125) @[Bitwise.scala 102:39] + node _T_127 = bits(_T_119, 6, 0) @[Bitwise.scala 101:28] + node _T_128 = shl(_T_127, 1) @[Bitwise.scala 101:47] + node _T_129 = xor(_T_119, _T_128) @[Bitwise.scala 101:21] + node _T_130 = shr(_T_126, 1) @[Bitwise.scala 102:21] + node _T_131 = and(_T_130, _T_129) @[Bitwise.scala 102:31] + node _T_132 = bits(_T_126, 6, 0) @[Bitwise.scala 102:46] + node _T_133 = shl(_T_132, 1) @[Bitwise.scala 102:65] + node _T_134 = not(_T_129) @[Bitwise.scala 102:77] + node _T_135 = and(_T_133, _T_134) @[Bitwise.scala 102:75] + node _T_136 = or(_T_131, _T_135) @[Bitwise.scala 102:39] + node _T_137 = bits(_T_104, 9, 8) @[Bitwise.scala 108:44] + node _T_138 = bits(_T_137, 0, 0) @[Bitwise.scala 108:18] + node _T_139 = bits(_T_137, 1, 1) @[Bitwise.scala 108:44] + node _T_140 = cat(_T_138, _T_139) @[Cat.scala 30:58] + node _T_141 = cat(_T_136, _T_140) @[Cat.scala 30:58] + node _T_143 = cat(_T_141, UInt<14>("h03fff")) @[Cat.scala 30:58] + node _T_145 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_101) @[primitives.scala 68:52] + node _T_146 = bits(_T_145, 13, 0) @[primitives.scala 69:26] + node _T_147 = bits(_T_146, 7, 0) @[Bitwise.scala 108:18] + node _T_150 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 101:47] + node _T_151 = xor(UInt<8>("h0ff"), _T_150) @[Bitwise.scala 101:21] + node _T_152 = shr(_T_147, 4) @[Bitwise.scala 102:21] + node _T_153 = and(_T_152, _T_151) @[Bitwise.scala 102:31] + node _T_154 = bits(_T_147, 3, 0) @[Bitwise.scala 102:46] + node _T_155 = shl(_T_154, 4) @[Bitwise.scala 102:65] + node _T_156 = not(_T_151) @[Bitwise.scala 102:77] + node _T_157 = and(_T_155, _T_156) @[Bitwise.scala 102:75] + node _T_158 = or(_T_153, _T_157) @[Bitwise.scala 102:39] + node _T_159 = bits(_T_151, 5, 0) @[Bitwise.scala 101:28] + node _T_160 = shl(_T_159, 2) @[Bitwise.scala 101:47] + node _T_161 = xor(_T_151, _T_160) @[Bitwise.scala 101:21] + node _T_162 = shr(_T_158, 2) @[Bitwise.scala 102:21] + node _T_163 = and(_T_162, _T_161) @[Bitwise.scala 102:31] + node _T_164 = bits(_T_158, 5, 0) @[Bitwise.scala 102:46] + node _T_165 = shl(_T_164, 2) @[Bitwise.scala 102:65] + node _T_166 = not(_T_161) @[Bitwise.scala 102:77] + node _T_167 = and(_T_165, _T_166) @[Bitwise.scala 102:75] + node _T_168 = or(_T_163, _T_167) @[Bitwise.scala 102:39] + node _T_169 = bits(_T_161, 6, 0) @[Bitwise.scala 101:28] + node _T_170 = shl(_T_169, 1) @[Bitwise.scala 101:47] + node _T_171 = xor(_T_161, _T_170) @[Bitwise.scala 101:21] + node _T_172 = shr(_T_168, 1) @[Bitwise.scala 102:21] + node _T_173 = and(_T_172, _T_171) @[Bitwise.scala 102:31] + node _T_174 = bits(_T_168, 6, 0) @[Bitwise.scala 102:46] + node _T_175 = shl(_T_174, 1) @[Bitwise.scala 102:65] + node _T_176 = not(_T_171) @[Bitwise.scala 102:77] + node _T_177 = and(_T_175, _T_176) @[Bitwise.scala 102:75] + node _T_178 = or(_T_173, _T_177) @[Bitwise.scala 102:39] + node _T_179 = bits(_T_146, 13, 8) @[Bitwise.scala 108:44] + node _T_180 = bits(_T_179, 3, 0) @[Bitwise.scala 108:18] + node _T_181 = bits(_T_180, 1, 0) @[Bitwise.scala 108:18] + node _T_182 = bits(_T_181, 0, 0) @[Bitwise.scala 108:18] + node _T_183 = bits(_T_181, 1, 1) @[Bitwise.scala 108:44] + node _T_184 = cat(_T_182, _T_183) @[Cat.scala 30:58] + node _T_185 = bits(_T_180, 3, 2) @[Bitwise.scala 108:44] + node _T_186 = bits(_T_185, 0, 0) @[Bitwise.scala 108:18] + node _T_187 = bits(_T_185, 1, 1) @[Bitwise.scala 108:44] + node _T_188 = cat(_T_186, _T_187) @[Cat.scala 30:58] + node _T_189 = cat(_T_184, _T_188) @[Cat.scala 30:58] + node _T_190 = bits(_T_179, 5, 4) @[Bitwise.scala 108:44] + node _T_191 = bits(_T_190, 0, 0) @[Bitwise.scala 108:18] + node _T_192 = bits(_T_190, 1, 1) @[Bitwise.scala 108:44] + node _T_193 = cat(_T_191, _T_192) @[Cat.scala 30:58] + node _T_194 = cat(_T_189, _T_193) @[Cat.scala 30:58] + node _T_195 = cat(_T_178, _T_194) @[Cat.scala 30:58] + node CExtraMask = mux(_T_100, _T_143, _T_195) @[primitives.scala 61:20] + node _T_196 = not(sigC) @[MulAddRecFN.scala 151:34] + node negSigC = mux(doSubMags, _T_196, sigC) @[MulAddRecFN.scala 151:22] + node _T_197 = bits(doSubMags, 0, 0) @[Bitwise.scala 71:15] + node _T_200 = mux(_T_197, UInt<50>("h03ffffffffffff"), UInt<50>("h00")) @[Bitwise.scala 71:12] + node _T_201 = cat(doSubMags, negSigC) @[Cat.scala 30:58] + node _T_202 = cat(_T_201, _T_200) @[Cat.scala 30:58] + node _T_203 = asSInt(_T_202) @[MulAddRecFN.scala 154:64] + node _T_204 = dshr(_T_203, CAlignDist) @[MulAddRecFN.scala 154:70] + node _T_205 = and(sigC, CExtraMask) @[MulAddRecFN.scala 156:19] + node _T_207 = neq(_T_205, UInt<1>("h00")) @[MulAddRecFN.scala 156:33] + node _T_208 = xor(_T_207, doSubMags) @[MulAddRecFN.scala 156:37] + node _T_209 = asUInt(_T_204) @[Cat.scala 30:58] + node _T_210 = cat(_T_209, _T_208) @[Cat.scala 30:58] + node alignedNegSigC = bits(_T_210, 74, 0) @[MulAddRecFN.scala 157:10] + io.mulAddA <= sigA @[MulAddRecFN.scala 159:16] + io.mulAddB <= sigB @[MulAddRecFN.scala 160:16] + node _T_211 = bits(alignedNegSigC, 48, 1) @[MulAddRecFN.scala 161:33] + io.mulAddC <= _T_211 @[MulAddRecFN.scala 161:16] + node _T_212 = bits(expA, 8, 6) @[MulAddRecFN.scala 163:44] + io.toPostMul.highExpA <= _T_212 @[MulAddRecFN.scala 163:37] + node _T_213 = bits(fractA, 22, 22) @[MulAddRecFN.scala 164:46] + io.toPostMul.isNaN_isQuietNaNA <= _T_213 @[MulAddRecFN.scala 164:37] + node _T_214 = bits(expB, 8, 6) @[MulAddRecFN.scala 165:44] + io.toPostMul.highExpB <= _T_214 @[MulAddRecFN.scala 165:37] + node _T_215 = bits(fractB, 22, 22) @[MulAddRecFN.scala 166:46] + io.toPostMul.isNaN_isQuietNaNB <= _T_215 @[MulAddRecFN.scala 166:37] + io.toPostMul.signProd <= signProd @[MulAddRecFN.scala 167:37] + io.toPostMul.isZeroProd <= isZeroProd @[MulAddRecFN.scala 168:37] + io.toPostMul.opSignC <= opSignC @[MulAddRecFN.scala 169:37] + node _T_216 = bits(expC, 8, 6) @[MulAddRecFN.scala 170:44] + io.toPostMul.highExpC <= _T_216 @[MulAddRecFN.scala 170:37] + node _T_217 = bits(fractC, 22, 22) @[MulAddRecFN.scala 171:46] + io.toPostMul.isNaN_isQuietNaNC <= _T_217 @[MulAddRecFN.scala 171:37] + io.toPostMul.isCDominant <= isCDominant @[MulAddRecFN.scala 172:37] + io.toPostMul.CAlignDist_0 <= CAlignDist_0 @[MulAddRecFN.scala 173:37] + io.toPostMul.CAlignDist <= CAlignDist @[MulAddRecFN.scala 174:37] + node _T_218 = bits(alignedNegSigC, 0, 0) @[MulAddRecFN.scala 175:54] + io.toPostMul.bit0AlignedNegSigC <= _T_218 @[MulAddRecFN.scala 175:37] + node _T_219 = bits(alignedNegSigC, 74, 49) @[MulAddRecFN.scala 177:23] + io.toPostMul.highAlignedNegSigC <= _T_219 @[MulAddRecFN.scala 176:37] + io.toPostMul.sExpSum <= sExpSum @[MulAddRecFN.scala 178:37] + io.toPostMul.roundingMode <= io.roundingMode @[MulAddRecFN.scala 179:37] + + module MulAddRecFN_postMul : + input clock : Clock + input reset : UInt<1> + output io : {flip fromPreMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<7>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<26>, sExpSum : UInt<11>, roundingMode : UInt<2>}, flip mulAddResult : UInt<49>, out : UInt<33>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + node isZeroA = eq(io.fromPreMul.highExpA, UInt<1>("h00")) @[MulAddRecFN.scala 207:46] + node _T_43 = bits(io.fromPreMul.highExpA, 2, 1) @[MulAddRecFN.scala 208:45] + node isSpecialA = eq(_T_43, UInt<2>("h03")) @[MulAddRecFN.scala 208:52] + node _T_45 = bits(io.fromPreMul.highExpA, 0, 0) @[MulAddRecFN.scala 209:56] + node _T_47 = eq(_T_45, UInt<1>("h00")) @[MulAddRecFN.scala 209:32] + node isInfA = and(isSpecialA, _T_47) @[MulAddRecFN.scala 209:29] + node _T_48 = bits(io.fromPreMul.highExpA, 0, 0) @[MulAddRecFN.scala 210:56] + node isNaNA = and(isSpecialA, _T_48) @[MulAddRecFN.scala 210:29] + node _T_50 = eq(io.fromPreMul.isNaN_isQuietNaNA, UInt<1>("h00")) @[MulAddRecFN.scala 211:31] + node isSigNaNA = and(isNaNA, _T_50) @[MulAddRecFN.scala 211:28] + node isZeroB = eq(io.fromPreMul.highExpB, UInt<1>("h00")) @[MulAddRecFN.scala 213:46] + node _T_52 = bits(io.fromPreMul.highExpB, 2, 1) @[MulAddRecFN.scala 214:45] + node isSpecialB = eq(_T_52, UInt<2>("h03")) @[MulAddRecFN.scala 214:52] + node _T_54 = bits(io.fromPreMul.highExpB, 0, 0) @[MulAddRecFN.scala 215:56] + node _T_56 = eq(_T_54, UInt<1>("h00")) @[MulAddRecFN.scala 215:32] + node isInfB = and(isSpecialB, _T_56) @[MulAddRecFN.scala 215:29] + node _T_57 = bits(io.fromPreMul.highExpB, 0, 0) @[MulAddRecFN.scala 216:56] + node isNaNB = and(isSpecialB, _T_57) @[MulAddRecFN.scala 216:29] + node _T_59 = eq(io.fromPreMul.isNaN_isQuietNaNB, UInt<1>("h00")) @[MulAddRecFN.scala 217:31] + node isSigNaNB = and(isNaNB, _T_59) @[MulAddRecFN.scala 217:28] + node isZeroC = eq(io.fromPreMul.highExpC, UInt<1>("h00")) @[MulAddRecFN.scala 219:46] + node _T_61 = bits(io.fromPreMul.highExpC, 2, 1) @[MulAddRecFN.scala 220:45] + node isSpecialC = eq(_T_61, UInt<2>("h03")) @[MulAddRecFN.scala 220:52] + node _T_63 = bits(io.fromPreMul.highExpC, 0, 0) @[MulAddRecFN.scala 221:56] + node _T_65 = eq(_T_63, UInt<1>("h00")) @[MulAddRecFN.scala 221:32] + node isInfC = and(isSpecialC, _T_65) @[MulAddRecFN.scala 221:29] + node _T_66 = bits(io.fromPreMul.highExpC, 0, 0) @[MulAddRecFN.scala 222:56] + node isNaNC = and(isSpecialC, _T_66) @[MulAddRecFN.scala 222:29] + node _T_68 = eq(io.fromPreMul.isNaN_isQuietNaNC, UInt<1>("h00")) @[MulAddRecFN.scala 223:31] + node isSigNaNC = and(isNaNC, _T_68) @[MulAddRecFN.scala 223:28] + node roundingMode_nearest_even = eq(io.fromPreMul.roundingMode, UInt<2>("h00")) @[MulAddRecFN.scala 226:37] + node roundingMode_minMag = eq(io.fromPreMul.roundingMode, UInt<2>("h01")) @[MulAddRecFN.scala 227:59] + node roundingMode_min = eq(io.fromPreMul.roundingMode, UInt<2>("h02")) @[MulAddRecFN.scala 228:59] + node roundingMode_max = eq(io.fromPreMul.roundingMode, UInt<2>("h03")) @[MulAddRecFN.scala 229:59] + node signZeroNotEqOpSigns = mux(roundingMode_min, UInt<1>("h01"), UInt<1>("h00")) @[MulAddRecFN.scala 231:35] + node doSubMags = xor(io.fromPreMul.signProd, io.fromPreMul.opSignC) @[MulAddRecFN.scala 232:44] + node _T_71 = bits(io.mulAddResult, 48, 48) @[MulAddRecFN.scala 237:32] + node _T_73 = add(io.fromPreMul.highAlignedNegSigC, UInt<1>("h01")) @[MulAddRecFN.scala 238:50] + node _T_74 = tail(_T_73, 1) @[MulAddRecFN.scala 238:50] + node _T_75 = mux(_T_71, _T_74, io.fromPreMul.highAlignedNegSigC) @[MulAddRecFN.scala 237:16] + node _T_76 = bits(io.mulAddResult, 47, 0) @[MulAddRecFN.scala 241:28] + node _T_77 = cat(_T_75, _T_76) @[Cat.scala 30:58] + node sigSum = cat(_T_77, io.fromPreMul.bit0AlignedNegSigC) @[Cat.scala 30:58] + node _T_79 = bits(sigSum, 50, 1) @[MulAddRecFN.scala 248:38] + node _T_80 = xor(UInt<50>("h00"), _T_79) @[MulAddRecFN.scala 191:27] + node _T_81 = or(UInt<50>("h00"), _T_79) @[MulAddRecFN.scala 191:37] + node _T_82 = shl(_T_81, 1) @[MulAddRecFN.scala 191:41] + node _T_83 = xor(_T_80, _T_82) @[MulAddRecFN.scala 191:32] + node _T_85 = bits(_T_83, 49, 0) @[primitives.scala 79:35] + node _T_86 = bits(_T_85, 49, 32) @[CircuitMath.scala 35:17] + node _T_87 = bits(_T_85, 31, 0) @[CircuitMath.scala 36:17] + node _T_89 = neq(_T_86, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_90 = bits(_T_86, 17, 16) @[CircuitMath.scala 35:17] + node _T_91 = bits(_T_86, 15, 0) @[CircuitMath.scala 36:17] + node _T_93 = neq(_T_90, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_94 = bits(_T_90, 1, 1) @[CircuitMath.scala 30:8] + node _T_95 = bits(_T_91, 15, 8) @[CircuitMath.scala 35:17] + node _T_96 = bits(_T_91, 7, 0) @[CircuitMath.scala 36:17] + node _T_98 = neq(_T_95, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_99 = bits(_T_95, 7, 4) @[CircuitMath.scala 35:17] + node _T_100 = bits(_T_95, 3, 0) @[CircuitMath.scala 36:17] + node _T_102 = neq(_T_99, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_103 = bits(_T_99, 3, 3) @[CircuitMath.scala 32:12] + node _T_105 = bits(_T_99, 2, 2) @[CircuitMath.scala 32:12] + node _T_107 = bits(_T_99, 1, 1) @[CircuitMath.scala 30:8] + node _T_108 = mux(_T_105, UInt<2>("h02"), _T_107) @[CircuitMath.scala 32:10] + node _T_109 = mux(_T_103, UInt<2>("h03"), _T_108) @[CircuitMath.scala 32:10] + node _T_110 = bits(_T_100, 3, 3) @[CircuitMath.scala 32:12] + node _T_112 = bits(_T_100, 2, 2) @[CircuitMath.scala 32:12] + node _T_114 = bits(_T_100, 1, 1) @[CircuitMath.scala 30:8] + node _T_115 = mux(_T_112, UInt<2>("h02"), _T_114) @[CircuitMath.scala 32:10] + node _T_116 = mux(_T_110, UInt<2>("h03"), _T_115) @[CircuitMath.scala 32:10] + node _T_117 = mux(_T_102, _T_109, _T_116) @[CircuitMath.scala 38:21] + node _T_118 = cat(_T_102, _T_117) @[Cat.scala 30:58] + node _T_119 = bits(_T_96, 7, 4) @[CircuitMath.scala 35:17] + node _T_120 = bits(_T_96, 3, 0) @[CircuitMath.scala 36:17] + node _T_122 = neq(_T_119, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_123 = bits(_T_119, 3, 3) @[CircuitMath.scala 32:12] + node _T_125 = bits(_T_119, 2, 2) @[CircuitMath.scala 32:12] + node _T_127 = bits(_T_119, 1, 1) @[CircuitMath.scala 30:8] + node _T_128 = mux(_T_125, UInt<2>("h02"), _T_127) @[CircuitMath.scala 32:10] + node _T_129 = mux(_T_123, UInt<2>("h03"), _T_128) @[CircuitMath.scala 32:10] + node _T_130 = bits(_T_120, 3, 3) @[CircuitMath.scala 32:12] + node _T_132 = bits(_T_120, 2, 2) @[CircuitMath.scala 32:12] + node _T_134 = bits(_T_120, 1, 1) @[CircuitMath.scala 30:8] + node _T_135 = mux(_T_132, UInt<2>("h02"), _T_134) @[CircuitMath.scala 32:10] + node _T_136 = mux(_T_130, UInt<2>("h03"), _T_135) @[CircuitMath.scala 32:10] + node _T_137 = mux(_T_122, _T_129, _T_136) @[CircuitMath.scala 38:21] + node _T_138 = cat(_T_122, _T_137) @[Cat.scala 30:58] + node _T_139 = mux(_T_98, _T_118, _T_138) @[CircuitMath.scala 38:21] + node _T_140 = cat(_T_98, _T_139) @[Cat.scala 30:58] + node _T_141 = mux(_T_93, _T_94, _T_140) @[CircuitMath.scala 38:21] + node _T_142 = cat(_T_93, _T_141) @[Cat.scala 30:58] + node _T_143 = bits(_T_87, 31, 16) @[CircuitMath.scala 35:17] + node _T_144 = bits(_T_87, 15, 0) @[CircuitMath.scala 36:17] + node _T_146 = neq(_T_143, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_147 = bits(_T_143, 15, 8) @[CircuitMath.scala 35:17] + node _T_148 = bits(_T_143, 7, 0) @[CircuitMath.scala 36:17] + node _T_150 = neq(_T_147, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_151 = bits(_T_147, 7, 4) @[CircuitMath.scala 35:17] + node _T_152 = bits(_T_147, 3, 0) @[CircuitMath.scala 36:17] + node _T_154 = neq(_T_151, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_155 = bits(_T_151, 3, 3) @[CircuitMath.scala 32:12] + node _T_157 = bits(_T_151, 2, 2) @[CircuitMath.scala 32:12] + node _T_159 = bits(_T_151, 1, 1) @[CircuitMath.scala 30:8] + node _T_160 = mux(_T_157, UInt<2>("h02"), _T_159) @[CircuitMath.scala 32:10] + node _T_161 = mux(_T_155, UInt<2>("h03"), _T_160) @[CircuitMath.scala 32:10] + node _T_162 = bits(_T_152, 3, 3) @[CircuitMath.scala 32:12] + node _T_164 = bits(_T_152, 2, 2) @[CircuitMath.scala 32:12] + node _T_166 = bits(_T_152, 1, 1) @[CircuitMath.scala 30:8] + node _T_167 = mux(_T_164, UInt<2>("h02"), _T_166) @[CircuitMath.scala 32:10] + node _T_168 = mux(_T_162, UInt<2>("h03"), _T_167) @[CircuitMath.scala 32:10] + node _T_169 = mux(_T_154, _T_161, _T_168) @[CircuitMath.scala 38:21] + node _T_170 = cat(_T_154, _T_169) @[Cat.scala 30:58] + node _T_171 = bits(_T_148, 7, 4) @[CircuitMath.scala 35:17] + node _T_172 = bits(_T_148, 3, 0) @[CircuitMath.scala 36:17] + node _T_174 = neq(_T_171, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_175 = bits(_T_171, 3, 3) @[CircuitMath.scala 32:12] + node _T_177 = bits(_T_171, 2, 2) @[CircuitMath.scala 32:12] + node _T_179 = bits(_T_171, 1, 1) @[CircuitMath.scala 30:8] + node _T_180 = mux(_T_177, UInt<2>("h02"), _T_179) @[CircuitMath.scala 32:10] + node _T_181 = mux(_T_175, UInt<2>("h03"), _T_180) @[CircuitMath.scala 32:10] + node _T_182 = bits(_T_172, 3, 3) @[CircuitMath.scala 32:12] + node _T_184 = bits(_T_172, 2, 2) @[CircuitMath.scala 32:12] + node _T_186 = bits(_T_172, 1, 1) @[CircuitMath.scala 30:8] + node _T_187 = mux(_T_184, UInt<2>("h02"), _T_186) @[CircuitMath.scala 32:10] + node _T_188 = mux(_T_182, UInt<2>("h03"), _T_187) @[CircuitMath.scala 32:10] + node _T_189 = mux(_T_174, _T_181, _T_188) @[CircuitMath.scala 38:21] + node _T_190 = cat(_T_174, _T_189) @[Cat.scala 30:58] + node _T_191 = mux(_T_150, _T_170, _T_190) @[CircuitMath.scala 38:21] + node _T_192 = cat(_T_150, _T_191) @[Cat.scala 30:58] + node _T_193 = bits(_T_144, 15, 8) @[CircuitMath.scala 35:17] + node _T_194 = bits(_T_144, 7, 0) @[CircuitMath.scala 36:17] + node _T_196 = neq(_T_193, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_197 = bits(_T_193, 7, 4) @[CircuitMath.scala 35:17] + node _T_198 = bits(_T_193, 3, 0) @[CircuitMath.scala 36:17] + node _T_200 = neq(_T_197, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_201 = bits(_T_197, 3, 3) @[CircuitMath.scala 32:12] + node _T_203 = bits(_T_197, 2, 2) @[CircuitMath.scala 32:12] + node _T_205 = bits(_T_197, 1, 1) @[CircuitMath.scala 30:8] + node _T_206 = mux(_T_203, UInt<2>("h02"), _T_205) @[CircuitMath.scala 32:10] + node _T_207 = mux(_T_201, UInt<2>("h03"), _T_206) @[CircuitMath.scala 32:10] + node _T_208 = bits(_T_198, 3, 3) @[CircuitMath.scala 32:12] + node _T_210 = bits(_T_198, 2, 2) @[CircuitMath.scala 32:12] + node _T_212 = bits(_T_198, 1, 1) @[CircuitMath.scala 30:8] + node _T_213 = mux(_T_210, UInt<2>("h02"), _T_212) @[CircuitMath.scala 32:10] + node _T_214 = mux(_T_208, UInt<2>("h03"), _T_213) @[CircuitMath.scala 32:10] + node _T_215 = mux(_T_200, _T_207, _T_214) @[CircuitMath.scala 38:21] + node _T_216 = cat(_T_200, _T_215) @[Cat.scala 30:58] + node _T_217 = bits(_T_194, 7, 4) @[CircuitMath.scala 35:17] + node _T_218 = bits(_T_194, 3, 0) @[CircuitMath.scala 36:17] + node _T_220 = neq(_T_217, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_221 = bits(_T_217, 3, 3) @[CircuitMath.scala 32:12] + node _T_223 = bits(_T_217, 2, 2) @[CircuitMath.scala 32:12] + node _T_225 = bits(_T_217, 1, 1) @[CircuitMath.scala 30:8] + node _T_226 = mux(_T_223, UInt<2>("h02"), _T_225) @[CircuitMath.scala 32:10] + node _T_227 = mux(_T_221, UInt<2>("h03"), _T_226) @[CircuitMath.scala 32:10] + node _T_228 = bits(_T_218, 3, 3) @[CircuitMath.scala 32:12] + node _T_230 = bits(_T_218, 2, 2) @[CircuitMath.scala 32:12] + node _T_232 = bits(_T_218, 1, 1) @[CircuitMath.scala 30:8] + node _T_233 = mux(_T_230, UInt<2>("h02"), _T_232) @[CircuitMath.scala 32:10] + node _T_234 = mux(_T_228, UInt<2>("h03"), _T_233) @[CircuitMath.scala 32:10] + node _T_235 = mux(_T_220, _T_227, _T_234) @[CircuitMath.scala 38:21] + node _T_236 = cat(_T_220, _T_235) @[Cat.scala 30:58] + node _T_237 = mux(_T_196, _T_216, _T_236) @[CircuitMath.scala 38:21] + node _T_238 = cat(_T_196, _T_237) @[Cat.scala 30:58] + node _T_239 = mux(_T_146, _T_192, _T_238) @[CircuitMath.scala 38:21] + node _T_240 = cat(_T_146, _T_239) @[Cat.scala 30:58] + node _T_241 = mux(_T_89, _T_142, _T_240) @[CircuitMath.scala 38:21] + node _T_242 = cat(_T_89, _T_241) @[Cat.scala 30:58] + node _T_243 = sub(UInt<7>("h049"), _T_242) @[primitives.scala 79:25] + node _T_244 = asUInt(_T_243) @[primitives.scala 79:25] + node estNormNeg_dist = tail(_T_244, 1) @[primitives.scala 79:25] + node _T_245 = bits(sigSum, 33, 18) @[MulAddRecFN.scala 252:19] + node _T_247 = neq(_T_245, UInt<1>("h00")) @[MulAddRecFN.scala 254:15] + node _T_248 = bits(sigSum, 17, 0) @[MulAddRecFN.scala 255:19] + node _T_250 = neq(_T_248, UInt<1>("h00")) @[MulAddRecFN.scala 255:57] + node firstReduceSigSum = cat(_T_247, _T_250) @[Cat.scala 30:58] + node complSigSum = not(sigSum) @[MulAddRecFN.scala 257:23] + node _T_251 = bits(complSigSum, 33, 18) @[MulAddRecFN.scala 259:24] + node _T_253 = neq(_T_251, UInt<1>("h00")) @[MulAddRecFN.scala 261:15] + node _T_254 = bits(complSigSum, 17, 0) @[MulAddRecFN.scala 262:24] + node _T_256 = neq(_T_254, UInt<1>("h00")) @[MulAddRecFN.scala 262:62] + node firstReduceComplSigSum = cat(_T_253, _T_256) @[Cat.scala 30:58] + node _T_257 = or(io.fromPreMul.CAlignDist_0, doSubMags) @[MulAddRecFN.scala 266:40] + node _T_259 = sub(io.fromPreMul.CAlignDist, UInt<1>("h01")) @[MulAddRecFN.scala 268:39] + node _T_260 = asUInt(_T_259) @[MulAddRecFN.scala 268:39] + node _T_261 = tail(_T_260, 1) @[MulAddRecFN.scala 268:39] + node _T_262 = bits(_T_261, 4, 0) @[MulAddRecFN.scala 268:49] + node CDom_estNormDist = mux(_T_257, io.fromPreMul.CAlignDist, _T_262) @[MulAddRecFN.scala 266:12] + node _T_264 = eq(doSubMags, UInt<1>("h00")) @[MulAddRecFN.scala 271:13] + node _T_265 = bits(CDom_estNormDist, 4, 4) @[MulAddRecFN.scala 271:46] + node _T_267 = eq(_T_265, UInt<1>("h00")) @[MulAddRecFN.scala 271:28] + node _T_268 = and(_T_264, _T_267) @[MulAddRecFN.scala 271:25] + node _T_269 = bits(sigSum, 74, 34) @[MulAddRecFN.scala 272:23] + node _T_271 = neq(firstReduceSigSum, UInt<1>("h00")) @[MulAddRecFN.scala 273:35] + node _T_272 = cat(_T_269, _T_271) @[Cat.scala 30:58] + node _T_274 = mux(_T_268, _T_272, UInt<1>("h00")) @[MulAddRecFN.scala 271:12] + node _T_276 = eq(doSubMags, UInt<1>("h00")) @[MulAddRecFN.scala 277:13] + node _T_277 = bits(CDom_estNormDist, 4, 4) @[MulAddRecFN.scala 277:44] + node _T_278 = and(_T_276, _T_277) @[MulAddRecFN.scala 277:25] + node _T_279 = bits(sigSum, 58, 18) @[MulAddRecFN.scala 278:23] + node _T_280 = bits(firstReduceSigSum, 0, 0) @[MulAddRecFN.scala 282:34] + node _T_281 = cat(_T_279, _T_280) @[Cat.scala 30:58] + node _T_283 = mux(_T_278, _T_281, UInt<1>("h00")) @[MulAddRecFN.scala 277:12] + node _T_284 = or(_T_274, _T_283) @[MulAddRecFN.scala 276:11] + node _T_285 = bits(CDom_estNormDist, 4, 4) @[MulAddRecFN.scala 286:44] + node _T_287 = eq(_T_285, UInt<1>("h00")) @[MulAddRecFN.scala 286:26] + node _T_288 = and(doSubMags, _T_287) @[MulAddRecFN.scala 286:23] + node _T_289 = bits(complSigSum, 74, 34) @[MulAddRecFN.scala 287:28] + node _T_291 = neq(firstReduceComplSigSum, UInt<1>("h00")) @[MulAddRecFN.scala 288:40] + node _T_292 = cat(_T_289, _T_291) @[Cat.scala 30:58] + node _T_294 = mux(_T_288, _T_292, UInt<1>("h00")) @[MulAddRecFN.scala 286:12] + node _T_295 = or(_T_284, _T_294) @[MulAddRecFN.scala 285:11] + node _T_296 = bits(CDom_estNormDist, 4, 4) @[MulAddRecFN.scala 292:42] + node _T_297 = and(doSubMags, _T_296) @[MulAddRecFN.scala 292:23] + node _T_298 = bits(complSigSum, 58, 18) @[MulAddRecFN.scala 293:28] + node _T_299 = bits(firstReduceComplSigSum, 0, 0) @[MulAddRecFN.scala 297:39] + node _T_300 = cat(_T_298, _T_299) @[Cat.scala 30:58] + node _T_302 = mux(_T_297, _T_300, UInt<1>("h00")) @[MulAddRecFN.scala 292:12] + node CDom_firstNormAbsSigSum = or(_T_295, _T_302) @[MulAddRecFN.scala 291:11] + node _T_303 = bits(sigSum, 50, 18) @[MulAddRecFN.scala 308:23] + node _T_304 = bits(firstReduceComplSigSum, 0, 0) @[MulAddRecFN.scala 310:45] + node _T_306 = eq(_T_304, UInt<1>("h00")) @[MulAddRecFN.scala 310:21] + node _T_307 = bits(firstReduceSigSum, 0, 0) @[MulAddRecFN.scala 311:38] + node _T_308 = mux(doSubMags, _T_306, _T_307) @[MulAddRecFN.scala 309:20] + node _T_309 = cat(_T_303, _T_308) @[Cat.scala 30:58] + node _T_310 = bits(sigSum, 42, 1) @[MulAddRecFN.scala 314:24] + node _T_311 = bits(estNormNeg_dist, 5, 5) @[MulAddRecFN.scala 338:28] + node _T_312 = bits(estNormNeg_dist, 4, 4) @[MulAddRecFN.scala 339:33] + node _T_313 = bits(sigSum, 26, 1) @[MulAddRecFN.scala 340:28] + node _T_314 = bits(doSubMags, 0, 0) @[Bitwise.scala 71:15] + node _T_317 = mux(_T_314, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 71:12] + node _T_318 = cat(_T_313, _T_317) @[Cat.scala 30:58] + node _T_319 = mux(_T_312, _T_318, _T_310) @[MulAddRecFN.scala 339:17] + node _T_320 = bits(estNormNeg_dist, 4, 4) @[MulAddRecFN.scala 345:33] + node _T_321 = bits(sigSum, 10, 1) @[MulAddRecFN.scala 347:28] + node _T_322 = bits(doSubMags, 0, 0) @[Bitwise.scala 71:15] + node _T_325 = mux(_T_322, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12] + node _T_326 = cat(_T_321, _T_325) @[Cat.scala 30:58] + node _T_327 = mux(_T_320, _T_309, _T_326) @[MulAddRecFN.scala 345:17] + node notCDom_pos_firstNormAbsSigSum = mux(_T_311, _T_319, _T_327) @[MulAddRecFN.scala 338:12] + node _T_328 = bits(complSigSum, 49, 18) @[MulAddRecFN.scala 360:28] + node _T_329 = bits(firstReduceComplSigSum, 0, 0) @[MulAddRecFN.scala 361:39] + node _T_330 = cat(_T_328, _T_329) @[Cat.scala 30:58] + node _T_331 = bits(complSigSum, 42, 1) @[MulAddRecFN.scala 363:29] + node _T_332 = bits(estNormNeg_dist, 5, 5) @[MulAddRecFN.scala 379:28] + node _T_333 = bits(estNormNeg_dist, 4, 4) @[MulAddRecFN.scala 380:33] + node _T_334 = bits(complSigSum, 27, 1) @[MulAddRecFN.scala 381:29] + node _T_335 = shl(_T_334, 16) @[MulAddRecFN.scala 381:64] + node _T_336 = mux(_T_333, _T_335, _T_331) @[MulAddRecFN.scala 380:17] + node _T_337 = bits(estNormNeg_dist, 4, 4) @[MulAddRecFN.scala 385:33] + node _T_338 = bits(complSigSum, 11, 1) @[MulAddRecFN.scala 387:29] + node _T_339 = shl(_T_338, 32) @[MulAddRecFN.scala 387:64] + node _T_340 = mux(_T_337, _T_330, _T_339) @[MulAddRecFN.scala 385:17] + node notCDom_neg_cFirstNormAbsSigSum = mux(_T_332, _T_336, _T_340) @[MulAddRecFN.scala 379:12] + node notCDom_signSigSum = bits(sigSum, 51, 51) @[MulAddRecFN.scala 392:36] + node _T_342 = eq(isZeroC, UInt<1>("h00")) @[MulAddRecFN.scala 395:26] + node _T_343 = and(doSubMags, _T_342) @[MulAddRecFN.scala 395:23] + node doNegSignSum = mux(io.fromPreMul.isCDominant, _T_343, notCDom_signSigSum) @[MulAddRecFN.scala 394:12] + node _T_344 = mux(notCDom_signSigSum, estNormNeg_dist, estNormNeg_dist) @[MulAddRecFN.scala 401:16] + node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, _T_344) @[MulAddRecFN.scala 399:12] + node _T_345 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) @[MulAddRecFN.scala 408:16] + node _T_346 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) @[MulAddRecFN.scala 412:16] + node cFirstNormAbsSigSum = mux(notCDom_signSigSum, _T_345, _T_346) @[MulAddRecFN.scala 407:12] + node _T_348 = eq(io.fromPreMul.isCDominant, UInt<1>("h00")) @[MulAddRecFN.scala 418:9] + node _T_350 = eq(notCDom_signSigSum, UInt<1>("h00")) @[MulAddRecFN.scala 418:40] + node _T_351 = and(_T_348, _T_350) @[MulAddRecFN.scala 418:37] + node doIncrSig = and(_T_351, doSubMags) @[MulAddRecFN.scala 418:61] + node estNormDist_5 = bits(estNormDist, 3, 0) @[MulAddRecFN.scala 419:36] + node normTo2ShiftDist = not(estNormDist_5) @[MulAddRecFN.scala 420:28] + node _T_353 = dshr(asSInt(UInt<17>("h010000")), normTo2ShiftDist) @[primitives.scala 68:52] + node _T_354 = bits(_T_353, 15, 1) @[primitives.scala 69:26] + node _T_355 = bits(_T_354, 7, 0) @[Bitwise.scala 108:18] + node _T_358 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 101:47] + node _T_359 = xor(UInt<8>("h0ff"), _T_358) @[Bitwise.scala 101:21] + node _T_360 = shr(_T_355, 4) @[Bitwise.scala 102:21] + node _T_361 = and(_T_360, _T_359) @[Bitwise.scala 102:31] + node _T_362 = bits(_T_355, 3, 0) @[Bitwise.scala 102:46] + node _T_363 = shl(_T_362, 4) @[Bitwise.scala 102:65] + node _T_364 = not(_T_359) @[Bitwise.scala 102:77] + node _T_365 = and(_T_363, _T_364) @[Bitwise.scala 102:75] + node _T_366 = or(_T_361, _T_365) @[Bitwise.scala 102:39] + node _T_367 = bits(_T_359, 5, 0) @[Bitwise.scala 101:28] + node _T_368 = shl(_T_367, 2) @[Bitwise.scala 101:47] + node _T_369 = xor(_T_359, _T_368) @[Bitwise.scala 101:21] + node _T_370 = shr(_T_366, 2) @[Bitwise.scala 102:21] + node _T_371 = and(_T_370, _T_369) @[Bitwise.scala 102:31] + node _T_372 = bits(_T_366, 5, 0) @[Bitwise.scala 102:46] + node _T_373 = shl(_T_372, 2) @[Bitwise.scala 102:65] + node _T_374 = not(_T_369) @[Bitwise.scala 102:77] + node _T_375 = and(_T_373, _T_374) @[Bitwise.scala 102:75] + node _T_376 = or(_T_371, _T_375) @[Bitwise.scala 102:39] + node _T_377 = bits(_T_369, 6, 0) @[Bitwise.scala 101:28] + node _T_378 = shl(_T_377, 1) @[Bitwise.scala 101:47] + node _T_379 = xor(_T_369, _T_378) @[Bitwise.scala 101:21] + node _T_380 = shr(_T_376, 1) @[Bitwise.scala 102:21] + node _T_381 = and(_T_380, _T_379) @[Bitwise.scala 102:31] + node _T_382 = bits(_T_376, 6, 0) @[Bitwise.scala 102:46] + node _T_383 = shl(_T_382, 1) @[Bitwise.scala 102:65] + node _T_384 = not(_T_379) @[Bitwise.scala 102:77] + node _T_385 = and(_T_383, _T_384) @[Bitwise.scala 102:75] + node _T_386 = or(_T_381, _T_385) @[Bitwise.scala 102:39] + node _T_387 = bits(_T_354, 14, 8) @[Bitwise.scala 108:44] + node _T_388 = bits(_T_387, 3, 0) @[Bitwise.scala 108:18] + node _T_389 = bits(_T_388, 1, 0) @[Bitwise.scala 108:18] + node _T_390 = bits(_T_389, 0, 0) @[Bitwise.scala 108:18] + node _T_391 = bits(_T_389, 1, 1) @[Bitwise.scala 108:44] + node _T_392 = cat(_T_390, _T_391) @[Cat.scala 30:58] + node _T_393 = bits(_T_388, 3, 2) @[Bitwise.scala 108:44] + node _T_394 = bits(_T_393, 0, 0) @[Bitwise.scala 108:18] + node _T_395 = bits(_T_393, 1, 1) @[Bitwise.scala 108:44] + node _T_396 = cat(_T_394, _T_395) @[Cat.scala 30:58] + node _T_397 = cat(_T_392, _T_396) @[Cat.scala 30:58] + node _T_398 = bits(_T_387, 6, 4) @[Bitwise.scala 108:44] + node _T_399 = bits(_T_398, 1, 0) @[Bitwise.scala 108:18] + node _T_400 = bits(_T_399, 0, 0) @[Bitwise.scala 108:18] + node _T_401 = bits(_T_399, 1, 1) @[Bitwise.scala 108:44] + node _T_402 = cat(_T_400, _T_401) @[Cat.scala 30:58] + node _T_403 = bits(_T_398, 2, 2) @[Bitwise.scala 108:44] + node _T_404 = cat(_T_402, _T_403) @[Cat.scala 30:58] + node _T_405 = cat(_T_397, _T_404) @[Cat.scala 30:58] + node _T_406 = cat(_T_386, _T_405) @[Cat.scala 30:58] + node absSigSumExtraMask = cat(_T_406, UInt<1>("h01")) @[Cat.scala 30:58] + node _T_408 = bits(cFirstNormAbsSigSum, 42, 1) @[MulAddRecFN.scala 424:32] + node _T_409 = dshr(_T_408, normTo2ShiftDist) @[MulAddRecFN.scala 424:65] + node _T_410 = bits(cFirstNormAbsSigSum, 15, 0) @[MulAddRecFN.scala 427:39] + node _T_411 = not(_T_410) @[MulAddRecFN.scala 427:19] + node _T_412 = and(_T_411, absSigSumExtraMask) @[MulAddRecFN.scala 427:62] + node _T_414 = eq(_T_412, UInt<1>("h00")) @[MulAddRecFN.scala 428:43] + node _T_415 = bits(cFirstNormAbsSigSum, 15, 0) @[MulAddRecFN.scala 430:38] + node _T_416 = and(_T_415, absSigSumExtraMask) @[MulAddRecFN.scala 430:61] + node _T_418 = neq(_T_416, UInt<1>("h00")) @[MulAddRecFN.scala 431:43] + node _T_419 = mux(doIncrSig, _T_414, _T_418) @[MulAddRecFN.scala 426:16] + node _T_420 = cat(_T_409, _T_419) @[Cat.scala 30:58] + node sigX3 = bits(_T_420, 27, 0) @[MulAddRecFN.scala 434:10] + node _T_421 = bits(sigX3, 27, 26) @[MulAddRecFN.scala 436:29] + node sigX3Shift1 = eq(_T_421, UInt<1>("h00")) @[MulAddRecFN.scala 436:58] + node _T_423 = sub(io.fromPreMul.sExpSum, estNormDist) @[MulAddRecFN.scala 437:40] + node _T_424 = asUInt(_T_423) @[MulAddRecFN.scala 437:40] + node sExpX3 = tail(_T_424, 1) @[MulAddRecFN.scala 437:40] + node _T_425 = bits(sigX3, 27, 25) @[MulAddRecFN.scala 439:25] + node isZeroY = eq(_T_425, UInt<1>("h00")) @[MulAddRecFN.scala 439:54] + node _T_427 = xor(io.fromPreMul.signProd, doNegSignSum) @[MulAddRecFN.scala 444:36] + node signY = mux(isZeroY, signZeroNotEqOpSigns, _T_427) @[MulAddRecFN.scala 442:12] + node sExpX3_13 = bits(sExpX3, 9, 0) @[MulAddRecFN.scala 446:27] + node _T_428 = bits(sExpX3, 10, 10) @[MulAddRecFN.scala 448:34] + node _T_429 = bits(_T_428, 0, 0) @[Bitwise.scala 71:15] + node _T_432 = mux(_T_429, UInt<27>("h07ffffff"), UInt<27>("h00")) @[Bitwise.scala 71:12] + node _T_433 = not(sExpX3_13) @[primitives.scala 50:21] + node _T_434 = bits(_T_433, 9, 9) @[primitives.scala 56:25] + node _T_435 = bits(_T_433, 8, 0) @[primitives.scala 57:26] + node _T_436 = bits(_T_435, 8, 8) @[primitives.scala 56:25] + node _T_437 = bits(_T_435, 7, 0) @[primitives.scala 57:26] + node _T_438 = bits(_T_437, 7, 7) @[primitives.scala 56:25] + node _T_439 = bits(_T_437, 6, 0) @[primitives.scala 57:26] + node _T_440 = bits(_T_439, 6, 6) @[primitives.scala 56:25] + node _T_441 = bits(_T_439, 5, 0) @[primitives.scala 57:26] + node _T_444 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_441) @[primitives.scala 68:52] + node _T_445 = bits(_T_444, 63, 43) @[primitives.scala 69:26] + node _T_446 = bits(_T_445, 15, 0) @[Bitwise.scala 108:18] + node _T_449 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 101:47] + node _T_450 = xor(UInt<16>("h0ffff"), _T_449) @[Bitwise.scala 101:21] + node _T_451 = shr(_T_446, 8) @[Bitwise.scala 102:21] + node _T_452 = and(_T_451, _T_450) @[Bitwise.scala 102:31] + node _T_453 = bits(_T_446, 7, 0) @[Bitwise.scala 102:46] + node _T_454 = shl(_T_453, 8) @[Bitwise.scala 102:65] + node _T_455 = not(_T_450) @[Bitwise.scala 102:77] + node _T_456 = and(_T_454, _T_455) @[Bitwise.scala 102:75] + node _T_457 = or(_T_452, _T_456) @[Bitwise.scala 102:39] + node _T_458 = bits(_T_450, 11, 0) @[Bitwise.scala 101:28] + node _T_459 = shl(_T_458, 4) @[Bitwise.scala 101:47] + node _T_460 = xor(_T_450, _T_459) @[Bitwise.scala 101:21] + node _T_461 = shr(_T_457, 4) @[Bitwise.scala 102:21] + node _T_462 = and(_T_461, _T_460) @[Bitwise.scala 102:31] + node _T_463 = bits(_T_457, 11, 0) @[Bitwise.scala 102:46] + node _T_464 = shl(_T_463, 4) @[Bitwise.scala 102:65] + node _T_465 = not(_T_460) @[Bitwise.scala 102:77] + node _T_466 = and(_T_464, _T_465) @[Bitwise.scala 102:75] + node _T_467 = or(_T_462, _T_466) @[Bitwise.scala 102:39] + node _T_468 = bits(_T_460, 13, 0) @[Bitwise.scala 101:28] + node _T_469 = shl(_T_468, 2) @[Bitwise.scala 101:47] + node _T_470 = xor(_T_460, _T_469) @[Bitwise.scala 101:21] + node _T_471 = shr(_T_467, 2) @[Bitwise.scala 102:21] + node _T_472 = and(_T_471, _T_470) @[Bitwise.scala 102:31] + node _T_473 = bits(_T_467, 13, 0) @[Bitwise.scala 102:46] + node _T_474 = shl(_T_473, 2) @[Bitwise.scala 102:65] + node _T_475 = not(_T_470) @[Bitwise.scala 102:77] + node _T_476 = and(_T_474, _T_475) @[Bitwise.scala 102:75] + node _T_477 = or(_T_472, _T_476) @[Bitwise.scala 102:39] + node _T_478 = bits(_T_470, 14, 0) @[Bitwise.scala 101:28] + node _T_479 = shl(_T_478, 1) @[Bitwise.scala 101:47] + node _T_480 = xor(_T_470, _T_479) @[Bitwise.scala 101:21] + node _T_481 = shr(_T_477, 1) @[Bitwise.scala 102:21] + node _T_482 = and(_T_481, _T_480) @[Bitwise.scala 102:31] + node _T_483 = bits(_T_477, 14, 0) @[Bitwise.scala 102:46] + node _T_484 = shl(_T_483, 1) @[Bitwise.scala 102:65] + node _T_485 = not(_T_480) @[Bitwise.scala 102:77] + node _T_486 = and(_T_484, _T_485) @[Bitwise.scala 102:75] + node _T_487 = or(_T_482, _T_486) @[Bitwise.scala 102:39] + node _T_488 = bits(_T_445, 20, 16) @[Bitwise.scala 108:44] + node _T_489 = bits(_T_488, 3, 0) @[Bitwise.scala 108:18] + node _T_490 = bits(_T_489, 1, 0) @[Bitwise.scala 108:18] + node _T_491 = bits(_T_490, 0, 0) @[Bitwise.scala 108:18] + node _T_492 = bits(_T_490, 1, 1) @[Bitwise.scala 108:44] + node _T_493 = cat(_T_491, _T_492) @[Cat.scala 30:58] + node _T_494 = bits(_T_489, 3, 2) @[Bitwise.scala 108:44] + node _T_495 = bits(_T_494, 0, 0) @[Bitwise.scala 108:18] + node _T_496 = bits(_T_494, 1, 1) @[Bitwise.scala 108:44] + node _T_497 = cat(_T_495, _T_496) @[Cat.scala 30:58] + node _T_498 = cat(_T_493, _T_497) @[Cat.scala 30:58] + node _T_499 = bits(_T_488, 4, 4) @[Bitwise.scala 108:44] + node _T_500 = cat(_T_498, _T_499) @[Cat.scala 30:58] + node _T_501 = cat(_T_487, _T_500) @[Cat.scala 30:58] + node _T_502 = not(_T_501) @[primitives.scala 65:36] + node _T_503 = mux(_T_440, UInt<1>("h00"), _T_502) @[primitives.scala 65:21] + node _T_504 = not(_T_503) @[primitives.scala 65:17] + node _T_506 = cat(_T_504, UInt<4>("h0f")) @[Cat.scala 30:58] + node _T_507 = bits(_T_439, 6, 6) @[primitives.scala 56:25] + node _T_508 = bits(_T_439, 5, 0) @[primitives.scala 57:26] + node _T_510 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_508) @[primitives.scala 68:52] + node _T_511 = bits(_T_510, 3, 0) @[primitives.scala 69:26] + node _T_512 = bits(_T_511, 1, 0) @[Bitwise.scala 108:18] + node _T_513 = bits(_T_512, 0, 0) @[Bitwise.scala 108:18] + node _T_514 = bits(_T_512, 1, 1) @[Bitwise.scala 108:44] + node _T_515 = cat(_T_513, _T_514) @[Cat.scala 30:58] + node _T_516 = bits(_T_511, 3, 2) @[Bitwise.scala 108:44] + node _T_517 = bits(_T_516, 0, 0) @[Bitwise.scala 108:18] + node _T_518 = bits(_T_516, 1, 1) @[Bitwise.scala 108:44] + node _T_519 = cat(_T_517, _T_518) @[Cat.scala 30:58] + node _T_520 = cat(_T_515, _T_519) @[Cat.scala 30:58] + node _T_522 = mux(_T_507, _T_520, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_523 = mux(_T_438, _T_506, _T_522) @[primitives.scala 61:20] + node _T_525 = mux(_T_436, _T_523, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_527 = mux(_T_434, _T_525, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_528 = bits(sigX3, 26, 26) @[MulAddRecFN.scala 450:26] + node _T_529 = or(_T_527, _T_528) @[MulAddRecFN.scala 449:75] + node _T_531 = cat(_T_529, UInt<2>("h03")) @[Cat.scala 30:58] + node roundMask = or(_T_432, _T_531) @[MulAddRecFN.scala 448:50] + node _T_532 = shr(roundMask, 1) @[MulAddRecFN.scala 454:35] + node _T_533 = not(_T_532) @[MulAddRecFN.scala 454:24] + node roundPosMask = and(_T_533, roundMask) @[MulAddRecFN.scala 454:40] + node _T_534 = and(sigX3, roundPosMask) @[MulAddRecFN.scala 455:30] + node roundPosBit = neq(_T_534, UInt<1>("h00")) @[MulAddRecFN.scala 455:46] + node _T_536 = shr(roundMask, 1) @[MulAddRecFN.scala 456:45] + node _T_537 = and(sigX3, _T_536) @[MulAddRecFN.scala 456:34] + node anyRoundExtra = neq(_T_537, UInt<1>("h00")) @[MulAddRecFN.scala 456:50] + node _T_539 = not(sigX3) @[MulAddRecFN.scala 457:27] + node _T_540 = shr(roundMask, 1) @[MulAddRecFN.scala 457:45] + node _T_541 = and(_T_539, _T_540) @[MulAddRecFN.scala 457:34] + node allRoundExtra = eq(_T_541, UInt<1>("h00")) @[MulAddRecFN.scala 457:50] + node anyRound = or(roundPosBit, anyRoundExtra) @[MulAddRecFN.scala 458:32] + node allRound = and(roundPosBit, allRoundExtra) @[MulAddRecFN.scala 459:32] + node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) @[MulAddRecFN.scala 460:28] + node _T_544 = eq(doIncrSig, UInt<1>("h00")) @[MulAddRecFN.scala 462:10] + node _T_545 = and(_T_544, roundingMode_nearest_even) @[MulAddRecFN.scala 462:22] + node _T_546 = and(_T_545, roundPosBit) @[MulAddRecFN.scala 462:51] + node _T_547 = and(_T_546, anyRoundExtra) @[MulAddRecFN.scala 463:60] + node _T_549 = eq(doIncrSig, UInt<1>("h00")) @[MulAddRecFN.scala 464:10] + node _T_550 = and(_T_549, roundDirectUp) @[MulAddRecFN.scala 464:22] + node _T_551 = and(_T_550, anyRound) @[MulAddRecFN.scala 464:49] + node _T_552 = or(_T_547, _T_551) @[MulAddRecFN.scala 463:78] + node _T_553 = and(doIncrSig, allRound) @[MulAddRecFN.scala 465:49] + node _T_554 = or(_T_552, _T_553) @[MulAddRecFN.scala 464:65] + node _T_555 = and(doIncrSig, roundingMode_nearest_even) @[MulAddRecFN.scala 466:20] + node _T_556 = and(_T_555, roundPosBit) @[MulAddRecFN.scala 466:49] + node _T_557 = or(_T_554, _T_556) @[MulAddRecFN.scala 465:65] + node _T_558 = and(doIncrSig, roundDirectUp) @[MulAddRecFN.scala 467:20] + node _T_560 = and(_T_558, UInt<1>("h01")) @[MulAddRecFN.scala 467:49] + node roundUp = or(_T_557, _T_560) @[MulAddRecFN.scala 466:65] + node _T_562 = eq(roundPosBit, UInt<1>("h00")) @[MulAddRecFN.scala 470:42] + node _T_563 = and(roundingMode_nearest_even, _T_562) @[MulAddRecFN.scala 470:39] + node _T_564 = and(_T_563, allRoundExtra) @[MulAddRecFN.scala 470:56] + node _T_565 = and(roundingMode_nearest_even, roundPosBit) @[MulAddRecFN.scala 471:39] + node _T_567 = eq(anyRoundExtra, UInt<1>("h00")) @[MulAddRecFN.scala 471:59] + node _T_568 = and(_T_565, _T_567) @[MulAddRecFN.scala 471:56] + node roundEven = mux(doIncrSig, _T_564, _T_568) @[MulAddRecFN.scala 469:12] + node _T_570 = eq(allRound, UInt<1>("h00")) @[MulAddRecFN.scala 473:39] + node inexactY = mux(doIncrSig, _T_570, anyRound) @[MulAddRecFN.scala 473:27] + node _T_571 = or(sigX3, roundMask) @[MulAddRecFN.scala 475:18] + node _T_572 = shr(_T_571, 2) @[MulAddRecFN.scala 475:30] + node _T_574 = add(_T_572, UInt<1>("h01")) @[MulAddRecFN.scala 475:35] + node _T_575 = tail(_T_574, 1) @[MulAddRecFN.scala 475:35] + node roundUp_sigY3 = bits(_T_575, 25, 0) @[MulAddRecFN.scala 475:45] + node _T_577 = eq(roundUp, UInt<1>("h00")) @[MulAddRecFN.scala 477:13] + node _T_579 = eq(roundEven, UInt<1>("h00")) @[MulAddRecFN.scala 477:26] + node _T_580 = and(_T_577, _T_579) @[MulAddRecFN.scala 477:23] + node _T_581 = not(roundMask) @[MulAddRecFN.scala 477:48] + node _T_582 = and(sigX3, _T_581) @[MulAddRecFN.scala 477:46] + node _T_583 = shr(_T_582, 2) @[MulAddRecFN.scala 477:59] + node _T_585 = mux(_T_580, _T_583, UInt<1>("h00")) @[MulAddRecFN.scala 477:12] + node _T_587 = mux(roundUp, roundUp_sigY3, UInt<1>("h00")) @[MulAddRecFN.scala 478:12] + node _T_588 = or(_T_585, _T_587) @[MulAddRecFN.scala 477:79] + node _T_589 = shr(roundMask, 1) @[MulAddRecFN.scala 479:64] + node _T_590 = not(_T_589) @[MulAddRecFN.scala 479:53] + node _T_591 = and(roundUp_sigY3, _T_590) @[MulAddRecFN.scala 479:51] + node _T_593 = mux(roundEven, _T_591, UInt<1>("h00")) @[MulAddRecFN.scala 479:12] + node sigY3 = or(_T_588, _T_593) @[MulAddRecFN.scala 478:79] + node _T_594 = bits(sigY3, 25, 25) @[MulAddRecFN.scala 482:18] + node _T_596 = add(sExpX3, UInt<1>("h01")) @[MulAddRecFN.scala 482:41] + node _T_597 = tail(_T_596, 1) @[MulAddRecFN.scala 482:41] + node _T_599 = mux(_T_594, _T_597, UInt<1>("h00")) @[MulAddRecFN.scala 482:12] + node _T_600 = bits(sigY3, 24, 24) @[MulAddRecFN.scala 483:18] + node _T_602 = mux(_T_600, sExpX3, UInt<1>("h00")) @[MulAddRecFN.scala 483:12] + node _T_603 = or(_T_599, _T_602) @[MulAddRecFN.scala 482:61] + node _T_604 = bits(sigY3, 25, 24) @[MulAddRecFN.scala 484:19] + node _T_606 = eq(_T_604, UInt<1>("h00")) @[MulAddRecFN.scala 484:44] + node _T_608 = sub(sExpX3, UInt<1>("h01")) @[MulAddRecFN.scala 485:20] + node _T_609 = asUInt(_T_608) @[MulAddRecFN.scala 485:20] + node _T_610 = tail(_T_609, 1) @[MulAddRecFN.scala 485:20] + node _T_612 = mux(_T_606, _T_610, UInt<1>("h00")) @[MulAddRecFN.scala 484:12] + node sExpY = or(_T_603, _T_612) @[MulAddRecFN.scala 483:61] + node expY = bits(sExpY, 8, 0) @[MulAddRecFN.scala 488:21] + node _T_613 = bits(sigY3, 22, 0) @[MulAddRecFN.scala 490:31] + node _T_614 = bits(sigY3, 23, 1) @[MulAddRecFN.scala 490:55] + node fractY = mux(sigX3Shift1, _T_613, _T_614) @[MulAddRecFN.scala 490:12] + node _T_615 = bits(sExpY, 9, 7) @[MulAddRecFN.scala 492:27] + node overflowY = eq(_T_615, UInt<2>("h03")) @[MulAddRecFN.scala 492:56] + node _T_618 = eq(isZeroY, UInt<1>("h00")) @[MulAddRecFN.scala 495:9] + node _T_619 = bits(sExpY, 9, 9) @[MulAddRecFN.scala 496:19] + node _T_620 = bits(sExpY, 8, 0) @[MulAddRecFN.scala 496:43] + node _T_622 = lt(_T_620, UInt<7>("h06b")) @[MulAddRecFN.scala 496:57] + node _T_623 = or(_T_619, _T_622) @[MulAddRecFN.scala 496:34] + node totalUnderflowY = and(_T_618, _T_623) @[MulAddRecFN.scala 495:19] + node _T_624 = bits(sExpX3, 10, 10) @[MulAddRecFN.scala 499:20] + node _T_627 = mux(sigX3Shift1, UInt<8>("h082"), UInt<8>("h081")) @[MulAddRecFN.scala 501:26] + node _T_628 = leq(sExpX3_13, _T_627) @[MulAddRecFN.scala 500:29] + node _T_629 = or(_T_624, _T_628) @[MulAddRecFN.scala 499:35] + node underflowY = and(inexactY, _T_629) @[MulAddRecFN.scala 498:22] + node _T_630 = and(roundingMode_min, signY) @[MulAddRecFN.scala 506:27] + node _T_632 = eq(signY, UInt<1>("h00")) @[MulAddRecFN.scala 506:61] + node _T_633 = and(roundingMode_max, _T_632) @[MulAddRecFN.scala 506:58] + node roundMagUp = or(_T_630, _T_633) @[MulAddRecFN.scala 506:37] + node overflowY_roundMagUp = or(roundingMode_nearest_even, roundMagUp) @[MulAddRecFN.scala 507:58] + node mulSpecial = or(isSpecialA, isSpecialB) @[MulAddRecFN.scala 511:33] + node addSpecial = or(mulSpecial, isSpecialC) @[MulAddRecFN.scala 512:33] + node notSpecial_addZeros = and(io.fromPreMul.isZeroProd, isZeroC) @[MulAddRecFN.scala 513:56] + node _T_635 = eq(addSpecial, UInt<1>("h00")) @[MulAddRecFN.scala 514:22] + node _T_637 = eq(notSpecial_addZeros, UInt<1>("h00")) @[MulAddRecFN.scala 514:38] + node commonCase = and(_T_635, _T_637) @[MulAddRecFN.scala 514:35] + node _T_638 = and(isInfA, isZeroB) @[MulAddRecFN.scala 517:17] + node _T_639 = and(isZeroA, isInfB) @[MulAddRecFN.scala 517:41] + node _T_640 = or(_T_638, _T_639) @[MulAddRecFN.scala 517:29] + node _T_642 = eq(isNaNA, UInt<1>("h00")) @[MulAddRecFN.scala 518:14] + node _T_644 = eq(isNaNB, UInt<1>("h00")) @[MulAddRecFN.scala 518:26] + node _T_645 = and(_T_642, _T_644) @[MulAddRecFN.scala 518:23] + node _T_646 = or(isInfA, isInfB) @[MulAddRecFN.scala 518:46] + node _T_647 = and(_T_645, _T_646) @[MulAddRecFN.scala 518:35] + node _T_648 = and(_T_647, isInfC) @[MulAddRecFN.scala 518:57] + node _T_649 = and(_T_648, doSubMags) @[MulAddRecFN.scala 518:67] + node notSigNaN_invalid = or(_T_640, _T_649) @[MulAddRecFN.scala 517:52] + node _T_650 = or(isSigNaNA, isSigNaNB) @[MulAddRecFN.scala 519:29] + node _T_651 = or(_T_650, isSigNaNC) @[MulAddRecFN.scala 519:42] + node invalid = or(_T_651, notSigNaN_invalid) @[MulAddRecFN.scala 519:55] + node overflow = and(commonCase, overflowY) @[MulAddRecFN.scala 520:32] + node underflow = and(commonCase, underflowY) @[MulAddRecFN.scala 521:32] + node _T_652 = and(commonCase, inexactY) @[MulAddRecFN.scala 522:43] + node inexact = or(overflow, _T_652) @[MulAddRecFN.scala 522:28] + node _T_653 = or(notSpecial_addZeros, isZeroY) @[MulAddRecFN.scala 525:29] + node notSpecial_isZeroOut = or(_T_653, totalUnderflowY) @[MulAddRecFN.scala 525:40] + node _T_654 = and(commonCase, totalUnderflowY) @[MulAddRecFN.scala 526:41] + node pegMinFiniteMagOut = and(_T_654, roundMagUp) @[MulAddRecFN.scala 526:60] + node _T_656 = eq(overflowY_roundMagUp, UInt<1>("h00")) @[MulAddRecFN.scala 527:42] + node pegMaxFiniteMagOut = and(overflow, _T_656) @[MulAddRecFN.scala 527:39] + node _T_657 = or(isInfA, isInfB) @[MulAddRecFN.scala 529:16] + node _T_658 = or(_T_657, isInfC) @[MulAddRecFN.scala 529:26] + node _T_659 = and(overflow, overflowY_roundMagUp) @[MulAddRecFN.scala 529:49] + node notNaN_isInfOut = or(_T_658, _T_659) @[MulAddRecFN.scala 529:36] + node _T_660 = or(isNaNA, isNaNB) @[MulAddRecFN.scala 530:27] + node _T_661 = or(_T_660, isNaNC) @[MulAddRecFN.scala 530:37] + node isNaNOut = or(_T_661, notSigNaN_invalid) @[MulAddRecFN.scala 530:47] + node _T_663 = eq(doSubMags, UInt<1>("h00")) @[MulAddRecFN.scala 533:10] + node _T_664 = and(_T_663, io.fromPreMul.opSignC) @[MulAddRecFN.scala 533:51] + node _T_666 = eq(isSpecialC, UInt<1>("h00")) @[MulAddRecFN.scala 534:24] + node _T_667 = and(mulSpecial, _T_666) @[MulAddRecFN.scala 534:21] + node _T_668 = and(_T_667, io.fromPreMul.signProd) @[MulAddRecFN.scala 534:51] + node _T_669 = or(_T_664, _T_668) @[MulAddRecFN.scala 533:78] + node _T_671 = eq(mulSpecial, UInt<1>("h00")) @[MulAddRecFN.scala 535:10] + node _T_672 = and(_T_671, isSpecialC) @[MulAddRecFN.scala 535:23] + node _T_673 = and(_T_672, io.fromPreMul.opSignC) @[MulAddRecFN.scala 535:51] + node _T_674 = or(_T_669, _T_673) @[MulAddRecFN.scala 534:78] + node _T_676 = eq(mulSpecial, UInt<1>("h00")) @[MulAddRecFN.scala 536:10] + node _T_677 = and(_T_676, notSpecial_addZeros) @[MulAddRecFN.scala 536:23] + node _T_678 = and(_T_677, doSubMags) @[MulAddRecFN.scala 536:46] + node _T_679 = and(_T_678, signZeroNotEqOpSigns) @[MulAddRecFN.scala 536:59] + node uncommonCaseSignOut = or(_T_674, _T_679) @[MulAddRecFN.scala 535:78] + node _T_681 = eq(isNaNOut, UInt<1>("h00")) @[MulAddRecFN.scala 538:20] + node _T_682 = and(_T_681, uncommonCaseSignOut) @[MulAddRecFN.scala 538:31] + node _T_683 = and(commonCase, signY) @[MulAddRecFN.scala 538:70] + node signOut = or(_T_682, _T_683) @[MulAddRecFN.scala 538:55] + node _T_686 = mux(notSpecial_isZeroOut, UInt<9>("h01c0"), UInt<9>("h00")) @[MulAddRecFN.scala 541:18] + node _T_687 = not(_T_686) @[MulAddRecFN.scala 541:14] + node _T_688 = and(expY, _T_687) @[MulAddRecFN.scala 540:15] + node _T_690 = not(UInt<9>("h06b")) @[MulAddRecFN.scala 546:19] + node _T_692 = mux(pegMinFiniteMagOut, _T_690, UInt<9>("h00")) @[MulAddRecFN.scala 545:18] + node _T_693 = not(_T_692) @[MulAddRecFN.scala 545:14] + node _T_694 = and(_T_688, _T_693) @[MulAddRecFN.scala 544:17] + node _T_697 = mux(pegMaxFiniteMagOut, UInt<9>("h080"), UInt<9>("h00")) @[MulAddRecFN.scala 549:18] + node _T_698 = not(_T_697) @[MulAddRecFN.scala 549:14] + node _T_699 = and(_T_694, _T_698) @[MulAddRecFN.scala 548:17] + node _T_702 = mux(notNaN_isInfOut, UInt<7>("h040"), UInt<9>("h00")) @[MulAddRecFN.scala 553:18] + node _T_703 = not(_T_702) @[MulAddRecFN.scala 553:14] + node _T_704 = and(_T_699, _T_703) @[MulAddRecFN.scala 552:17] + node _T_707 = mux(pegMinFiniteMagOut, UInt<7>("h06b"), UInt<9>("h00")) @[MulAddRecFN.scala 557:16] + node _T_708 = or(_T_704, _T_707) @[MulAddRecFN.scala 556:18] + node _T_711 = mux(pegMaxFiniteMagOut, UInt<9>("h017f"), UInt<9>("h00")) @[MulAddRecFN.scala 558:16] + node _T_712 = or(_T_708, _T_711) @[MulAddRecFN.scala 557:74] + node _T_715 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<9>("h00")) @[MulAddRecFN.scala 562:16] + node _T_716 = or(_T_712, _T_715) @[MulAddRecFN.scala 561:15] + node _T_719 = mux(isNaNOut, UInt<9>("h01c0"), UInt<9>("h00")) @[MulAddRecFN.scala 566:16] + node expOut = or(_T_716, _T_719) @[MulAddRecFN.scala 565:15] + node _T_720 = and(totalUnderflowY, roundMagUp) @[MulAddRecFN.scala 568:30] + node _T_721 = or(_T_720, isNaNOut) @[MulAddRecFN.scala 568:45] + node _T_723 = shl(UInt<1>("h01"), 22) @[MulAddRecFN.scala 569:34] + node _T_725 = mux(isNaNOut, _T_723, UInt<1>("h00")) @[MulAddRecFN.scala 569:16] + node _T_726 = mux(_T_721, _T_725, fractY) @[MulAddRecFN.scala 568:12] + node _T_727 = bits(pegMaxFiniteMagOut, 0, 0) @[Bitwise.scala 71:15] + node _T_730 = mux(_T_727, UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 71:12] + node fractOut = or(_T_726, _T_730) @[MulAddRecFN.scala 571:11] + node _T_731 = cat(signOut, expOut) @[Cat.scala 30:58] + node _T_732 = cat(_T_731, fractOut) @[Cat.scala 30:58] + io.out <= _T_732 @[MulAddRecFN.scala 574:12] + node _T_734 = cat(underflow, inexact) @[Cat.scala 30:58] + node _T_735 = cat(invalid, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_736 = cat(_T_735, overflow) @[Cat.scala 30:58] + node _T_737 = cat(_T_736, _T_734) @[Cat.scala 30:58] + io.exceptionFlags <= _T_737 @[MulAddRecFN.scala 575:23] + + module RoundRawFNToRecFN : + input clock : Clock + input reset : UInt<1> + output io : {flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + node roundingMode_nearest_even = eq(io.roundingMode, UInt<2>("h00")) @[RoundRawFNToRecFN.scala 88:54] + node roundingMode_minMag = eq(io.roundingMode, UInt<2>("h01")) @[RoundRawFNToRecFN.scala 89:54] + node roundingMode_min = eq(io.roundingMode, UInt<2>("h02")) @[RoundRawFNToRecFN.scala 90:54] + node roundingMode_max = eq(io.roundingMode, UInt<2>("h03")) @[RoundRawFNToRecFN.scala 91:54] + node _T_26 = and(roundingMode_min, io.in.sign) @[RoundRawFNToRecFN.scala 94:27] + node _T_28 = eq(io.in.sign, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 94:66] + node _T_29 = and(roundingMode_max, _T_28) @[RoundRawFNToRecFN.scala 94:63] + node roundMagUp = or(_T_26, _T_29) @[RoundRawFNToRecFN.scala 94:42] + node doShiftSigDown1 = bits(io.in.sig, 26, 26) @[RoundRawFNToRecFN.scala 98:36] + node isNegExp = lt(io.in.sExp, asSInt(UInt<1>("h00"))) @[RoundRawFNToRecFN.scala 99:32] + node _T_31 = bits(isNegExp, 0, 0) @[Bitwise.scala 71:15] + node _T_34 = mux(_T_31, UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 71:12] + node _T_35 = bits(io.in.sExp, 8, 0) @[RoundRawFNToRecFN.scala 103:31] + node _T_36 = not(_T_35) @[primitives.scala 50:21] + node _T_37 = bits(_T_36, 8, 8) @[primitives.scala 56:25] + node _T_38 = bits(_T_36, 7, 0) @[primitives.scala 57:26] + node _T_39 = bits(_T_38, 7, 7) @[primitives.scala 56:25] + node _T_40 = bits(_T_38, 6, 0) @[primitives.scala 57:26] + node _T_41 = bits(_T_40, 6, 6) @[primitives.scala 56:25] + node _T_42 = bits(_T_40, 5, 0) @[primitives.scala 57:26] + node _T_45 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_42) @[primitives.scala 68:52] + node _T_46 = bits(_T_45, 63, 42) @[primitives.scala 69:26] + node _T_47 = bits(_T_46, 15, 0) @[Bitwise.scala 108:18] + node _T_50 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 101:47] + node _T_51 = xor(UInt<16>("h0ffff"), _T_50) @[Bitwise.scala 101:21] + node _T_52 = shr(_T_47, 8) @[Bitwise.scala 102:21] + node _T_53 = and(_T_52, _T_51) @[Bitwise.scala 102:31] + node _T_54 = bits(_T_47, 7, 0) @[Bitwise.scala 102:46] + node _T_55 = shl(_T_54, 8) @[Bitwise.scala 102:65] + node _T_56 = not(_T_51) @[Bitwise.scala 102:77] + node _T_57 = and(_T_55, _T_56) @[Bitwise.scala 102:75] + node _T_58 = or(_T_53, _T_57) @[Bitwise.scala 102:39] + node _T_59 = bits(_T_51, 11, 0) @[Bitwise.scala 101:28] + node _T_60 = shl(_T_59, 4) @[Bitwise.scala 101:47] + node _T_61 = xor(_T_51, _T_60) @[Bitwise.scala 101:21] + node _T_62 = shr(_T_58, 4) @[Bitwise.scala 102:21] + node _T_63 = and(_T_62, _T_61) @[Bitwise.scala 102:31] + node _T_64 = bits(_T_58, 11, 0) @[Bitwise.scala 102:46] + node _T_65 = shl(_T_64, 4) @[Bitwise.scala 102:65] + node _T_66 = not(_T_61) @[Bitwise.scala 102:77] + node _T_67 = and(_T_65, _T_66) @[Bitwise.scala 102:75] + node _T_68 = or(_T_63, _T_67) @[Bitwise.scala 102:39] + node _T_69 = bits(_T_61, 13, 0) @[Bitwise.scala 101:28] + node _T_70 = shl(_T_69, 2) @[Bitwise.scala 101:47] + node _T_71 = xor(_T_61, _T_70) @[Bitwise.scala 101:21] + node _T_72 = shr(_T_68, 2) @[Bitwise.scala 102:21] + node _T_73 = and(_T_72, _T_71) @[Bitwise.scala 102:31] + node _T_74 = bits(_T_68, 13, 0) @[Bitwise.scala 102:46] + node _T_75 = shl(_T_74, 2) @[Bitwise.scala 102:65] + node _T_76 = not(_T_71) @[Bitwise.scala 102:77] + node _T_77 = and(_T_75, _T_76) @[Bitwise.scala 102:75] + node _T_78 = or(_T_73, _T_77) @[Bitwise.scala 102:39] + node _T_79 = bits(_T_71, 14, 0) @[Bitwise.scala 101:28] + node _T_80 = shl(_T_79, 1) @[Bitwise.scala 101:47] + node _T_81 = xor(_T_71, _T_80) @[Bitwise.scala 101:21] + node _T_82 = shr(_T_78, 1) @[Bitwise.scala 102:21] + node _T_83 = and(_T_82, _T_81) @[Bitwise.scala 102:31] + node _T_84 = bits(_T_78, 14, 0) @[Bitwise.scala 102:46] + node _T_85 = shl(_T_84, 1) @[Bitwise.scala 102:65] + node _T_86 = not(_T_81) @[Bitwise.scala 102:77] + node _T_87 = and(_T_85, _T_86) @[Bitwise.scala 102:75] + node _T_88 = or(_T_83, _T_87) @[Bitwise.scala 102:39] + node _T_89 = bits(_T_46, 21, 16) @[Bitwise.scala 108:44] + node _T_90 = bits(_T_89, 3, 0) @[Bitwise.scala 108:18] + node _T_91 = bits(_T_90, 1, 0) @[Bitwise.scala 108:18] + node _T_92 = bits(_T_91, 0, 0) @[Bitwise.scala 108:18] + node _T_93 = bits(_T_91, 1, 1) @[Bitwise.scala 108:44] + node _T_94 = cat(_T_92, _T_93) @[Cat.scala 30:58] + node _T_95 = bits(_T_90, 3, 2) @[Bitwise.scala 108:44] + node _T_96 = bits(_T_95, 0, 0) @[Bitwise.scala 108:18] + node _T_97 = bits(_T_95, 1, 1) @[Bitwise.scala 108:44] + node _T_98 = cat(_T_96, _T_97) @[Cat.scala 30:58] + node _T_99 = cat(_T_94, _T_98) @[Cat.scala 30:58] + node _T_100 = bits(_T_89, 5, 4) @[Bitwise.scala 108:44] + node _T_101 = bits(_T_100, 0, 0) @[Bitwise.scala 108:18] + node _T_102 = bits(_T_100, 1, 1) @[Bitwise.scala 108:44] + node _T_103 = cat(_T_101, _T_102) @[Cat.scala 30:58] + node _T_104 = cat(_T_99, _T_103) @[Cat.scala 30:58] + node _T_105 = cat(_T_88, _T_104) @[Cat.scala 30:58] + node _T_106 = not(_T_105) @[primitives.scala 65:36] + node _T_107 = mux(_T_41, UInt<1>("h00"), _T_106) @[primitives.scala 65:21] + node _T_108 = not(_T_107) @[primitives.scala 65:17] + node _T_110 = cat(_T_108, UInt<3>("h07")) @[Cat.scala 30:58] + node _T_111 = bits(_T_40, 6, 6) @[primitives.scala 56:25] + node _T_112 = bits(_T_40, 5, 0) @[primitives.scala 57:26] + node _T_114 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_112) @[primitives.scala 68:52] + node _T_115 = bits(_T_114, 2, 0) @[primitives.scala 69:26] + node _T_116 = bits(_T_115, 1, 0) @[Bitwise.scala 108:18] + node _T_117 = bits(_T_116, 0, 0) @[Bitwise.scala 108:18] + node _T_118 = bits(_T_116, 1, 1) @[Bitwise.scala 108:44] + node _T_119 = cat(_T_117, _T_118) @[Cat.scala 30:58] + node _T_120 = bits(_T_115, 2, 2) @[Bitwise.scala 108:44] + node _T_121 = cat(_T_119, _T_120) @[Cat.scala 30:58] + node _T_123 = mux(_T_111, _T_121, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_124 = mux(_T_39, _T_110, _T_123) @[primitives.scala 61:20] + node _T_126 = mux(_T_37, _T_124, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_127 = or(_T_34, _T_126) @[RoundRawFNToRecFN.scala 101:42] + node _T_128 = or(_T_127, doShiftSigDown1) @[RoundRawFNToRecFN.scala 106:19] + node roundMask = cat(_T_128, UInt<2>("h03")) @[Cat.scala 30:58] + node _T_130 = cat(isNegExp, roundMask) @[Cat.scala 30:58] + node shiftedRoundMask = shr(_T_130, 1) @[RoundRawFNToRecFN.scala 109:52] + node _T_131 = not(shiftedRoundMask) @[RoundRawFNToRecFN.scala 110:24] + node roundPosMask = and(_T_131, roundMask) @[RoundRawFNToRecFN.scala 110:42] + node _T_132 = and(io.in.sig, roundPosMask) @[RoundRawFNToRecFN.scala 111:34] + node roundPosBit = neq(_T_132, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 111:50] + node _T_134 = and(io.in.sig, shiftedRoundMask) @[RoundRawFNToRecFN.scala 112:36] + node anyRoundExtra = neq(_T_134, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 112:56] + node anyRound = or(roundPosBit, anyRoundExtra) @[RoundRawFNToRecFN.scala 113:32] + node _T_136 = and(roundingMode_nearest_even, roundPosBit) @[RoundRawFNToRecFN.scala 116:40] + node _T_137 = and(roundMagUp, anyRound) @[RoundRawFNToRecFN.scala 117:29] + node _T_138 = or(_T_136, _T_137) @[RoundRawFNToRecFN.scala 116:56] + node _T_139 = or(io.in.sig, roundMask) @[RoundRawFNToRecFN.scala 118:26] + node _T_140 = shr(_T_139, 2) @[RoundRawFNToRecFN.scala 118:38] + node _T_142 = add(_T_140, UInt<1>("h01")) @[RoundRawFNToRecFN.scala 118:43] + node _T_143 = and(roundingMode_nearest_even, roundPosBit) @[RoundRawFNToRecFN.scala 119:48] + node _T_145 = eq(anyRoundExtra, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 120:26] + node _T_146 = and(_T_143, _T_145) @[RoundRawFNToRecFN.scala 119:63] + node _T_147 = shr(roundMask, 1) @[RoundRawFNToRecFN.scala 121:31] + node _T_149 = mux(_T_146, _T_147, UInt<26>("h00")) @[RoundRawFNToRecFN.scala 119:21] + node _T_150 = not(_T_149) @[RoundRawFNToRecFN.scala 119:17] + node _T_151 = and(_T_142, _T_150) @[RoundRawFNToRecFN.scala 118:55] + node _T_152 = not(roundMask) @[RoundRawFNToRecFN.scala 124:26] + node _T_153 = and(io.in.sig, _T_152) @[RoundRawFNToRecFN.scala 124:24] + node _T_154 = shr(_T_153, 2) @[RoundRawFNToRecFN.scala 124:37] + node roundedSig = mux(_T_138, _T_151, _T_154) @[RoundRawFNToRecFN.scala 116:12] + node _T_155 = shr(roundedSig, 24) @[RoundRawFNToRecFN.scala 127:48] + node _T_156 = cvt(_T_155) @[RoundRawFNToRecFN.scala 127:60] + node sRoundedExp = add(io.in.sExp, _T_156) @[RoundRawFNToRecFN.scala 127:34] + node common_expOut = bits(sRoundedExp, 8, 0) @[RoundRawFNToRecFN.scala 129:36] + node _T_157 = bits(roundedSig, 23, 1) @[RoundRawFNToRecFN.scala 132:23] + node _T_158 = bits(roundedSig, 22, 0) @[RoundRawFNToRecFN.scala 133:23] + node common_fractOut = mux(doShiftSigDown1, _T_157, _T_158) @[RoundRawFNToRecFN.scala 131:12] + node _T_159 = shr(sRoundedExp, 7) @[RoundRawFNToRecFN.scala 136:39] + node common_overflow = geq(_T_159, asSInt(UInt<3>("h03"))) @[RoundRawFNToRecFN.scala 136:56] + node common_totalUnderflow = lt(sRoundedExp, asSInt(UInt<8>("h06b"))) @[RoundRawFNToRecFN.scala 138:46] + node _T_164 = mux(doShiftSigDown1, asSInt(UInt<9>("h081")), asSInt(UInt<9>("h082"))) @[RoundRawFNToRecFN.scala 142:21] + node _T_165 = lt(io.in.sExp, _T_164) @[RoundRawFNToRecFN.scala 141:25] + node common_underflow = and(anyRound, _T_165) @[RoundRawFNToRecFN.scala 140:18] + node isNaNOut = or(io.invalidExc, io.in.isNaN) @[RoundRawFNToRecFN.scala 147:34] + node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) @[RoundRawFNToRecFN.scala 148:49] + node _T_167 = eq(isNaNOut, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 149:22] + node _T_169 = eq(notNaN_isSpecialInfOut, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 149:36] + node _T_170 = and(_T_167, _T_169) @[RoundRawFNToRecFN.scala 149:33] + node _T_172 = eq(io.in.isZero, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 149:64] + node commonCase = and(_T_170, _T_172) @[RoundRawFNToRecFN.scala 149:61] + node overflow = and(commonCase, common_overflow) @[RoundRawFNToRecFN.scala 150:32] + node underflow = and(commonCase, common_underflow) @[RoundRawFNToRecFN.scala 151:32] + node _T_173 = and(commonCase, anyRound) @[RoundRawFNToRecFN.scala 152:43] + node inexact = or(overflow, _T_173) @[RoundRawFNToRecFN.scala 152:28] + node overflow_roundMagUp = or(roundingMode_nearest_even, roundMagUp) @[RoundRawFNToRecFN.scala 154:57] + node _T_174 = and(commonCase, common_totalUnderflow) @[RoundRawFNToRecFN.scala 155:42] + node pegMinNonzeroMagOut = and(_T_174, roundMagUp) @[RoundRawFNToRecFN.scala 155:67] + node _T_175 = and(commonCase, overflow) @[RoundRawFNToRecFN.scala 156:41] + node _T_177 = eq(overflow_roundMagUp, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 156:56] + node pegMaxFiniteMagOut = and(_T_175, _T_177) @[RoundRawFNToRecFN.scala 156:53] + node _T_178 = and(overflow, overflow_roundMagUp) @[RoundRawFNToRecFN.scala 158:45] + node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _T_178) @[RoundRawFNToRecFN.scala 158:32] + node signOut = mux(isNaNOut, UInt<1>("h00"), io.in.sign) @[RoundRawFNToRecFN.scala 160:22] + node _T_180 = or(io.in.isZero, common_totalUnderflow) @[RoundRawFNToRecFN.scala 163:32] + node _T_183 = mux(_T_180, UInt<9>("h01c0"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 163:18] + node _T_184 = not(_T_183) @[RoundRawFNToRecFN.scala 163:14] + node _T_185 = and(common_expOut, _T_184) @[RoundRawFNToRecFN.scala 162:24] + node _T_187 = not(UInt<9>("h06b")) @[RoundRawFNToRecFN.scala 168:19] + node _T_189 = mux(pegMinNonzeroMagOut, _T_187, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 167:18] + node _T_190 = not(_T_189) @[RoundRawFNToRecFN.scala 167:14] + node _T_191 = and(_T_185, _T_190) @[RoundRawFNToRecFN.scala 166:17] + node _T_194 = mux(pegMaxFiniteMagOut, UInt<9>("h080"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 171:18] + node _T_195 = not(_T_194) @[RoundRawFNToRecFN.scala 171:14] + node _T_196 = and(_T_191, _T_195) @[RoundRawFNToRecFN.scala 170:17] + node _T_199 = mux(notNaN_isInfOut, UInt<9>("h040"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 175:18] + node _T_200 = not(_T_199) @[RoundRawFNToRecFN.scala 175:14] + node _T_201 = and(_T_196, _T_200) @[RoundRawFNToRecFN.scala 174:17] + node _T_204 = mux(pegMinNonzeroMagOut, UInt<9>("h06b"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 179:16] + node _T_205 = or(_T_201, _T_204) @[RoundRawFNToRecFN.scala 178:18] + node _T_208 = mux(pegMaxFiniteMagOut, UInt<9>("h017f"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 183:16] + node _T_209 = or(_T_205, _T_208) @[RoundRawFNToRecFN.scala 182:15] + node _T_212 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 187:16] + node _T_213 = or(_T_209, _T_212) @[RoundRawFNToRecFN.scala 186:15] + node _T_216 = mux(isNaNOut, UInt<9>("h01c0"), UInt<1>("h00")) @[RoundRawFNToRecFN.scala 188:16] + node expOut = or(_T_213, _T_216) @[RoundRawFNToRecFN.scala 187:71] + node _T_217 = or(common_totalUnderflow, isNaNOut) @[RoundRawFNToRecFN.scala 190:35] + node _T_219 = shl(UInt<1>("h01"), 22) @[RoundRawFNToRecFN.scala 191:34] + node _T_221 = mux(isNaNOut, _T_219, UInt<1>("h00")) @[RoundRawFNToRecFN.scala 191:16] + node _T_222 = mux(_T_217, _T_221, common_fractOut) @[RoundRawFNToRecFN.scala 190:12] + node _T_223 = bits(pegMaxFiniteMagOut, 0, 0) @[Bitwise.scala 71:15] + node _T_226 = mux(_T_223, UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 71:12] + node fractOut = or(_T_222, _T_226) @[RoundRawFNToRecFN.scala 193:11] + node _T_227 = cat(signOut, expOut) @[Cat.scala 30:58] + node _T_228 = cat(_T_227, fractOut) @[Cat.scala 30:58] + io.out <= _T_228 @[RoundRawFNToRecFN.scala 196:12] + node _T_229 = cat(underflow, inexact) @[Cat.scala 30:58] + node _T_230 = cat(io.invalidExc, io.infiniteExc) @[Cat.scala 30:58] + node _T_231 = cat(_T_230, overflow) @[Cat.scala 30:58] + node _T_232 = cat(_T_231, _T_229) @[Cat.scala 30:58] + io.exceptionFlags <= _T_232 @[RoundRawFNToRecFN.scala 197:23] + + module MulAddRecFN_preMul_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<2>, mulAddA : UInt<53>, mulAddB : UInt<53>, mulAddC : UInt<106>, toPostMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<8>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<55>, sExpSum : UInt<14>, roundingMode : UInt<2>}} + + io is invalid + io is invalid + node signA = bits(io.a, 64, 64) @[MulAddRecFN.scala 102:22] + node expA = bits(io.a, 63, 52) @[MulAddRecFN.scala 103:22] + node fractA = bits(io.a, 51, 0) @[MulAddRecFN.scala 104:22] + node _T_52 = bits(expA, 11, 9) @[MulAddRecFN.scala 105:24] + node isZeroA = eq(_T_52, UInt<1>("h00")) @[MulAddRecFN.scala 105:49] + node _T_55 = eq(isZeroA, UInt<1>("h00")) @[MulAddRecFN.scala 106:20] + node sigA = cat(_T_55, fractA) @[Cat.scala 30:58] + node signB = bits(io.b, 64, 64) @[MulAddRecFN.scala 108:22] + node expB = bits(io.b, 63, 52) @[MulAddRecFN.scala 109:22] + node fractB = bits(io.b, 51, 0) @[MulAddRecFN.scala 110:22] + node _T_56 = bits(expB, 11, 9) @[MulAddRecFN.scala 111:24] + node isZeroB = eq(_T_56, UInt<1>("h00")) @[MulAddRecFN.scala 111:49] + node _T_59 = eq(isZeroB, UInt<1>("h00")) @[MulAddRecFN.scala 112:20] + node sigB = cat(_T_59, fractB) @[Cat.scala 30:58] + node _T_60 = bits(io.c, 64, 64) @[MulAddRecFN.scala 114:23] + node _T_61 = bits(io.op, 0, 0) @[MulAddRecFN.scala 114:52] + node opSignC = xor(_T_60, _T_61) @[MulAddRecFN.scala 114:45] + node expC = bits(io.c, 63, 52) @[MulAddRecFN.scala 115:22] + node fractC = bits(io.c, 51, 0) @[MulAddRecFN.scala 116:22] + node _T_62 = bits(expC, 11, 9) @[MulAddRecFN.scala 117:24] + node isZeroC = eq(_T_62, UInt<1>("h00")) @[MulAddRecFN.scala 117:49] + node _T_65 = eq(isZeroC, UInt<1>("h00")) @[MulAddRecFN.scala 118:20] + node sigC = cat(_T_65, fractC) @[Cat.scala 30:58] + node _T_66 = xor(signA, signB) @[MulAddRecFN.scala 122:26] + node _T_67 = bits(io.op, 1, 1) @[MulAddRecFN.scala 122:41] + node signProd = xor(_T_66, _T_67) @[MulAddRecFN.scala 122:34] + node isZeroProd = or(isZeroA, isZeroB) @[MulAddRecFN.scala 123:30] + node _T_68 = bits(expB, 11, 11) @[MulAddRecFN.scala 125:34] + node _T_70 = eq(_T_68, UInt<1>("h00")) @[MulAddRecFN.scala 125:28] + node _T_71 = bits(_T_70, 0, 0) @[Bitwise.scala 71:15] + node _T_74 = mux(_T_71, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 71:12] + node _T_75 = bits(expB, 10, 0) @[MulAddRecFN.scala 125:51] + node _T_76 = cat(_T_74, _T_75) @[Cat.scala 30:58] + node _T_77 = add(expA, _T_76) @[MulAddRecFN.scala 125:14] + node _T_78 = tail(_T_77, 1) @[MulAddRecFN.scala 125:14] + node _T_80 = add(_T_78, UInt<6>("h038")) @[MulAddRecFN.scala 125:70] + node sExpAlignedProd = tail(_T_80, 1) @[MulAddRecFN.scala 125:70] + node doSubMags = xor(signProd, opSignC) @[MulAddRecFN.scala 130:30] + node _T_81 = sub(sExpAlignedProd, expC) @[MulAddRecFN.scala 132:42] + node _T_82 = asUInt(_T_81) @[MulAddRecFN.scala 132:42] + node sNatCAlignDist = tail(_T_82, 1) @[MulAddRecFN.scala 132:42] + node _T_83 = bits(sNatCAlignDist, 13, 13) @[MulAddRecFN.scala 133:56] + node CAlignDist_floor = or(isZeroProd, _T_83) @[MulAddRecFN.scala 133:39] + node _T_84 = bits(sNatCAlignDist, 12, 0) @[MulAddRecFN.scala 135:44] + node _T_86 = eq(_T_84, UInt<1>("h00")) @[MulAddRecFN.scala 135:62] + node CAlignDist_0 = or(CAlignDist_floor, _T_86) @[MulAddRecFN.scala 135:26] + node _T_88 = eq(isZeroC, UInt<1>("h00")) @[MulAddRecFN.scala 137:9] + node _T_89 = bits(sNatCAlignDist, 12, 0) @[MulAddRecFN.scala 139:33] + node _T_91 = lt(_T_89, UInt<6>("h036")) @[MulAddRecFN.scala 139:51] + node _T_92 = or(CAlignDist_floor, _T_91) @[MulAddRecFN.scala 138:31] + node isCDominant = and(_T_88, _T_92) @[MulAddRecFN.scala 137:19] + node _T_94 = bits(sNatCAlignDist, 12, 0) @[MulAddRecFN.scala 143:31] + node _T_96 = lt(_T_94, UInt<8>("h0a1")) @[MulAddRecFN.scala 143:49] + node _T_97 = bits(sNatCAlignDist, 7, 0) @[MulAddRecFN.scala 144:31] + node _T_99 = mux(_T_96, _T_97, UInt<8>("h0a1")) @[MulAddRecFN.scala 143:16] + node CAlignDist = mux(CAlignDist_floor, UInt<1>("h00"), _T_99) @[MulAddRecFN.scala 141:12] + node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) @[MulAddRecFN.scala 148:22] + node _T_100 = bits(CAlignDist, 7, 7) @[primitives.scala 56:25] + node _T_101 = bits(CAlignDist, 6, 0) @[primitives.scala 57:26] + node _T_102 = bits(_T_101, 6, 6) @[primitives.scala 56:25] + node _T_103 = bits(_T_101, 5, 0) @[primitives.scala 57:26] + node _T_106 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_103) @[primitives.scala 68:52] + node _T_107 = bits(_T_106, 63, 31) @[primitives.scala 69:26] + node _T_108 = bits(_T_107, 31, 0) @[Bitwise.scala 108:18] + node _T_111 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 101:47] + node _T_112 = xor(UInt<32>("h0ffffffff"), _T_111) @[Bitwise.scala 101:21] + node _T_113 = shr(_T_108, 16) @[Bitwise.scala 102:21] + node _T_114 = and(_T_113, _T_112) @[Bitwise.scala 102:31] + node _T_115 = bits(_T_108, 15, 0) @[Bitwise.scala 102:46] + node _T_116 = shl(_T_115, 16) @[Bitwise.scala 102:65] + node _T_117 = not(_T_112) @[Bitwise.scala 102:77] + node _T_118 = and(_T_116, _T_117) @[Bitwise.scala 102:75] + node _T_119 = or(_T_114, _T_118) @[Bitwise.scala 102:39] + node _T_120 = bits(_T_112, 23, 0) @[Bitwise.scala 101:28] + node _T_121 = shl(_T_120, 8) @[Bitwise.scala 101:47] + node _T_122 = xor(_T_112, _T_121) @[Bitwise.scala 101:21] + node _T_123 = shr(_T_119, 8) @[Bitwise.scala 102:21] + node _T_124 = and(_T_123, _T_122) @[Bitwise.scala 102:31] + node _T_125 = bits(_T_119, 23, 0) @[Bitwise.scala 102:46] + node _T_126 = shl(_T_125, 8) @[Bitwise.scala 102:65] + node _T_127 = not(_T_122) @[Bitwise.scala 102:77] + node _T_128 = and(_T_126, _T_127) @[Bitwise.scala 102:75] + node _T_129 = or(_T_124, _T_128) @[Bitwise.scala 102:39] + node _T_130 = bits(_T_122, 27, 0) @[Bitwise.scala 101:28] + node _T_131 = shl(_T_130, 4) @[Bitwise.scala 101:47] + node _T_132 = xor(_T_122, _T_131) @[Bitwise.scala 101:21] + node _T_133 = shr(_T_129, 4) @[Bitwise.scala 102:21] + node _T_134 = and(_T_133, _T_132) @[Bitwise.scala 102:31] + node _T_135 = bits(_T_129, 27, 0) @[Bitwise.scala 102:46] + node _T_136 = shl(_T_135, 4) @[Bitwise.scala 102:65] + node _T_137 = not(_T_132) @[Bitwise.scala 102:77] + node _T_138 = and(_T_136, _T_137) @[Bitwise.scala 102:75] + node _T_139 = or(_T_134, _T_138) @[Bitwise.scala 102:39] + node _T_140 = bits(_T_132, 29, 0) @[Bitwise.scala 101:28] + node _T_141 = shl(_T_140, 2) @[Bitwise.scala 101:47] + node _T_142 = xor(_T_132, _T_141) @[Bitwise.scala 101:21] + node _T_143 = shr(_T_139, 2) @[Bitwise.scala 102:21] + node _T_144 = and(_T_143, _T_142) @[Bitwise.scala 102:31] + node _T_145 = bits(_T_139, 29, 0) @[Bitwise.scala 102:46] + node _T_146 = shl(_T_145, 2) @[Bitwise.scala 102:65] + node _T_147 = not(_T_142) @[Bitwise.scala 102:77] + node _T_148 = and(_T_146, _T_147) @[Bitwise.scala 102:75] + node _T_149 = or(_T_144, _T_148) @[Bitwise.scala 102:39] + node _T_150 = bits(_T_142, 30, 0) @[Bitwise.scala 101:28] + node _T_151 = shl(_T_150, 1) @[Bitwise.scala 101:47] + node _T_152 = xor(_T_142, _T_151) @[Bitwise.scala 101:21] + node _T_153 = shr(_T_149, 1) @[Bitwise.scala 102:21] + node _T_154 = and(_T_153, _T_152) @[Bitwise.scala 102:31] + node _T_155 = bits(_T_149, 30, 0) @[Bitwise.scala 102:46] + node _T_156 = shl(_T_155, 1) @[Bitwise.scala 102:65] + node _T_157 = not(_T_152) @[Bitwise.scala 102:77] + node _T_158 = and(_T_156, _T_157) @[Bitwise.scala 102:75] + node _T_159 = or(_T_154, _T_158) @[Bitwise.scala 102:39] + node _T_160 = bits(_T_107, 32, 32) @[Bitwise.scala 108:44] + node _T_161 = cat(_T_159, _T_160) @[Cat.scala 30:58] + node _T_162 = not(_T_161) @[primitives.scala 65:36] + node _T_163 = mux(_T_102, UInt<1>("h00"), _T_162) @[primitives.scala 65:21] + node _T_164 = not(_T_163) @[primitives.scala 65:17] + node _T_166 = cat(_T_164, UInt<20>("h0fffff")) @[Cat.scala 30:58] + node _T_167 = bits(_T_101, 6, 6) @[primitives.scala 56:25] + node _T_168 = bits(_T_101, 5, 0) @[primitives.scala 57:26] + node _T_170 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_168) @[primitives.scala 68:52] + node _T_171 = bits(_T_170, 19, 0) @[primitives.scala 69:26] + node _T_172 = bits(_T_171, 15, 0) @[Bitwise.scala 108:18] + node _T_175 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 101:47] + node _T_176 = xor(UInt<16>("h0ffff"), _T_175) @[Bitwise.scala 101:21] + node _T_177 = shr(_T_172, 8) @[Bitwise.scala 102:21] + node _T_178 = and(_T_177, _T_176) @[Bitwise.scala 102:31] + node _T_179 = bits(_T_172, 7, 0) @[Bitwise.scala 102:46] + node _T_180 = shl(_T_179, 8) @[Bitwise.scala 102:65] + node _T_181 = not(_T_176) @[Bitwise.scala 102:77] + node _T_182 = and(_T_180, _T_181) @[Bitwise.scala 102:75] + node _T_183 = or(_T_178, _T_182) @[Bitwise.scala 102:39] + node _T_184 = bits(_T_176, 11, 0) @[Bitwise.scala 101:28] + node _T_185 = shl(_T_184, 4) @[Bitwise.scala 101:47] + node _T_186 = xor(_T_176, _T_185) @[Bitwise.scala 101:21] + node _T_187 = shr(_T_183, 4) @[Bitwise.scala 102:21] + node _T_188 = and(_T_187, _T_186) @[Bitwise.scala 102:31] + node _T_189 = bits(_T_183, 11, 0) @[Bitwise.scala 102:46] + node _T_190 = shl(_T_189, 4) @[Bitwise.scala 102:65] + node _T_191 = not(_T_186) @[Bitwise.scala 102:77] + node _T_192 = and(_T_190, _T_191) @[Bitwise.scala 102:75] + node _T_193 = or(_T_188, _T_192) @[Bitwise.scala 102:39] + node _T_194 = bits(_T_186, 13, 0) @[Bitwise.scala 101:28] + node _T_195 = shl(_T_194, 2) @[Bitwise.scala 101:47] + node _T_196 = xor(_T_186, _T_195) @[Bitwise.scala 101:21] + node _T_197 = shr(_T_193, 2) @[Bitwise.scala 102:21] + node _T_198 = and(_T_197, _T_196) @[Bitwise.scala 102:31] + node _T_199 = bits(_T_193, 13, 0) @[Bitwise.scala 102:46] + node _T_200 = shl(_T_199, 2) @[Bitwise.scala 102:65] + node _T_201 = not(_T_196) @[Bitwise.scala 102:77] + node _T_202 = and(_T_200, _T_201) @[Bitwise.scala 102:75] + node _T_203 = or(_T_198, _T_202) @[Bitwise.scala 102:39] + node _T_204 = bits(_T_196, 14, 0) @[Bitwise.scala 101:28] + node _T_205 = shl(_T_204, 1) @[Bitwise.scala 101:47] + node _T_206 = xor(_T_196, _T_205) @[Bitwise.scala 101:21] + node _T_207 = shr(_T_203, 1) @[Bitwise.scala 102:21] + node _T_208 = and(_T_207, _T_206) @[Bitwise.scala 102:31] + node _T_209 = bits(_T_203, 14, 0) @[Bitwise.scala 102:46] + node _T_210 = shl(_T_209, 1) @[Bitwise.scala 102:65] + node _T_211 = not(_T_206) @[Bitwise.scala 102:77] + node _T_212 = and(_T_210, _T_211) @[Bitwise.scala 102:75] + node _T_213 = or(_T_208, _T_212) @[Bitwise.scala 102:39] + node _T_214 = bits(_T_171, 19, 16) @[Bitwise.scala 108:44] + node _T_215 = bits(_T_214, 1, 0) @[Bitwise.scala 108:18] + node _T_216 = bits(_T_215, 0, 0) @[Bitwise.scala 108:18] + node _T_217 = bits(_T_215, 1, 1) @[Bitwise.scala 108:44] + node _T_218 = cat(_T_216, _T_217) @[Cat.scala 30:58] + node _T_219 = bits(_T_214, 3, 2) @[Bitwise.scala 108:44] + node _T_220 = bits(_T_219, 0, 0) @[Bitwise.scala 108:18] + node _T_221 = bits(_T_219, 1, 1) @[Bitwise.scala 108:44] + node _T_222 = cat(_T_220, _T_221) @[Cat.scala 30:58] + node _T_223 = cat(_T_218, _T_222) @[Cat.scala 30:58] + node _T_224 = cat(_T_213, _T_223) @[Cat.scala 30:58] + node _T_226 = mux(_T_167, _T_224, UInt<1>("h00")) @[primitives.scala 59:20] + node CExtraMask = mux(_T_100, _T_166, _T_226) @[primitives.scala 61:20] + node _T_227 = not(sigC) @[MulAddRecFN.scala 151:34] + node negSigC = mux(doSubMags, _T_227, sigC) @[MulAddRecFN.scala 151:22] + node _T_228 = bits(doSubMags, 0, 0) @[Bitwise.scala 71:15] + node _T_231 = mux(_T_228, UInt<108>("h0fffffffffffffffffffffffffff"), UInt<108>("h00")) @[Bitwise.scala 71:12] + node _T_232 = cat(doSubMags, negSigC) @[Cat.scala 30:58] + node _T_233 = cat(_T_232, _T_231) @[Cat.scala 30:58] + node _T_234 = asSInt(_T_233) @[MulAddRecFN.scala 154:64] + node _T_235 = dshr(_T_234, CAlignDist) @[MulAddRecFN.scala 154:70] + node _T_236 = and(sigC, CExtraMask) @[MulAddRecFN.scala 156:19] + node _T_238 = neq(_T_236, UInt<1>("h00")) @[MulAddRecFN.scala 156:33] + node _T_239 = xor(_T_238, doSubMags) @[MulAddRecFN.scala 156:37] + node _T_240 = asUInt(_T_235) @[Cat.scala 30:58] + node _T_241 = cat(_T_240, _T_239) @[Cat.scala 30:58] + node alignedNegSigC = bits(_T_241, 161, 0) @[MulAddRecFN.scala 157:10] + io.mulAddA <= sigA @[MulAddRecFN.scala 159:16] + io.mulAddB <= sigB @[MulAddRecFN.scala 160:16] + node _T_242 = bits(alignedNegSigC, 106, 1) @[MulAddRecFN.scala 161:33] + io.mulAddC <= _T_242 @[MulAddRecFN.scala 161:16] + node _T_243 = bits(expA, 11, 9) @[MulAddRecFN.scala 163:44] + io.toPostMul.highExpA <= _T_243 @[MulAddRecFN.scala 163:37] + node _T_244 = bits(fractA, 51, 51) @[MulAddRecFN.scala 164:46] + io.toPostMul.isNaN_isQuietNaNA <= _T_244 @[MulAddRecFN.scala 164:37] + node _T_245 = bits(expB, 11, 9) @[MulAddRecFN.scala 165:44] + io.toPostMul.highExpB <= _T_245 @[MulAddRecFN.scala 165:37] + node _T_246 = bits(fractB, 51, 51) @[MulAddRecFN.scala 166:46] + io.toPostMul.isNaN_isQuietNaNB <= _T_246 @[MulAddRecFN.scala 166:37] + io.toPostMul.signProd <= signProd @[MulAddRecFN.scala 167:37] + io.toPostMul.isZeroProd <= isZeroProd @[MulAddRecFN.scala 168:37] + io.toPostMul.opSignC <= opSignC @[MulAddRecFN.scala 169:37] + node _T_247 = bits(expC, 11, 9) @[MulAddRecFN.scala 170:44] + io.toPostMul.highExpC <= _T_247 @[MulAddRecFN.scala 170:37] + node _T_248 = bits(fractC, 51, 51) @[MulAddRecFN.scala 171:46] + io.toPostMul.isNaN_isQuietNaNC <= _T_248 @[MulAddRecFN.scala 171:37] + io.toPostMul.isCDominant <= isCDominant @[MulAddRecFN.scala 172:37] + io.toPostMul.CAlignDist_0 <= CAlignDist_0 @[MulAddRecFN.scala 173:37] + io.toPostMul.CAlignDist <= CAlignDist @[MulAddRecFN.scala 174:37] + node _T_249 = bits(alignedNegSigC, 0, 0) @[MulAddRecFN.scala 175:54] + io.toPostMul.bit0AlignedNegSigC <= _T_249 @[MulAddRecFN.scala 175:37] + node _T_250 = bits(alignedNegSigC, 161, 107) @[MulAddRecFN.scala 177:23] + io.toPostMul.highAlignedNegSigC <= _T_250 @[MulAddRecFN.scala 176:37] + io.toPostMul.sExpSum <= sExpSum @[MulAddRecFN.scala 178:37] + io.toPostMul.roundingMode <= io.roundingMode @[MulAddRecFN.scala 179:37] + + module MulAddRecFN_postMul_1 : + input clock : Clock + input reset : UInt<1> + output io : {flip fromPreMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<8>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<55>, sExpSum : UInt<14>, roundingMode : UInt<2>}, flip mulAddResult : UInt<107>, out : UInt<65>, exceptionFlags : UInt<5>} + + io is invalid + io is invalid + node isZeroA = eq(io.fromPreMul.highExpA, UInt<1>("h00")) @[MulAddRecFN.scala 207:46] + node _T_43 = bits(io.fromPreMul.highExpA, 2, 1) @[MulAddRecFN.scala 208:45] + node isSpecialA = eq(_T_43, UInt<2>("h03")) @[MulAddRecFN.scala 208:52] + node _T_45 = bits(io.fromPreMul.highExpA, 0, 0) @[MulAddRecFN.scala 209:56] + node _T_47 = eq(_T_45, UInt<1>("h00")) @[MulAddRecFN.scala 209:32] + node isInfA = and(isSpecialA, _T_47) @[MulAddRecFN.scala 209:29] + node _T_48 = bits(io.fromPreMul.highExpA, 0, 0) @[MulAddRecFN.scala 210:56] + node isNaNA = and(isSpecialA, _T_48) @[MulAddRecFN.scala 210:29] + node _T_50 = eq(io.fromPreMul.isNaN_isQuietNaNA, UInt<1>("h00")) @[MulAddRecFN.scala 211:31] + node isSigNaNA = and(isNaNA, _T_50) @[MulAddRecFN.scala 211:28] + node isZeroB = eq(io.fromPreMul.highExpB, UInt<1>("h00")) @[MulAddRecFN.scala 213:46] + node _T_52 = bits(io.fromPreMul.highExpB, 2, 1) @[MulAddRecFN.scala 214:45] + node isSpecialB = eq(_T_52, UInt<2>("h03")) @[MulAddRecFN.scala 214:52] + node _T_54 = bits(io.fromPreMul.highExpB, 0, 0) @[MulAddRecFN.scala 215:56] + node _T_56 = eq(_T_54, UInt<1>("h00")) @[MulAddRecFN.scala 215:32] + node isInfB = and(isSpecialB, _T_56) @[MulAddRecFN.scala 215:29] + node _T_57 = bits(io.fromPreMul.highExpB, 0, 0) @[MulAddRecFN.scala 216:56] + node isNaNB = and(isSpecialB, _T_57) @[MulAddRecFN.scala 216:29] + node _T_59 = eq(io.fromPreMul.isNaN_isQuietNaNB, UInt<1>("h00")) @[MulAddRecFN.scala 217:31] + node isSigNaNB = and(isNaNB, _T_59) @[MulAddRecFN.scala 217:28] + node isZeroC = eq(io.fromPreMul.highExpC, UInt<1>("h00")) @[MulAddRecFN.scala 219:46] + node _T_61 = bits(io.fromPreMul.highExpC, 2, 1) @[MulAddRecFN.scala 220:45] + node isSpecialC = eq(_T_61, UInt<2>("h03")) @[MulAddRecFN.scala 220:52] + node _T_63 = bits(io.fromPreMul.highExpC, 0, 0) @[MulAddRecFN.scala 221:56] + node _T_65 = eq(_T_63, UInt<1>("h00")) @[MulAddRecFN.scala 221:32] + node isInfC = and(isSpecialC, _T_65) @[MulAddRecFN.scala 221:29] + node _T_66 = bits(io.fromPreMul.highExpC, 0, 0) @[MulAddRecFN.scala 222:56] + node isNaNC = and(isSpecialC, _T_66) @[MulAddRecFN.scala 222:29] + node _T_68 = eq(io.fromPreMul.isNaN_isQuietNaNC, UInt<1>("h00")) @[MulAddRecFN.scala 223:31] + node isSigNaNC = and(isNaNC, _T_68) @[MulAddRecFN.scala 223:28] + node roundingMode_nearest_even = eq(io.fromPreMul.roundingMode, UInt<2>("h00")) @[MulAddRecFN.scala 226:37] + node roundingMode_minMag = eq(io.fromPreMul.roundingMode, UInt<2>("h01")) @[MulAddRecFN.scala 227:59] + node roundingMode_min = eq(io.fromPreMul.roundingMode, UInt<2>("h02")) @[MulAddRecFN.scala 228:59] + node roundingMode_max = eq(io.fromPreMul.roundingMode, UInt<2>("h03")) @[MulAddRecFN.scala 229:59] + node signZeroNotEqOpSigns = mux(roundingMode_min, UInt<1>("h01"), UInt<1>("h00")) @[MulAddRecFN.scala 231:35] + node doSubMags = xor(io.fromPreMul.signProd, io.fromPreMul.opSignC) @[MulAddRecFN.scala 232:44] + node _T_71 = bits(io.mulAddResult, 106, 106) @[MulAddRecFN.scala 237:32] + node _T_73 = add(io.fromPreMul.highAlignedNegSigC, UInt<1>("h01")) @[MulAddRecFN.scala 238:50] + node _T_74 = tail(_T_73, 1) @[MulAddRecFN.scala 238:50] + node _T_75 = mux(_T_71, _T_74, io.fromPreMul.highAlignedNegSigC) @[MulAddRecFN.scala 237:16] + node _T_76 = bits(io.mulAddResult, 105, 0) @[MulAddRecFN.scala 241:28] + node _T_77 = cat(_T_75, _T_76) @[Cat.scala 30:58] + node sigSum = cat(_T_77, io.fromPreMul.bit0AlignedNegSigC) @[Cat.scala 30:58] + node _T_79 = bits(sigSum, 108, 1) @[MulAddRecFN.scala 248:38] + node _T_80 = xor(UInt<108>("h00"), _T_79) @[MulAddRecFN.scala 191:27] + node _T_81 = or(UInt<108>("h00"), _T_79) @[MulAddRecFN.scala 191:37] + node _T_82 = shl(_T_81, 1) @[MulAddRecFN.scala 191:41] + node _T_83 = xor(_T_80, _T_82) @[MulAddRecFN.scala 191:32] + node _T_85 = bits(_T_83, 107, 0) @[primitives.scala 79:35] + node _T_86 = bits(_T_85, 107, 64) @[CircuitMath.scala 35:17] + node _T_87 = bits(_T_85, 63, 0) @[CircuitMath.scala 36:17] + node _T_89 = neq(_T_86, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_90 = bits(_T_86, 43, 32) @[CircuitMath.scala 35:17] + node _T_91 = bits(_T_86, 31, 0) @[CircuitMath.scala 36:17] + node _T_93 = neq(_T_90, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_94 = bits(_T_90, 11, 8) @[CircuitMath.scala 35:17] + node _T_95 = bits(_T_90, 7, 0) @[CircuitMath.scala 36:17] + node _T_97 = neq(_T_94, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_98 = bits(_T_94, 3, 3) @[CircuitMath.scala 32:12] + node _T_100 = bits(_T_94, 2, 2) @[CircuitMath.scala 32:12] + node _T_102 = bits(_T_94, 1, 1) @[CircuitMath.scala 30:8] + node _T_103 = mux(_T_100, UInt<2>("h02"), _T_102) @[CircuitMath.scala 32:10] + node _T_104 = mux(_T_98, UInt<2>("h03"), _T_103) @[CircuitMath.scala 32:10] + node _T_105 = bits(_T_95, 7, 4) @[CircuitMath.scala 35:17] + node _T_106 = bits(_T_95, 3, 0) @[CircuitMath.scala 36:17] + node _T_108 = neq(_T_105, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_109 = bits(_T_105, 3, 3) @[CircuitMath.scala 32:12] + node _T_111 = bits(_T_105, 2, 2) @[CircuitMath.scala 32:12] + node _T_113 = bits(_T_105, 1, 1) @[CircuitMath.scala 30:8] + node _T_114 = mux(_T_111, UInt<2>("h02"), _T_113) @[CircuitMath.scala 32:10] + node _T_115 = mux(_T_109, UInt<2>("h03"), _T_114) @[CircuitMath.scala 32:10] + node _T_116 = bits(_T_106, 3, 3) @[CircuitMath.scala 32:12] + node _T_118 = bits(_T_106, 2, 2) @[CircuitMath.scala 32:12] + node _T_120 = bits(_T_106, 1, 1) @[CircuitMath.scala 30:8] + node _T_121 = mux(_T_118, UInt<2>("h02"), _T_120) @[CircuitMath.scala 32:10] + node _T_122 = mux(_T_116, UInt<2>("h03"), _T_121) @[CircuitMath.scala 32:10] + node _T_123 = mux(_T_108, _T_115, _T_122) @[CircuitMath.scala 38:21] + node _T_124 = cat(_T_108, _T_123) @[Cat.scala 30:58] + node _T_125 = mux(_T_97, _T_104, _T_124) @[CircuitMath.scala 38:21] + node _T_126 = cat(_T_97, _T_125) @[Cat.scala 30:58] + node _T_127 = bits(_T_91, 31, 16) @[CircuitMath.scala 35:17] + node _T_128 = bits(_T_91, 15, 0) @[CircuitMath.scala 36:17] + node _T_130 = neq(_T_127, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_131 = bits(_T_127, 15, 8) @[CircuitMath.scala 35:17] + node _T_132 = bits(_T_127, 7, 0) @[CircuitMath.scala 36:17] + node _T_134 = neq(_T_131, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_135 = bits(_T_131, 7, 4) @[CircuitMath.scala 35:17] + node _T_136 = bits(_T_131, 3, 0) @[CircuitMath.scala 36:17] + node _T_138 = neq(_T_135, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_139 = bits(_T_135, 3, 3) @[CircuitMath.scala 32:12] + node _T_141 = bits(_T_135, 2, 2) @[CircuitMath.scala 32:12] + node _T_143 = bits(_T_135, 1, 1) @[CircuitMath.scala 30:8] + node _T_144 = mux(_T_141, UInt<2>("h02"), _T_143) @[CircuitMath.scala 32:10] + node _T_145 = mux(_T_139, UInt<2>("h03"), _T_144) @[CircuitMath.scala 32:10] + node _T_146 = bits(_T_136, 3, 3) @[CircuitMath.scala 32:12] + node _T_148 = bits(_T_136, 2, 2) @[CircuitMath.scala 32:12] + node _T_150 = bits(_T_136, 1, 1) @[CircuitMath.scala 30:8] + node _T_151 = mux(_T_148, UInt<2>("h02"), _T_150) @[CircuitMath.scala 32:10] + node _T_152 = mux(_T_146, UInt<2>("h03"), _T_151) @[CircuitMath.scala 32:10] + node _T_153 = mux(_T_138, _T_145, _T_152) @[CircuitMath.scala 38:21] + node _T_154 = cat(_T_138, _T_153) @[Cat.scala 30:58] + node _T_155 = bits(_T_132, 7, 4) @[CircuitMath.scala 35:17] + node _T_156 = bits(_T_132, 3, 0) @[CircuitMath.scala 36:17] + node _T_158 = neq(_T_155, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_159 = bits(_T_155, 3, 3) @[CircuitMath.scala 32:12] + node _T_161 = bits(_T_155, 2, 2) @[CircuitMath.scala 32:12] + node _T_163 = bits(_T_155, 1, 1) @[CircuitMath.scala 30:8] + node _T_164 = mux(_T_161, UInt<2>("h02"), _T_163) @[CircuitMath.scala 32:10] + node _T_165 = mux(_T_159, UInt<2>("h03"), _T_164) @[CircuitMath.scala 32:10] + node _T_166 = bits(_T_156, 3, 3) @[CircuitMath.scala 32:12] + node _T_168 = bits(_T_156, 2, 2) @[CircuitMath.scala 32:12] + node _T_170 = bits(_T_156, 1, 1) @[CircuitMath.scala 30:8] + node _T_171 = mux(_T_168, UInt<2>("h02"), _T_170) @[CircuitMath.scala 32:10] + node _T_172 = mux(_T_166, UInt<2>("h03"), _T_171) @[CircuitMath.scala 32:10] + node _T_173 = mux(_T_158, _T_165, _T_172) @[CircuitMath.scala 38:21] + node _T_174 = cat(_T_158, _T_173) @[Cat.scala 30:58] + node _T_175 = mux(_T_134, _T_154, _T_174) @[CircuitMath.scala 38:21] + node _T_176 = cat(_T_134, _T_175) @[Cat.scala 30:58] + node _T_177 = bits(_T_128, 15, 8) @[CircuitMath.scala 35:17] + node _T_178 = bits(_T_128, 7, 0) @[CircuitMath.scala 36:17] + node _T_180 = neq(_T_177, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_181 = bits(_T_177, 7, 4) @[CircuitMath.scala 35:17] + node _T_182 = bits(_T_177, 3, 0) @[CircuitMath.scala 36:17] + node _T_184 = neq(_T_181, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_185 = bits(_T_181, 3, 3) @[CircuitMath.scala 32:12] + node _T_187 = bits(_T_181, 2, 2) @[CircuitMath.scala 32:12] + node _T_189 = bits(_T_181, 1, 1) @[CircuitMath.scala 30:8] + node _T_190 = mux(_T_187, UInt<2>("h02"), _T_189) @[CircuitMath.scala 32:10] + node _T_191 = mux(_T_185, UInt<2>("h03"), _T_190) @[CircuitMath.scala 32:10] + node _T_192 = bits(_T_182, 3, 3) @[CircuitMath.scala 32:12] + node _T_194 = bits(_T_182, 2, 2) @[CircuitMath.scala 32:12] + node _T_196 = bits(_T_182, 1, 1) @[CircuitMath.scala 30:8] + node _T_197 = mux(_T_194, UInt<2>("h02"), _T_196) @[CircuitMath.scala 32:10] + node _T_198 = mux(_T_192, UInt<2>("h03"), _T_197) @[CircuitMath.scala 32:10] + node _T_199 = mux(_T_184, _T_191, _T_198) @[CircuitMath.scala 38:21] + node _T_200 = cat(_T_184, _T_199) @[Cat.scala 30:58] + node _T_201 = bits(_T_178, 7, 4) @[CircuitMath.scala 35:17] + node _T_202 = bits(_T_178, 3, 0) @[CircuitMath.scala 36:17] + node _T_204 = neq(_T_201, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_205 = bits(_T_201, 3, 3) @[CircuitMath.scala 32:12] + node _T_207 = bits(_T_201, 2, 2) @[CircuitMath.scala 32:12] + node _T_209 = bits(_T_201, 1, 1) @[CircuitMath.scala 30:8] + node _T_210 = mux(_T_207, UInt<2>("h02"), _T_209) @[CircuitMath.scala 32:10] + node _T_211 = mux(_T_205, UInt<2>("h03"), _T_210) @[CircuitMath.scala 32:10] + node _T_212 = bits(_T_202, 3, 3) @[CircuitMath.scala 32:12] + node _T_214 = bits(_T_202, 2, 2) @[CircuitMath.scala 32:12] + node _T_216 = bits(_T_202, 1, 1) @[CircuitMath.scala 30:8] + node _T_217 = mux(_T_214, UInt<2>("h02"), _T_216) @[CircuitMath.scala 32:10] + node _T_218 = mux(_T_212, UInt<2>("h03"), _T_217) @[CircuitMath.scala 32:10] + node _T_219 = mux(_T_204, _T_211, _T_218) @[CircuitMath.scala 38:21] + node _T_220 = cat(_T_204, _T_219) @[Cat.scala 30:58] + node _T_221 = mux(_T_180, _T_200, _T_220) @[CircuitMath.scala 38:21] + node _T_222 = cat(_T_180, _T_221) @[Cat.scala 30:58] + node _T_223 = mux(_T_130, _T_176, _T_222) @[CircuitMath.scala 38:21] + node _T_224 = cat(_T_130, _T_223) @[Cat.scala 30:58] + node _T_225 = mux(_T_93, _T_126, _T_224) @[CircuitMath.scala 38:21] + node _T_226 = cat(_T_93, _T_225) @[Cat.scala 30:58] + node _T_227 = bits(_T_87, 63, 32) @[CircuitMath.scala 35:17] + node _T_228 = bits(_T_87, 31, 0) @[CircuitMath.scala 36:17] + node _T_230 = neq(_T_227, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_231 = bits(_T_227, 31, 16) @[CircuitMath.scala 35:17] + node _T_232 = bits(_T_227, 15, 0) @[CircuitMath.scala 36:17] + node _T_234 = neq(_T_231, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_235 = bits(_T_231, 15, 8) @[CircuitMath.scala 35:17] + node _T_236 = bits(_T_231, 7, 0) @[CircuitMath.scala 36:17] + node _T_238 = neq(_T_235, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_239 = bits(_T_235, 7, 4) @[CircuitMath.scala 35:17] + node _T_240 = bits(_T_235, 3, 0) @[CircuitMath.scala 36:17] + node _T_242 = neq(_T_239, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_243 = bits(_T_239, 3, 3) @[CircuitMath.scala 32:12] + node _T_245 = bits(_T_239, 2, 2) @[CircuitMath.scala 32:12] + node _T_247 = bits(_T_239, 1, 1) @[CircuitMath.scala 30:8] + node _T_248 = mux(_T_245, UInt<2>("h02"), _T_247) @[CircuitMath.scala 32:10] + node _T_249 = mux(_T_243, UInt<2>("h03"), _T_248) @[CircuitMath.scala 32:10] + node _T_250 = bits(_T_240, 3, 3) @[CircuitMath.scala 32:12] + node _T_252 = bits(_T_240, 2, 2) @[CircuitMath.scala 32:12] + node _T_254 = bits(_T_240, 1, 1) @[CircuitMath.scala 30:8] + node _T_255 = mux(_T_252, UInt<2>("h02"), _T_254) @[CircuitMath.scala 32:10] + node _T_256 = mux(_T_250, UInt<2>("h03"), _T_255) @[CircuitMath.scala 32:10] + node _T_257 = mux(_T_242, _T_249, _T_256) @[CircuitMath.scala 38:21] + node _T_258 = cat(_T_242, _T_257) @[Cat.scala 30:58] + node _T_259 = bits(_T_236, 7, 4) @[CircuitMath.scala 35:17] + node _T_260 = bits(_T_236, 3, 0) @[CircuitMath.scala 36:17] + node _T_262 = neq(_T_259, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_263 = bits(_T_259, 3, 3) @[CircuitMath.scala 32:12] + node _T_265 = bits(_T_259, 2, 2) @[CircuitMath.scala 32:12] + node _T_267 = bits(_T_259, 1, 1) @[CircuitMath.scala 30:8] + node _T_268 = mux(_T_265, UInt<2>("h02"), _T_267) @[CircuitMath.scala 32:10] + node _T_269 = mux(_T_263, UInt<2>("h03"), _T_268) @[CircuitMath.scala 32:10] + node _T_270 = bits(_T_260, 3, 3) @[CircuitMath.scala 32:12] + node _T_272 = bits(_T_260, 2, 2) @[CircuitMath.scala 32:12] + node _T_274 = bits(_T_260, 1, 1) @[CircuitMath.scala 30:8] + node _T_275 = mux(_T_272, UInt<2>("h02"), _T_274) @[CircuitMath.scala 32:10] + node _T_276 = mux(_T_270, UInt<2>("h03"), _T_275) @[CircuitMath.scala 32:10] + node _T_277 = mux(_T_262, _T_269, _T_276) @[CircuitMath.scala 38:21] + node _T_278 = cat(_T_262, _T_277) @[Cat.scala 30:58] + node _T_279 = mux(_T_238, _T_258, _T_278) @[CircuitMath.scala 38:21] + node _T_280 = cat(_T_238, _T_279) @[Cat.scala 30:58] + node _T_281 = bits(_T_232, 15, 8) @[CircuitMath.scala 35:17] + node _T_282 = bits(_T_232, 7, 0) @[CircuitMath.scala 36:17] + node _T_284 = neq(_T_281, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_285 = bits(_T_281, 7, 4) @[CircuitMath.scala 35:17] + node _T_286 = bits(_T_281, 3, 0) @[CircuitMath.scala 36:17] + node _T_288 = neq(_T_285, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_289 = bits(_T_285, 3, 3) @[CircuitMath.scala 32:12] + node _T_291 = bits(_T_285, 2, 2) @[CircuitMath.scala 32:12] + node _T_293 = bits(_T_285, 1, 1) @[CircuitMath.scala 30:8] + node _T_294 = mux(_T_291, UInt<2>("h02"), _T_293) @[CircuitMath.scala 32:10] + node _T_295 = mux(_T_289, UInt<2>("h03"), _T_294) @[CircuitMath.scala 32:10] + node _T_296 = bits(_T_286, 3, 3) @[CircuitMath.scala 32:12] + node _T_298 = bits(_T_286, 2, 2) @[CircuitMath.scala 32:12] + node _T_300 = bits(_T_286, 1, 1) @[CircuitMath.scala 30:8] + node _T_301 = mux(_T_298, UInt<2>("h02"), _T_300) @[CircuitMath.scala 32:10] + node _T_302 = mux(_T_296, UInt<2>("h03"), _T_301) @[CircuitMath.scala 32:10] + node _T_303 = mux(_T_288, _T_295, _T_302) @[CircuitMath.scala 38:21] + node _T_304 = cat(_T_288, _T_303) @[Cat.scala 30:58] + node _T_305 = bits(_T_282, 7, 4) @[CircuitMath.scala 35:17] + node _T_306 = bits(_T_282, 3, 0) @[CircuitMath.scala 36:17] + node _T_308 = neq(_T_305, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_309 = bits(_T_305, 3, 3) @[CircuitMath.scala 32:12] + node _T_311 = bits(_T_305, 2, 2) @[CircuitMath.scala 32:12] + node _T_313 = bits(_T_305, 1, 1) @[CircuitMath.scala 30:8] + node _T_314 = mux(_T_311, UInt<2>("h02"), _T_313) @[CircuitMath.scala 32:10] + node _T_315 = mux(_T_309, UInt<2>("h03"), _T_314) @[CircuitMath.scala 32:10] + node _T_316 = bits(_T_306, 3, 3) @[CircuitMath.scala 32:12] + node _T_318 = bits(_T_306, 2, 2) @[CircuitMath.scala 32:12] + node _T_320 = bits(_T_306, 1, 1) @[CircuitMath.scala 30:8] + node _T_321 = mux(_T_318, UInt<2>("h02"), _T_320) @[CircuitMath.scala 32:10] + node _T_322 = mux(_T_316, UInt<2>("h03"), _T_321) @[CircuitMath.scala 32:10] + node _T_323 = mux(_T_308, _T_315, _T_322) @[CircuitMath.scala 38:21] + node _T_324 = cat(_T_308, _T_323) @[Cat.scala 30:58] + node _T_325 = mux(_T_284, _T_304, _T_324) @[CircuitMath.scala 38:21] + node _T_326 = cat(_T_284, _T_325) @[Cat.scala 30:58] + node _T_327 = mux(_T_234, _T_280, _T_326) @[CircuitMath.scala 38:21] + node _T_328 = cat(_T_234, _T_327) @[Cat.scala 30:58] + node _T_329 = bits(_T_228, 31, 16) @[CircuitMath.scala 35:17] + node _T_330 = bits(_T_228, 15, 0) @[CircuitMath.scala 36:17] + node _T_332 = neq(_T_329, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_333 = bits(_T_329, 15, 8) @[CircuitMath.scala 35:17] + node _T_334 = bits(_T_329, 7, 0) @[CircuitMath.scala 36:17] + node _T_336 = neq(_T_333, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_337 = bits(_T_333, 7, 4) @[CircuitMath.scala 35:17] + node _T_338 = bits(_T_333, 3, 0) @[CircuitMath.scala 36:17] + node _T_340 = neq(_T_337, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_341 = bits(_T_337, 3, 3) @[CircuitMath.scala 32:12] + node _T_343 = bits(_T_337, 2, 2) @[CircuitMath.scala 32:12] + node _T_345 = bits(_T_337, 1, 1) @[CircuitMath.scala 30:8] + node _T_346 = mux(_T_343, UInt<2>("h02"), _T_345) @[CircuitMath.scala 32:10] + node _T_347 = mux(_T_341, UInt<2>("h03"), _T_346) @[CircuitMath.scala 32:10] + node _T_348 = bits(_T_338, 3, 3) @[CircuitMath.scala 32:12] + node _T_350 = bits(_T_338, 2, 2) @[CircuitMath.scala 32:12] + node _T_352 = bits(_T_338, 1, 1) @[CircuitMath.scala 30:8] + node _T_353 = mux(_T_350, UInt<2>("h02"), _T_352) @[CircuitMath.scala 32:10] + node _T_354 = mux(_T_348, UInt<2>("h03"), _T_353) @[CircuitMath.scala 32:10] + node _T_355 = mux(_T_340, _T_347, _T_354) @[CircuitMath.scala 38:21] + node _T_356 = cat(_T_340, _T_355) @[Cat.scala 30:58] + node _T_357 = bits(_T_334, 7, 4) @[CircuitMath.scala 35:17] + node _T_358 = bits(_T_334, 3, 0) @[CircuitMath.scala 36:17] + node _T_360 = neq(_T_357, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_361 = bits(_T_357, 3, 3) @[CircuitMath.scala 32:12] + node _T_363 = bits(_T_357, 2, 2) @[CircuitMath.scala 32:12] + node _T_365 = bits(_T_357, 1, 1) @[CircuitMath.scala 30:8] + node _T_366 = mux(_T_363, UInt<2>("h02"), _T_365) @[CircuitMath.scala 32:10] + node _T_367 = mux(_T_361, UInt<2>("h03"), _T_366) @[CircuitMath.scala 32:10] + node _T_368 = bits(_T_358, 3, 3) @[CircuitMath.scala 32:12] + node _T_370 = bits(_T_358, 2, 2) @[CircuitMath.scala 32:12] + node _T_372 = bits(_T_358, 1, 1) @[CircuitMath.scala 30:8] + node _T_373 = mux(_T_370, UInt<2>("h02"), _T_372) @[CircuitMath.scala 32:10] + node _T_374 = mux(_T_368, UInt<2>("h03"), _T_373) @[CircuitMath.scala 32:10] + node _T_375 = mux(_T_360, _T_367, _T_374) @[CircuitMath.scala 38:21] + node _T_376 = cat(_T_360, _T_375) @[Cat.scala 30:58] + node _T_377 = mux(_T_336, _T_356, _T_376) @[CircuitMath.scala 38:21] + node _T_378 = cat(_T_336, _T_377) @[Cat.scala 30:58] + node _T_379 = bits(_T_330, 15, 8) @[CircuitMath.scala 35:17] + node _T_380 = bits(_T_330, 7, 0) @[CircuitMath.scala 36:17] + node _T_382 = neq(_T_379, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_383 = bits(_T_379, 7, 4) @[CircuitMath.scala 35:17] + node _T_384 = bits(_T_379, 3, 0) @[CircuitMath.scala 36:17] + node _T_386 = neq(_T_383, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_387 = bits(_T_383, 3, 3) @[CircuitMath.scala 32:12] + node _T_389 = bits(_T_383, 2, 2) @[CircuitMath.scala 32:12] + node _T_391 = bits(_T_383, 1, 1) @[CircuitMath.scala 30:8] + node _T_392 = mux(_T_389, UInt<2>("h02"), _T_391) @[CircuitMath.scala 32:10] + node _T_393 = mux(_T_387, UInt<2>("h03"), _T_392) @[CircuitMath.scala 32:10] + node _T_394 = bits(_T_384, 3, 3) @[CircuitMath.scala 32:12] + node _T_396 = bits(_T_384, 2, 2) @[CircuitMath.scala 32:12] + node _T_398 = bits(_T_384, 1, 1) @[CircuitMath.scala 30:8] + node _T_399 = mux(_T_396, UInt<2>("h02"), _T_398) @[CircuitMath.scala 32:10] + node _T_400 = mux(_T_394, UInt<2>("h03"), _T_399) @[CircuitMath.scala 32:10] + node _T_401 = mux(_T_386, _T_393, _T_400) @[CircuitMath.scala 38:21] + node _T_402 = cat(_T_386, _T_401) @[Cat.scala 30:58] + node _T_403 = bits(_T_380, 7, 4) @[CircuitMath.scala 35:17] + node _T_404 = bits(_T_380, 3, 0) @[CircuitMath.scala 36:17] + node _T_406 = neq(_T_403, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_407 = bits(_T_403, 3, 3) @[CircuitMath.scala 32:12] + node _T_409 = bits(_T_403, 2, 2) @[CircuitMath.scala 32:12] + node _T_411 = bits(_T_403, 1, 1) @[CircuitMath.scala 30:8] + node _T_412 = mux(_T_409, UInt<2>("h02"), _T_411) @[CircuitMath.scala 32:10] + node _T_413 = mux(_T_407, UInt<2>("h03"), _T_412) @[CircuitMath.scala 32:10] + node _T_414 = bits(_T_404, 3, 3) @[CircuitMath.scala 32:12] + node _T_416 = bits(_T_404, 2, 2) @[CircuitMath.scala 32:12] + node _T_418 = bits(_T_404, 1, 1) @[CircuitMath.scala 30:8] + node _T_419 = mux(_T_416, UInt<2>("h02"), _T_418) @[CircuitMath.scala 32:10] + node _T_420 = mux(_T_414, UInt<2>("h03"), _T_419) @[CircuitMath.scala 32:10] + node _T_421 = mux(_T_406, _T_413, _T_420) @[CircuitMath.scala 38:21] + node _T_422 = cat(_T_406, _T_421) @[Cat.scala 30:58] + node _T_423 = mux(_T_382, _T_402, _T_422) @[CircuitMath.scala 38:21] + node _T_424 = cat(_T_382, _T_423) @[Cat.scala 30:58] + node _T_425 = mux(_T_332, _T_378, _T_424) @[CircuitMath.scala 38:21] + node _T_426 = cat(_T_332, _T_425) @[Cat.scala 30:58] + node _T_427 = mux(_T_230, _T_328, _T_426) @[CircuitMath.scala 38:21] + node _T_428 = cat(_T_230, _T_427) @[Cat.scala 30:58] + node _T_429 = mux(_T_89, _T_226, _T_428) @[CircuitMath.scala 38:21] + node _T_430 = cat(_T_89, _T_429) @[Cat.scala 30:58] + node _T_431 = sub(UInt<8>("h0a0"), _T_430) @[primitives.scala 79:25] + node _T_432 = asUInt(_T_431) @[primitives.scala 79:25] + node estNormNeg_dist = tail(_T_432, 1) @[primitives.scala 79:25] + node _T_433 = bits(sigSum, 75, 44) @[MulAddRecFN.scala 252:19] + node _T_435 = neq(_T_433, UInt<1>("h00")) @[MulAddRecFN.scala 254:15] + node _T_436 = bits(sigSum, 43, 0) @[MulAddRecFN.scala 255:19] + node _T_438 = neq(_T_436, UInt<1>("h00")) @[MulAddRecFN.scala 255:57] + node firstReduceSigSum = cat(_T_435, _T_438) @[Cat.scala 30:58] + node complSigSum = not(sigSum) @[MulAddRecFN.scala 257:23] + node _T_439 = bits(complSigSum, 75, 44) @[MulAddRecFN.scala 259:24] + node _T_441 = neq(_T_439, UInt<1>("h00")) @[MulAddRecFN.scala 261:15] + node _T_442 = bits(complSigSum, 43, 0) @[MulAddRecFN.scala 262:24] + node _T_444 = neq(_T_442, UInt<1>("h00")) @[MulAddRecFN.scala 262:62] + node firstReduceComplSigSum = cat(_T_441, _T_444) @[Cat.scala 30:58] + node _T_445 = or(io.fromPreMul.CAlignDist_0, doSubMags) @[MulAddRecFN.scala 266:40] + node _T_447 = sub(io.fromPreMul.CAlignDist, UInt<1>("h01")) @[MulAddRecFN.scala 268:39] + node _T_448 = asUInt(_T_447) @[MulAddRecFN.scala 268:39] + node _T_449 = tail(_T_448, 1) @[MulAddRecFN.scala 268:39] + node _T_450 = bits(_T_449, 5, 0) @[MulAddRecFN.scala 268:49] + node CDom_estNormDist = mux(_T_445, io.fromPreMul.CAlignDist, _T_450) @[MulAddRecFN.scala 266:12] + node _T_452 = eq(doSubMags, UInt<1>("h00")) @[MulAddRecFN.scala 271:13] + node _T_453 = bits(CDom_estNormDist, 5, 5) @[MulAddRecFN.scala 271:46] + node _T_455 = eq(_T_453, UInt<1>("h00")) @[MulAddRecFN.scala 271:28] + node _T_456 = and(_T_452, _T_455) @[MulAddRecFN.scala 271:25] + node _T_457 = bits(sigSum, 161, 76) @[MulAddRecFN.scala 272:23] + node _T_459 = neq(firstReduceSigSum, UInt<1>("h00")) @[MulAddRecFN.scala 273:35] + node _T_460 = cat(_T_457, _T_459) @[Cat.scala 30:58] + node _T_462 = mux(_T_456, _T_460, UInt<1>("h00")) @[MulAddRecFN.scala 271:12] + node _T_464 = eq(doSubMags, UInt<1>("h00")) @[MulAddRecFN.scala 277:13] + node _T_465 = bits(CDom_estNormDist, 5, 5) @[MulAddRecFN.scala 277:44] + node _T_466 = and(_T_464, _T_465) @[MulAddRecFN.scala 277:25] + node _T_467 = bits(sigSum, 129, 44) @[MulAddRecFN.scala 278:23] + node _T_468 = bits(firstReduceSigSum, 0, 0) @[MulAddRecFN.scala 282:34] + node _T_469 = cat(_T_467, _T_468) @[Cat.scala 30:58] + node _T_471 = mux(_T_466, _T_469, UInt<1>("h00")) @[MulAddRecFN.scala 277:12] + node _T_472 = or(_T_462, _T_471) @[MulAddRecFN.scala 276:11] + node _T_473 = bits(CDom_estNormDist, 5, 5) @[MulAddRecFN.scala 286:44] + node _T_475 = eq(_T_473, UInt<1>("h00")) @[MulAddRecFN.scala 286:26] + node _T_476 = and(doSubMags, _T_475) @[MulAddRecFN.scala 286:23] + node _T_477 = bits(complSigSum, 161, 76) @[MulAddRecFN.scala 287:28] + node _T_479 = neq(firstReduceComplSigSum, UInt<1>("h00")) @[MulAddRecFN.scala 288:40] + node _T_480 = cat(_T_477, _T_479) @[Cat.scala 30:58] + node _T_482 = mux(_T_476, _T_480, UInt<1>("h00")) @[MulAddRecFN.scala 286:12] + node _T_483 = or(_T_472, _T_482) @[MulAddRecFN.scala 285:11] + node _T_484 = bits(CDom_estNormDist, 5, 5) @[MulAddRecFN.scala 292:42] + node _T_485 = and(doSubMags, _T_484) @[MulAddRecFN.scala 292:23] + node _T_486 = bits(complSigSum, 129, 44) @[MulAddRecFN.scala 293:28] + node _T_487 = bits(firstReduceComplSigSum, 0, 0) @[MulAddRecFN.scala 297:39] + node _T_488 = cat(_T_486, _T_487) @[Cat.scala 30:58] + node _T_490 = mux(_T_485, _T_488, UInt<1>("h00")) @[MulAddRecFN.scala 292:12] + node CDom_firstNormAbsSigSum = or(_T_483, _T_490) @[MulAddRecFN.scala 291:11] + node _T_491 = bits(sigSum, 108, 44) @[MulAddRecFN.scala 308:23] + node _T_492 = bits(firstReduceComplSigSum, 0, 0) @[MulAddRecFN.scala 310:45] + node _T_494 = eq(_T_492, UInt<1>("h00")) @[MulAddRecFN.scala 310:21] + node _T_495 = bits(firstReduceSigSum, 0, 0) @[MulAddRecFN.scala 311:38] + node _T_496 = mux(doSubMags, _T_494, _T_495) @[MulAddRecFN.scala 309:20] + node _T_497 = cat(_T_491, _T_496) @[Cat.scala 30:58] + node _T_498 = bits(sigSum, 97, 1) @[MulAddRecFN.scala 314:24] + node _T_499 = bits(estNormNeg_dist, 4, 4) @[MulAddRecFN.scala 316:37] + node _T_500 = bits(sigSum, 1, 1) @[MulAddRecFN.scala 318:32] + node _T_501 = bits(doSubMags, 0, 0) @[Bitwise.scala 71:15] + node _T_504 = mux(_T_501, UInt<86>("h03fffffffffffffffffffff"), UInt<86>("h00")) @[Bitwise.scala 71:12] + node _T_505 = cat(_T_500, _T_504) @[Cat.scala 30:58] + node _T_506 = mux(_T_499, _T_497, _T_505) @[MulAddRecFN.scala 316:21] + node _T_507 = bits(sigSum, 97, 12) @[MulAddRecFN.scala 324:28] + node _T_508 = bits(complSigSum, 11, 1) @[MulAddRecFN.scala 329:39] + node _T_510 = eq(_T_508, UInt<1>("h00")) @[MulAddRecFN.scala 329:77] + node _T_511 = bits(sigSum, 11, 1) @[MulAddRecFN.scala 331:34] + node _T_513 = neq(_T_511, UInt<1>("h00")) @[MulAddRecFN.scala 331:72] + node _T_514 = mux(doSubMags, _T_510, _T_513) @[MulAddRecFN.scala 328:26] + node _T_515 = cat(_T_507, _T_514) @[Cat.scala 30:58] + node _T_516 = bits(estNormNeg_dist, 6, 6) @[MulAddRecFN.scala 338:28] + node _T_517 = bits(estNormNeg_dist, 5, 5) @[MulAddRecFN.scala 339:33] + node _T_518 = bits(sigSum, 65, 1) @[MulAddRecFN.scala 340:28] + node _T_519 = bits(doSubMags, 0, 0) @[Bitwise.scala 71:15] + node _T_522 = mux(_T_519, UInt<22>("h03fffff"), UInt<22>("h00")) @[Bitwise.scala 71:12] + node _T_523 = cat(_T_518, _T_522) @[Cat.scala 30:58] + node _T_524 = mux(_T_517, _T_523, _T_515) @[MulAddRecFN.scala 339:17] + node _T_525 = bits(estNormNeg_dist, 5, 5) @[MulAddRecFN.scala 345:33] + node _T_526 = bits(sigSum, 33, 1) @[MulAddRecFN.scala 347:28] + node _T_527 = bits(doSubMags, 0, 0) @[Bitwise.scala 71:15] + node _T_530 = mux(_T_527, UInt<54>("h03fffffffffffff"), UInt<54>("h00")) @[Bitwise.scala 71:12] + node _T_531 = cat(_T_526, _T_530) @[Cat.scala 30:58] + node _T_532 = mux(_T_525, _T_506, _T_531) @[MulAddRecFN.scala 345:17] + node notCDom_pos_firstNormAbsSigSum = mux(_T_516, _T_524, _T_532) @[MulAddRecFN.scala 338:12] + node _T_533 = bits(complSigSum, 107, 44) @[MulAddRecFN.scala 360:28] + node _T_534 = bits(firstReduceComplSigSum, 0, 0) @[MulAddRecFN.scala 361:39] + node _T_535 = cat(_T_533, _T_534) @[Cat.scala 30:58] + node _T_536 = bits(complSigSum, 97, 1) @[MulAddRecFN.scala 363:29] + node _T_537 = bits(estNormNeg_dist, 4, 4) @[MulAddRecFN.scala 365:37] + node _T_538 = bits(complSigSum, 2, 1) @[MulAddRecFN.scala 367:33] + node _T_539 = shl(_T_538, 86) @[MulAddRecFN.scala 367:68] + node _T_540 = mux(_T_537, _T_535, _T_539) @[MulAddRecFN.scala 365:21] + node _T_541 = bits(complSigSum, 98, 12) @[MulAddRecFN.scala 372:33] + node _T_542 = bits(complSigSum, 11, 1) @[MulAddRecFN.scala 376:33] + node _T_544 = neq(_T_542, UInt<1>("h00")) @[MulAddRecFN.scala 376:71] + node _T_545 = cat(_T_541, _T_544) @[Cat.scala 30:58] + node _T_546 = bits(estNormNeg_dist, 6, 6) @[MulAddRecFN.scala 379:28] + node _T_547 = bits(estNormNeg_dist, 5, 5) @[MulAddRecFN.scala 380:33] + node _T_548 = bits(complSigSum, 66, 1) @[MulAddRecFN.scala 381:29] + node _T_549 = shl(_T_548, 22) @[MulAddRecFN.scala 381:64] + node _T_550 = mux(_T_547, _T_549, _T_545) @[MulAddRecFN.scala 380:17] + node _T_551 = bits(estNormNeg_dist, 5, 5) @[MulAddRecFN.scala 385:33] + node _T_552 = bits(complSigSum, 34, 1) @[MulAddRecFN.scala 387:29] + node _T_553 = shl(_T_552, 54) @[MulAddRecFN.scala 387:64] + node _T_554 = mux(_T_551, _T_540, _T_553) @[MulAddRecFN.scala 385:17] + node notCDom_neg_cFirstNormAbsSigSum = mux(_T_546, _T_550, _T_554) @[MulAddRecFN.scala 379:12] + node notCDom_signSigSum = bits(sigSum, 109, 109) @[MulAddRecFN.scala 392:36] + node _T_556 = eq(isZeroC, UInt<1>("h00")) @[MulAddRecFN.scala 395:26] + node _T_557 = and(doSubMags, _T_556) @[MulAddRecFN.scala 395:23] + node doNegSignSum = mux(io.fromPreMul.isCDominant, _T_557, notCDom_signSigSum) @[MulAddRecFN.scala 394:12] + node _T_558 = mux(notCDom_signSigSum, estNormNeg_dist, estNormNeg_dist) @[MulAddRecFN.scala 401:16] + node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, _T_558) @[MulAddRecFN.scala 399:12] + node _T_559 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) @[MulAddRecFN.scala 408:16] + node _T_560 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) @[MulAddRecFN.scala 412:16] + node cFirstNormAbsSigSum = mux(notCDom_signSigSum, _T_559, _T_560) @[MulAddRecFN.scala 407:12] + node _T_562 = eq(io.fromPreMul.isCDominant, UInt<1>("h00")) @[MulAddRecFN.scala 418:9] + node _T_564 = eq(notCDom_signSigSum, UInt<1>("h00")) @[MulAddRecFN.scala 418:40] + node _T_565 = and(_T_562, _T_564) @[MulAddRecFN.scala 418:37] + node doIncrSig = and(_T_565, doSubMags) @[MulAddRecFN.scala 418:61] + node estNormDist_5 = bits(estNormDist, 4, 0) @[MulAddRecFN.scala 419:36] + node normTo2ShiftDist = not(estNormDist_5) @[MulAddRecFN.scala 420:28] + node _T_567 = dshr(asSInt(UInt<33>("h0100000000")), normTo2ShiftDist) @[primitives.scala 68:52] + node _T_568 = bits(_T_567, 31, 1) @[primitives.scala 69:26] + node _T_569 = bits(_T_568, 15, 0) @[Bitwise.scala 108:18] + node _T_572 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 101:47] + node _T_573 = xor(UInt<16>("h0ffff"), _T_572) @[Bitwise.scala 101:21] + node _T_574 = shr(_T_569, 8) @[Bitwise.scala 102:21] + node _T_575 = and(_T_574, _T_573) @[Bitwise.scala 102:31] + node _T_576 = bits(_T_569, 7, 0) @[Bitwise.scala 102:46] + node _T_577 = shl(_T_576, 8) @[Bitwise.scala 102:65] + node _T_578 = not(_T_573) @[Bitwise.scala 102:77] + node _T_579 = and(_T_577, _T_578) @[Bitwise.scala 102:75] + node _T_580 = or(_T_575, _T_579) @[Bitwise.scala 102:39] + node _T_581 = bits(_T_573, 11, 0) @[Bitwise.scala 101:28] + node _T_582 = shl(_T_581, 4) @[Bitwise.scala 101:47] + node _T_583 = xor(_T_573, _T_582) @[Bitwise.scala 101:21] + node _T_584 = shr(_T_580, 4) @[Bitwise.scala 102:21] + node _T_585 = and(_T_584, _T_583) @[Bitwise.scala 102:31] + node _T_586 = bits(_T_580, 11, 0) @[Bitwise.scala 102:46] + node _T_587 = shl(_T_586, 4) @[Bitwise.scala 102:65] + node _T_588 = not(_T_583) @[Bitwise.scala 102:77] + node _T_589 = and(_T_587, _T_588) @[Bitwise.scala 102:75] + node _T_590 = or(_T_585, _T_589) @[Bitwise.scala 102:39] + node _T_591 = bits(_T_583, 13, 0) @[Bitwise.scala 101:28] + node _T_592 = shl(_T_591, 2) @[Bitwise.scala 101:47] + node _T_593 = xor(_T_583, _T_592) @[Bitwise.scala 101:21] + node _T_594 = shr(_T_590, 2) @[Bitwise.scala 102:21] + node _T_595 = and(_T_594, _T_593) @[Bitwise.scala 102:31] + node _T_596 = bits(_T_590, 13, 0) @[Bitwise.scala 102:46] + node _T_597 = shl(_T_596, 2) @[Bitwise.scala 102:65] + node _T_598 = not(_T_593) @[Bitwise.scala 102:77] + node _T_599 = and(_T_597, _T_598) @[Bitwise.scala 102:75] + node _T_600 = or(_T_595, _T_599) @[Bitwise.scala 102:39] + node _T_601 = bits(_T_593, 14, 0) @[Bitwise.scala 101:28] + node _T_602 = shl(_T_601, 1) @[Bitwise.scala 101:47] + node _T_603 = xor(_T_593, _T_602) @[Bitwise.scala 101:21] + node _T_604 = shr(_T_600, 1) @[Bitwise.scala 102:21] + node _T_605 = and(_T_604, _T_603) @[Bitwise.scala 102:31] + node _T_606 = bits(_T_600, 14, 0) @[Bitwise.scala 102:46] + node _T_607 = shl(_T_606, 1) @[Bitwise.scala 102:65] + node _T_608 = not(_T_603) @[Bitwise.scala 102:77] + node _T_609 = and(_T_607, _T_608) @[Bitwise.scala 102:75] + node _T_610 = or(_T_605, _T_609) @[Bitwise.scala 102:39] + node _T_611 = bits(_T_568, 30, 16) @[Bitwise.scala 108:44] + node _T_612 = bits(_T_611, 7, 0) @[Bitwise.scala 108:18] + node _T_615 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 101:47] + node _T_616 = xor(UInt<8>("h0ff"), _T_615) @[Bitwise.scala 101:21] + node _T_617 = shr(_T_612, 4) @[Bitwise.scala 102:21] + node _T_618 = and(_T_617, _T_616) @[Bitwise.scala 102:31] + node _T_619 = bits(_T_612, 3, 0) @[Bitwise.scala 102:46] + node _T_620 = shl(_T_619, 4) @[Bitwise.scala 102:65] + node _T_621 = not(_T_616) @[Bitwise.scala 102:77] + node _T_622 = and(_T_620, _T_621) @[Bitwise.scala 102:75] + node _T_623 = or(_T_618, _T_622) @[Bitwise.scala 102:39] + node _T_624 = bits(_T_616, 5, 0) @[Bitwise.scala 101:28] + node _T_625 = shl(_T_624, 2) @[Bitwise.scala 101:47] + node _T_626 = xor(_T_616, _T_625) @[Bitwise.scala 101:21] + node _T_627 = shr(_T_623, 2) @[Bitwise.scala 102:21] + node _T_628 = and(_T_627, _T_626) @[Bitwise.scala 102:31] + node _T_629 = bits(_T_623, 5, 0) @[Bitwise.scala 102:46] + node _T_630 = shl(_T_629, 2) @[Bitwise.scala 102:65] + node _T_631 = not(_T_626) @[Bitwise.scala 102:77] + node _T_632 = and(_T_630, _T_631) @[Bitwise.scala 102:75] + node _T_633 = or(_T_628, _T_632) @[Bitwise.scala 102:39] + node _T_634 = bits(_T_626, 6, 0) @[Bitwise.scala 101:28] + node _T_635 = shl(_T_634, 1) @[Bitwise.scala 101:47] + node _T_636 = xor(_T_626, _T_635) @[Bitwise.scala 101:21] + node _T_637 = shr(_T_633, 1) @[Bitwise.scala 102:21] + node _T_638 = and(_T_637, _T_636) @[Bitwise.scala 102:31] + node _T_639 = bits(_T_633, 6, 0) @[Bitwise.scala 102:46] + node _T_640 = shl(_T_639, 1) @[Bitwise.scala 102:65] + node _T_641 = not(_T_636) @[Bitwise.scala 102:77] + node _T_642 = and(_T_640, _T_641) @[Bitwise.scala 102:75] + node _T_643 = or(_T_638, _T_642) @[Bitwise.scala 102:39] + node _T_644 = bits(_T_611, 14, 8) @[Bitwise.scala 108:44] + node _T_645 = bits(_T_644, 3, 0) @[Bitwise.scala 108:18] + node _T_646 = bits(_T_645, 1, 0) @[Bitwise.scala 108:18] + node _T_647 = bits(_T_646, 0, 0) @[Bitwise.scala 108:18] + node _T_648 = bits(_T_646, 1, 1) @[Bitwise.scala 108:44] + node _T_649 = cat(_T_647, _T_648) @[Cat.scala 30:58] + node _T_650 = bits(_T_645, 3, 2) @[Bitwise.scala 108:44] + node _T_651 = bits(_T_650, 0, 0) @[Bitwise.scala 108:18] + node _T_652 = bits(_T_650, 1, 1) @[Bitwise.scala 108:44] + node _T_653 = cat(_T_651, _T_652) @[Cat.scala 30:58] + node _T_654 = cat(_T_649, _T_653) @[Cat.scala 30:58] + node _T_655 = bits(_T_644, 6, 4) @[Bitwise.scala 108:44] + node _T_656 = bits(_T_655, 1, 0) @[Bitwise.scala 108:18] + node _T_657 = bits(_T_656, 0, 0) @[Bitwise.scala 108:18] + node _T_658 = bits(_T_656, 1, 1) @[Bitwise.scala 108:44] + node _T_659 = cat(_T_657, _T_658) @[Cat.scala 30:58] + node _T_660 = bits(_T_655, 2, 2) @[Bitwise.scala 108:44] + node _T_661 = cat(_T_659, _T_660) @[Cat.scala 30:58] + node _T_662 = cat(_T_654, _T_661) @[Cat.scala 30:58] + node _T_663 = cat(_T_643, _T_662) @[Cat.scala 30:58] + node _T_664 = cat(_T_610, _T_663) @[Cat.scala 30:58] + node absSigSumExtraMask = cat(_T_664, UInt<1>("h01")) @[Cat.scala 30:58] + node _T_666 = bits(cFirstNormAbsSigSum, 87, 1) @[MulAddRecFN.scala 424:32] + node _T_667 = dshr(_T_666, normTo2ShiftDist) @[MulAddRecFN.scala 424:65] + node _T_668 = bits(cFirstNormAbsSigSum, 31, 0) @[MulAddRecFN.scala 427:39] + node _T_669 = not(_T_668) @[MulAddRecFN.scala 427:19] + node _T_670 = and(_T_669, absSigSumExtraMask) @[MulAddRecFN.scala 427:62] + node _T_672 = eq(_T_670, UInt<1>("h00")) @[MulAddRecFN.scala 428:43] + node _T_673 = bits(cFirstNormAbsSigSum, 31, 0) @[MulAddRecFN.scala 430:38] + node _T_674 = and(_T_673, absSigSumExtraMask) @[MulAddRecFN.scala 430:61] + node _T_676 = neq(_T_674, UInt<1>("h00")) @[MulAddRecFN.scala 431:43] + node _T_677 = mux(doIncrSig, _T_672, _T_676) @[MulAddRecFN.scala 426:16] + node _T_678 = cat(_T_667, _T_677) @[Cat.scala 30:58] + node sigX3 = bits(_T_678, 56, 0) @[MulAddRecFN.scala 434:10] + node _T_679 = bits(sigX3, 56, 55) @[MulAddRecFN.scala 436:29] + node sigX3Shift1 = eq(_T_679, UInt<1>("h00")) @[MulAddRecFN.scala 436:58] + node _T_681 = sub(io.fromPreMul.sExpSum, estNormDist) @[MulAddRecFN.scala 437:40] + node _T_682 = asUInt(_T_681) @[MulAddRecFN.scala 437:40] + node sExpX3 = tail(_T_682, 1) @[MulAddRecFN.scala 437:40] + node _T_683 = bits(sigX3, 56, 54) @[MulAddRecFN.scala 439:25] + node isZeroY = eq(_T_683, UInt<1>("h00")) @[MulAddRecFN.scala 439:54] + node _T_685 = xor(io.fromPreMul.signProd, doNegSignSum) @[MulAddRecFN.scala 444:36] + node signY = mux(isZeroY, signZeroNotEqOpSigns, _T_685) @[MulAddRecFN.scala 442:12] + node sExpX3_13 = bits(sExpX3, 12, 0) @[MulAddRecFN.scala 446:27] + node _T_686 = bits(sExpX3, 13, 13) @[MulAddRecFN.scala 448:34] + node _T_687 = bits(_T_686, 0, 0) @[Bitwise.scala 71:15] + node _T_690 = mux(_T_687, UInt<56>("h0ffffffffffffff"), UInt<56>("h00")) @[Bitwise.scala 71:12] + node _T_691 = not(sExpX3_13) @[primitives.scala 50:21] + node _T_692 = bits(_T_691, 12, 12) @[primitives.scala 56:25] + node _T_693 = bits(_T_691, 11, 0) @[primitives.scala 57:26] + node _T_694 = bits(_T_693, 11, 11) @[primitives.scala 56:25] + node _T_695 = bits(_T_693, 10, 0) @[primitives.scala 57:26] + node _T_696 = bits(_T_695, 10, 10) @[primitives.scala 56:25] + node _T_697 = bits(_T_695, 9, 0) @[primitives.scala 57:26] + node _T_698 = bits(_T_697, 9, 9) @[primitives.scala 56:25] + node _T_699 = bits(_T_697, 8, 0) @[primitives.scala 57:26] + node _T_701 = bits(_T_699, 8, 8) @[primitives.scala 56:25] + node _T_702 = bits(_T_699, 7, 0) @[primitives.scala 57:26] + node _T_704 = bits(_T_702, 7, 7) @[primitives.scala 56:25] + node _T_705 = bits(_T_702, 6, 0) @[primitives.scala 57:26] + node _T_707 = bits(_T_705, 6, 6) @[primitives.scala 56:25] + node _T_708 = bits(_T_705, 5, 0) @[primitives.scala 57:26] + node _T_711 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_708) @[primitives.scala 68:52] + node _T_712 = bits(_T_711, 63, 14) @[primitives.scala 69:26] + node _T_713 = bits(_T_712, 31, 0) @[Bitwise.scala 108:18] + node _T_716 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 101:47] + node _T_717 = xor(UInt<32>("h0ffffffff"), _T_716) @[Bitwise.scala 101:21] + node _T_718 = shr(_T_713, 16) @[Bitwise.scala 102:21] + node _T_719 = and(_T_718, _T_717) @[Bitwise.scala 102:31] + node _T_720 = bits(_T_713, 15, 0) @[Bitwise.scala 102:46] + node _T_721 = shl(_T_720, 16) @[Bitwise.scala 102:65] + node _T_722 = not(_T_717) @[Bitwise.scala 102:77] + node _T_723 = and(_T_721, _T_722) @[Bitwise.scala 102:75] + node _T_724 = or(_T_719, _T_723) @[Bitwise.scala 102:39] + node _T_725 = bits(_T_717, 23, 0) @[Bitwise.scala 101:28] + node _T_726 = shl(_T_725, 8) @[Bitwise.scala 101:47] + node _T_727 = xor(_T_717, _T_726) @[Bitwise.scala 101:21] + node _T_728 = shr(_T_724, 8) @[Bitwise.scala 102:21] + node _T_729 = and(_T_728, _T_727) @[Bitwise.scala 102:31] + node _T_730 = bits(_T_724, 23, 0) @[Bitwise.scala 102:46] + node _T_731 = shl(_T_730, 8) @[Bitwise.scala 102:65] + node _T_732 = not(_T_727) @[Bitwise.scala 102:77] + node _T_733 = and(_T_731, _T_732) @[Bitwise.scala 102:75] + node _T_734 = or(_T_729, _T_733) @[Bitwise.scala 102:39] + node _T_735 = bits(_T_727, 27, 0) @[Bitwise.scala 101:28] + node _T_736 = shl(_T_735, 4) @[Bitwise.scala 101:47] + node _T_737 = xor(_T_727, _T_736) @[Bitwise.scala 101:21] + node _T_738 = shr(_T_734, 4) @[Bitwise.scala 102:21] + node _T_739 = and(_T_738, _T_737) @[Bitwise.scala 102:31] + node _T_740 = bits(_T_734, 27, 0) @[Bitwise.scala 102:46] + node _T_741 = shl(_T_740, 4) @[Bitwise.scala 102:65] + node _T_742 = not(_T_737) @[Bitwise.scala 102:77] + node _T_743 = and(_T_741, _T_742) @[Bitwise.scala 102:75] + node _T_744 = or(_T_739, _T_743) @[Bitwise.scala 102:39] + node _T_745 = bits(_T_737, 29, 0) @[Bitwise.scala 101:28] + node _T_746 = shl(_T_745, 2) @[Bitwise.scala 101:47] + node _T_747 = xor(_T_737, _T_746) @[Bitwise.scala 101:21] + node _T_748 = shr(_T_744, 2) @[Bitwise.scala 102:21] + node _T_749 = and(_T_748, _T_747) @[Bitwise.scala 102:31] + node _T_750 = bits(_T_744, 29, 0) @[Bitwise.scala 102:46] + node _T_751 = shl(_T_750, 2) @[Bitwise.scala 102:65] + node _T_752 = not(_T_747) @[Bitwise.scala 102:77] + node _T_753 = and(_T_751, _T_752) @[Bitwise.scala 102:75] + node _T_754 = or(_T_749, _T_753) @[Bitwise.scala 102:39] + node _T_755 = bits(_T_747, 30, 0) @[Bitwise.scala 101:28] + node _T_756 = shl(_T_755, 1) @[Bitwise.scala 101:47] + node _T_757 = xor(_T_747, _T_756) @[Bitwise.scala 101:21] + node _T_758 = shr(_T_754, 1) @[Bitwise.scala 102:21] + node _T_759 = and(_T_758, _T_757) @[Bitwise.scala 102:31] + node _T_760 = bits(_T_754, 30, 0) @[Bitwise.scala 102:46] + node _T_761 = shl(_T_760, 1) @[Bitwise.scala 102:65] + node _T_762 = not(_T_757) @[Bitwise.scala 102:77] + node _T_763 = and(_T_761, _T_762) @[Bitwise.scala 102:75] + node _T_764 = or(_T_759, _T_763) @[Bitwise.scala 102:39] + node _T_765 = bits(_T_712, 49, 32) @[Bitwise.scala 108:44] + node _T_766 = bits(_T_765, 15, 0) @[Bitwise.scala 108:18] + node _T_769 = shl(UInt<8>("h0ff"), 8) @[Bitwise.scala 101:47] + node _T_770 = xor(UInt<16>("h0ffff"), _T_769) @[Bitwise.scala 101:21] + node _T_771 = shr(_T_766, 8) @[Bitwise.scala 102:21] + node _T_772 = and(_T_771, _T_770) @[Bitwise.scala 102:31] + node _T_773 = bits(_T_766, 7, 0) @[Bitwise.scala 102:46] + node _T_774 = shl(_T_773, 8) @[Bitwise.scala 102:65] + node _T_775 = not(_T_770) @[Bitwise.scala 102:77] + node _T_776 = and(_T_774, _T_775) @[Bitwise.scala 102:75] + node _T_777 = or(_T_772, _T_776) @[Bitwise.scala 102:39] + node _T_778 = bits(_T_770, 11, 0) @[Bitwise.scala 101:28] + node _T_779 = shl(_T_778, 4) @[Bitwise.scala 101:47] + node _T_780 = xor(_T_770, _T_779) @[Bitwise.scala 101:21] + node _T_781 = shr(_T_777, 4) @[Bitwise.scala 102:21] + node _T_782 = and(_T_781, _T_780) @[Bitwise.scala 102:31] + node _T_783 = bits(_T_777, 11, 0) @[Bitwise.scala 102:46] + node _T_784 = shl(_T_783, 4) @[Bitwise.scala 102:65] + node _T_785 = not(_T_780) @[Bitwise.scala 102:77] + node _T_786 = and(_T_784, _T_785) @[Bitwise.scala 102:75] + node _T_787 = or(_T_782, _T_786) @[Bitwise.scala 102:39] + node _T_788 = bits(_T_780, 13, 0) @[Bitwise.scala 101:28] + node _T_789 = shl(_T_788, 2) @[Bitwise.scala 101:47] + node _T_790 = xor(_T_780, _T_789) @[Bitwise.scala 101:21] + node _T_791 = shr(_T_787, 2) @[Bitwise.scala 102:21] + node _T_792 = and(_T_791, _T_790) @[Bitwise.scala 102:31] + node _T_793 = bits(_T_787, 13, 0) @[Bitwise.scala 102:46] + node _T_794 = shl(_T_793, 2) @[Bitwise.scala 102:65] + node _T_795 = not(_T_790) @[Bitwise.scala 102:77] + node _T_796 = and(_T_794, _T_795) @[Bitwise.scala 102:75] + node _T_797 = or(_T_792, _T_796) @[Bitwise.scala 102:39] + node _T_798 = bits(_T_790, 14, 0) @[Bitwise.scala 101:28] + node _T_799 = shl(_T_798, 1) @[Bitwise.scala 101:47] + node _T_800 = xor(_T_790, _T_799) @[Bitwise.scala 101:21] + node _T_801 = shr(_T_797, 1) @[Bitwise.scala 102:21] + node _T_802 = and(_T_801, _T_800) @[Bitwise.scala 102:31] + node _T_803 = bits(_T_797, 14, 0) @[Bitwise.scala 102:46] + node _T_804 = shl(_T_803, 1) @[Bitwise.scala 102:65] + node _T_805 = not(_T_800) @[Bitwise.scala 102:77] + node _T_806 = and(_T_804, _T_805) @[Bitwise.scala 102:75] + node _T_807 = or(_T_802, _T_806) @[Bitwise.scala 102:39] + node _T_808 = bits(_T_765, 17, 16) @[Bitwise.scala 108:44] + node _T_809 = bits(_T_808, 0, 0) @[Bitwise.scala 108:18] + node _T_810 = bits(_T_808, 1, 1) @[Bitwise.scala 108:44] + node _T_811 = cat(_T_809, _T_810) @[Cat.scala 30:58] + node _T_812 = cat(_T_807, _T_811) @[Cat.scala 30:58] + node _T_813 = cat(_T_764, _T_812) @[Cat.scala 30:58] + node _T_814 = not(_T_813) @[primitives.scala 65:36] + node _T_815 = mux(_T_707, UInt<1>("h00"), _T_814) @[primitives.scala 65:21] + node _T_816 = not(_T_815) @[primitives.scala 65:17] + node _T_817 = not(_T_816) @[primitives.scala 65:36] + node _T_818 = mux(_T_704, UInt<1>("h00"), _T_817) @[primitives.scala 65:21] + node _T_819 = not(_T_818) @[primitives.scala 65:17] + node _T_820 = not(_T_819) @[primitives.scala 65:36] + node _T_821 = mux(_T_701, UInt<1>("h00"), _T_820) @[primitives.scala 65:21] + node _T_822 = not(_T_821) @[primitives.scala 65:17] + node _T_823 = not(_T_822) @[primitives.scala 65:36] + node _T_824 = mux(_T_698, UInt<1>("h00"), _T_823) @[primitives.scala 65:21] + node _T_825 = not(_T_824) @[primitives.scala 65:17] + node _T_827 = cat(_T_825, UInt<4>("h0f")) @[Cat.scala 30:58] + node _T_828 = bits(_T_697, 9, 9) @[primitives.scala 56:25] + node _T_829 = bits(_T_697, 8, 0) @[primitives.scala 57:26] + node _T_830 = bits(_T_829, 8, 8) @[primitives.scala 56:25] + node _T_831 = bits(_T_829, 7, 0) @[primitives.scala 57:26] + node _T_832 = bits(_T_831, 7, 7) @[primitives.scala 56:25] + node _T_833 = bits(_T_831, 6, 0) @[primitives.scala 57:26] + node _T_834 = bits(_T_833, 6, 6) @[primitives.scala 56:25] + node _T_835 = bits(_T_833, 5, 0) @[primitives.scala 57:26] + node _T_837 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_835) @[primitives.scala 68:52] + node _T_838 = bits(_T_837, 3, 0) @[primitives.scala 69:26] + node _T_839 = bits(_T_838, 1, 0) @[Bitwise.scala 108:18] + node _T_840 = bits(_T_839, 0, 0) @[Bitwise.scala 108:18] + node _T_841 = bits(_T_839, 1, 1) @[Bitwise.scala 108:44] + node _T_842 = cat(_T_840, _T_841) @[Cat.scala 30:58] + node _T_843 = bits(_T_838, 3, 2) @[Bitwise.scala 108:44] + node _T_844 = bits(_T_843, 0, 0) @[Bitwise.scala 108:18] + node _T_845 = bits(_T_843, 1, 1) @[Bitwise.scala 108:44] + node _T_846 = cat(_T_844, _T_845) @[Cat.scala 30:58] + node _T_847 = cat(_T_842, _T_846) @[Cat.scala 30:58] + node _T_849 = mux(_T_834, _T_847, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_851 = mux(_T_832, _T_849, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_853 = mux(_T_830, _T_851, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_855 = mux(_T_828, _T_853, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_856 = mux(_T_696, _T_827, _T_855) @[primitives.scala 61:20] + node _T_858 = mux(_T_694, _T_856, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_860 = mux(_T_692, _T_858, UInt<1>("h00")) @[primitives.scala 59:20] + node _T_861 = bits(sigX3, 55, 55) @[MulAddRecFN.scala 450:26] + node _T_862 = or(_T_860, _T_861) @[MulAddRecFN.scala 449:75] + node _T_864 = cat(_T_862, UInt<2>("h03")) @[Cat.scala 30:58] + node roundMask = or(_T_690, _T_864) @[MulAddRecFN.scala 448:50] + node _T_865 = shr(roundMask, 1) @[MulAddRecFN.scala 454:35] + node _T_866 = not(_T_865) @[MulAddRecFN.scala 454:24] + node roundPosMask = and(_T_866, roundMask) @[MulAddRecFN.scala 454:40] + node _T_867 = and(sigX3, roundPosMask) @[MulAddRecFN.scala 455:30] + node roundPosBit = neq(_T_867, UInt<1>("h00")) @[MulAddRecFN.scala 455:46] + node _T_869 = shr(roundMask, 1) @[MulAddRecFN.scala 456:45] + node _T_870 = and(sigX3, _T_869) @[MulAddRecFN.scala 456:34] + node anyRoundExtra = neq(_T_870, UInt<1>("h00")) @[MulAddRecFN.scala 456:50] + node _T_872 = not(sigX3) @[MulAddRecFN.scala 457:27] + node _T_873 = shr(roundMask, 1) @[MulAddRecFN.scala 457:45] + node _T_874 = and(_T_872, _T_873) @[MulAddRecFN.scala 457:34] + node allRoundExtra = eq(_T_874, UInt<1>("h00")) @[MulAddRecFN.scala 457:50] + node anyRound = or(roundPosBit, anyRoundExtra) @[MulAddRecFN.scala 458:32] + node allRound = and(roundPosBit, allRoundExtra) @[MulAddRecFN.scala 459:32] + node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) @[MulAddRecFN.scala 460:28] + node _T_877 = eq(doIncrSig, UInt<1>("h00")) @[MulAddRecFN.scala 462:10] + node _T_878 = and(_T_877, roundingMode_nearest_even) @[MulAddRecFN.scala 462:22] + node _T_879 = and(_T_878, roundPosBit) @[MulAddRecFN.scala 462:51] + node _T_880 = and(_T_879, anyRoundExtra) @[MulAddRecFN.scala 463:60] + node _T_882 = eq(doIncrSig, UInt<1>("h00")) @[MulAddRecFN.scala 464:10] + node _T_883 = and(_T_882, roundDirectUp) @[MulAddRecFN.scala 464:22] + node _T_884 = and(_T_883, anyRound) @[MulAddRecFN.scala 464:49] + node _T_885 = or(_T_880, _T_884) @[MulAddRecFN.scala 463:78] + node _T_886 = and(doIncrSig, allRound) @[MulAddRecFN.scala 465:49] + node _T_887 = or(_T_885, _T_886) @[MulAddRecFN.scala 464:65] + node _T_888 = and(doIncrSig, roundingMode_nearest_even) @[MulAddRecFN.scala 466:20] + node _T_889 = and(_T_888, roundPosBit) @[MulAddRecFN.scala 466:49] + node _T_890 = or(_T_887, _T_889) @[MulAddRecFN.scala 465:65] + node _T_891 = and(doIncrSig, roundDirectUp) @[MulAddRecFN.scala 467:20] + node _T_893 = and(_T_891, UInt<1>("h01")) @[MulAddRecFN.scala 467:49] + node roundUp = or(_T_890, _T_893) @[MulAddRecFN.scala 466:65] + node _T_895 = eq(roundPosBit, UInt<1>("h00")) @[MulAddRecFN.scala 470:42] + node _T_896 = and(roundingMode_nearest_even, _T_895) @[MulAddRecFN.scala 470:39] + node _T_897 = and(_T_896, allRoundExtra) @[MulAddRecFN.scala 470:56] + node _T_898 = and(roundingMode_nearest_even, roundPosBit) @[MulAddRecFN.scala 471:39] + node _T_900 = eq(anyRoundExtra, UInt<1>("h00")) @[MulAddRecFN.scala 471:59] + node _T_901 = and(_T_898, _T_900) @[MulAddRecFN.scala 471:56] + node roundEven = mux(doIncrSig, _T_897, _T_901) @[MulAddRecFN.scala 469:12] + node _T_903 = eq(allRound, UInt<1>("h00")) @[MulAddRecFN.scala 473:39] + node inexactY = mux(doIncrSig, _T_903, anyRound) @[MulAddRecFN.scala 473:27] + node _T_904 = or(sigX3, roundMask) @[MulAddRecFN.scala 475:18] + node _T_905 = shr(_T_904, 2) @[MulAddRecFN.scala 475:30] + node _T_907 = add(_T_905, UInt<1>("h01")) @[MulAddRecFN.scala 475:35] + node _T_908 = tail(_T_907, 1) @[MulAddRecFN.scala 475:35] + node roundUp_sigY3 = bits(_T_908, 54, 0) @[MulAddRecFN.scala 475:45] + node _T_910 = eq(roundUp, UInt<1>("h00")) @[MulAddRecFN.scala 477:13] + node _T_912 = eq(roundEven, UInt<1>("h00")) @[MulAddRecFN.scala 477:26] + node _T_913 = and(_T_910, _T_912) @[MulAddRecFN.scala 477:23] + node _T_914 = not(roundMask) @[MulAddRecFN.scala 477:48] + node _T_915 = and(sigX3, _T_914) @[MulAddRecFN.scala 477:46] + node _T_916 = shr(_T_915, 2) @[MulAddRecFN.scala 477:59] + node _T_918 = mux(_T_913, _T_916, UInt<1>("h00")) @[MulAddRecFN.scala 477:12] + node _T_920 = mux(roundUp, roundUp_sigY3, UInt<1>("h00")) @[MulAddRecFN.scala 478:12] + node _T_921 = or(_T_918, _T_920) @[MulAddRecFN.scala 477:79] + node _T_922 = shr(roundMask, 1) @[MulAddRecFN.scala 479:64] + node _T_923 = not(_T_922) @[MulAddRecFN.scala 479:53] + node _T_924 = and(roundUp_sigY3, _T_923) @[MulAddRecFN.scala 479:51] + node _T_926 = mux(roundEven, _T_924, UInt<1>("h00")) @[MulAddRecFN.scala 479:12] + node sigY3 = or(_T_921, _T_926) @[MulAddRecFN.scala 478:79] + node _T_927 = bits(sigY3, 54, 54) @[MulAddRecFN.scala 482:18] + node _T_929 = add(sExpX3, UInt<1>("h01")) @[MulAddRecFN.scala 482:41] + node _T_930 = tail(_T_929, 1) @[MulAddRecFN.scala 482:41] + node _T_932 = mux(_T_927, _T_930, UInt<1>("h00")) @[MulAddRecFN.scala 482:12] + node _T_933 = bits(sigY3, 53, 53) @[MulAddRecFN.scala 483:18] + node _T_935 = mux(_T_933, sExpX3, UInt<1>("h00")) @[MulAddRecFN.scala 483:12] + node _T_936 = or(_T_932, _T_935) @[MulAddRecFN.scala 482:61] + node _T_937 = bits(sigY3, 54, 53) @[MulAddRecFN.scala 484:19] + node _T_939 = eq(_T_937, UInt<1>("h00")) @[MulAddRecFN.scala 484:44] + node _T_941 = sub(sExpX3, UInt<1>("h01")) @[MulAddRecFN.scala 485:20] + node _T_942 = asUInt(_T_941) @[MulAddRecFN.scala 485:20] + node _T_943 = tail(_T_942, 1) @[MulAddRecFN.scala 485:20] + node _T_945 = mux(_T_939, _T_943, UInt<1>("h00")) @[MulAddRecFN.scala 484:12] + node sExpY = or(_T_936, _T_945) @[MulAddRecFN.scala 483:61] + node expY = bits(sExpY, 11, 0) @[MulAddRecFN.scala 488:21] + node _T_946 = bits(sigY3, 51, 0) @[MulAddRecFN.scala 490:31] + node _T_947 = bits(sigY3, 52, 1) @[MulAddRecFN.scala 490:55] + node fractY = mux(sigX3Shift1, _T_946, _T_947) @[MulAddRecFN.scala 490:12] + node _T_948 = bits(sExpY, 12, 10) @[MulAddRecFN.scala 492:27] + node overflowY = eq(_T_948, UInt<2>("h03")) @[MulAddRecFN.scala 492:56] + node _T_951 = eq(isZeroY, UInt<1>("h00")) @[MulAddRecFN.scala 495:9] + node _T_952 = bits(sExpY, 12, 12) @[MulAddRecFN.scala 496:19] + node _T_953 = bits(sExpY, 11, 0) @[MulAddRecFN.scala 496:43] + node _T_955 = lt(_T_953, UInt<10>("h03ce")) @[MulAddRecFN.scala 496:57] + node _T_956 = or(_T_952, _T_955) @[MulAddRecFN.scala 496:34] + node totalUnderflowY = and(_T_951, _T_956) @[MulAddRecFN.scala 495:19] + node _T_957 = bits(sExpX3, 13, 13) @[MulAddRecFN.scala 499:20] + node _T_960 = mux(sigX3Shift1, UInt<11>("h0402"), UInt<11>("h0401")) @[MulAddRecFN.scala 501:26] + node _T_961 = leq(sExpX3_13, _T_960) @[MulAddRecFN.scala 500:29] + node _T_962 = or(_T_957, _T_961) @[MulAddRecFN.scala 499:35] + node underflowY = and(inexactY, _T_962) @[MulAddRecFN.scala 498:22] + node _T_963 = and(roundingMode_min, signY) @[MulAddRecFN.scala 506:27] + node _T_965 = eq(signY, UInt<1>("h00")) @[MulAddRecFN.scala 506:61] + node _T_966 = and(roundingMode_max, _T_965) @[MulAddRecFN.scala 506:58] + node roundMagUp = or(_T_963, _T_966) @[MulAddRecFN.scala 506:37] + node overflowY_roundMagUp = or(roundingMode_nearest_even, roundMagUp) @[MulAddRecFN.scala 507:58] + node mulSpecial = or(isSpecialA, isSpecialB) @[MulAddRecFN.scala 511:33] + node addSpecial = or(mulSpecial, isSpecialC) @[MulAddRecFN.scala 512:33] + node notSpecial_addZeros = and(io.fromPreMul.isZeroProd, isZeroC) @[MulAddRecFN.scala 513:56] + node _T_968 = eq(addSpecial, UInt<1>("h00")) @[MulAddRecFN.scala 514:22] + node _T_970 = eq(notSpecial_addZeros, UInt<1>("h00")) @[MulAddRecFN.scala 514:38] + node commonCase = and(_T_968, _T_970) @[MulAddRecFN.scala 514:35] + node _T_971 = and(isInfA, isZeroB) @[MulAddRecFN.scala 517:17] + node _T_972 = and(isZeroA, isInfB) @[MulAddRecFN.scala 517:41] + node _T_973 = or(_T_971, _T_972) @[MulAddRecFN.scala 517:29] + node _T_975 = eq(isNaNA, UInt<1>("h00")) @[MulAddRecFN.scala 518:14] + node _T_977 = eq(isNaNB, UInt<1>("h00")) @[MulAddRecFN.scala 518:26] + node _T_978 = and(_T_975, _T_977) @[MulAddRecFN.scala 518:23] + node _T_979 = or(isInfA, isInfB) @[MulAddRecFN.scala 518:46] + node _T_980 = and(_T_978, _T_979) @[MulAddRecFN.scala 518:35] + node _T_981 = and(_T_980, isInfC) @[MulAddRecFN.scala 518:57] + node _T_982 = and(_T_981, doSubMags) @[MulAddRecFN.scala 518:67] + node notSigNaN_invalid = or(_T_973, _T_982) @[MulAddRecFN.scala 517:52] + node _T_983 = or(isSigNaNA, isSigNaNB) @[MulAddRecFN.scala 519:29] + node _T_984 = or(_T_983, isSigNaNC) @[MulAddRecFN.scala 519:42] + node invalid = or(_T_984, notSigNaN_invalid) @[MulAddRecFN.scala 519:55] + node overflow = and(commonCase, overflowY) @[MulAddRecFN.scala 520:32] + node underflow = and(commonCase, underflowY) @[MulAddRecFN.scala 521:32] + node _T_985 = and(commonCase, inexactY) @[MulAddRecFN.scala 522:43] + node inexact = or(overflow, _T_985) @[MulAddRecFN.scala 522:28] + node _T_986 = or(notSpecial_addZeros, isZeroY) @[MulAddRecFN.scala 525:29] + node notSpecial_isZeroOut = or(_T_986, totalUnderflowY) @[MulAddRecFN.scala 525:40] + node _T_987 = and(commonCase, totalUnderflowY) @[MulAddRecFN.scala 526:41] + node pegMinFiniteMagOut = and(_T_987, roundMagUp) @[MulAddRecFN.scala 526:60] + node _T_989 = eq(overflowY_roundMagUp, UInt<1>("h00")) @[MulAddRecFN.scala 527:42] + node pegMaxFiniteMagOut = and(overflow, _T_989) @[MulAddRecFN.scala 527:39] + node _T_990 = or(isInfA, isInfB) @[MulAddRecFN.scala 529:16] + node _T_991 = or(_T_990, isInfC) @[MulAddRecFN.scala 529:26] + node _T_992 = and(overflow, overflowY_roundMagUp) @[MulAddRecFN.scala 529:49] + node notNaN_isInfOut = or(_T_991, _T_992) @[MulAddRecFN.scala 529:36] + node _T_993 = or(isNaNA, isNaNB) @[MulAddRecFN.scala 530:27] + node _T_994 = or(_T_993, isNaNC) @[MulAddRecFN.scala 530:37] + node isNaNOut = or(_T_994, notSigNaN_invalid) @[MulAddRecFN.scala 530:47] + node _T_996 = eq(doSubMags, UInt<1>("h00")) @[MulAddRecFN.scala 533:10] + node _T_997 = and(_T_996, io.fromPreMul.opSignC) @[MulAddRecFN.scala 533:51] + node _T_999 = eq(isSpecialC, UInt<1>("h00")) @[MulAddRecFN.scala 534:24] + node _T_1000 = and(mulSpecial, _T_999) @[MulAddRecFN.scala 534:21] + node _T_1001 = and(_T_1000, io.fromPreMul.signProd) @[MulAddRecFN.scala 534:51] + node _T_1002 = or(_T_997, _T_1001) @[MulAddRecFN.scala 533:78] + node _T_1004 = eq(mulSpecial, UInt<1>("h00")) @[MulAddRecFN.scala 535:10] + node _T_1005 = and(_T_1004, isSpecialC) @[MulAddRecFN.scala 535:23] + node _T_1006 = and(_T_1005, io.fromPreMul.opSignC) @[MulAddRecFN.scala 535:51] + node _T_1007 = or(_T_1002, _T_1006) @[MulAddRecFN.scala 534:78] + node _T_1009 = eq(mulSpecial, UInt<1>("h00")) @[MulAddRecFN.scala 536:10] + node _T_1010 = and(_T_1009, notSpecial_addZeros) @[MulAddRecFN.scala 536:23] + node _T_1011 = and(_T_1010, doSubMags) @[MulAddRecFN.scala 536:46] + node _T_1012 = and(_T_1011, signZeroNotEqOpSigns) @[MulAddRecFN.scala 536:59] + node uncommonCaseSignOut = or(_T_1007, _T_1012) @[MulAddRecFN.scala 535:78] + node _T_1014 = eq(isNaNOut, UInt<1>("h00")) @[MulAddRecFN.scala 538:20] + node _T_1015 = and(_T_1014, uncommonCaseSignOut) @[MulAddRecFN.scala 538:31] + node _T_1016 = and(commonCase, signY) @[MulAddRecFN.scala 538:70] + node signOut = or(_T_1015, _T_1016) @[MulAddRecFN.scala 538:55] + node _T_1019 = mux(notSpecial_isZeroOut, UInt<12>("h0e00"), UInt<12>("h00")) @[MulAddRecFN.scala 541:18] + node _T_1020 = not(_T_1019) @[MulAddRecFN.scala 541:14] + node _T_1021 = and(expY, _T_1020) @[MulAddRecFN.scala 540:15] + node _T_1023 = not(UInt<12>("h03ce")) @[MulAddRecFN.scala 546:19] + node _T_1025 = mux(pegMinFiniteMagOut, _T_1023, UInt<12>("h00")) @[MulAddRecFN.scala 545:18] + node _T_1026 = not(_T_1025) @[MulAddRecFN.scala 545:14] + node _T_1027 = and(_T_1021, _T_1026) @[MulAddRecFN.scala 544:17] + node _T_1030 = mux(pegMaxFiniteMagOut, UInt<12>("h0400"), UInt<12>("h00")) @[MulAddRecFN.scala 549:18] + node _T_1031 = not(_T_1030) @[MulAddRecFN.scala 549:14] + node _T_1032 = and(_T_1027, _T_1031) @[MulAddRecFN.scala 548:17] + node _T_1035 = mux(notNaN_isInfOut, UInt<10>("h0200"), UInt<12>("h00")) @[MulAddRecFN.scala 553:18] + node _T_1036 = not(_T_1035) @[MulAddRecFN.scala 553:14] + node _T_1037 = and(_T_1032, _T_1036) @[MulAddRecFN.scala 552:17] + node _T_1040 = mux(pegMinFiniteMagOut, UInt<10>("h03ce"), UInt<12>("h00")) @[MulAddRecFN.scala 557:16] + node _T_1041 = or(_T_1037, _T_1040) @[MulAddRecFN.scala 556:18] + node _T_1044 = mux(pegMaxFiniteMagOut, UInt<12>("h0bff"), UInt<12>("h00")) @[MulAddRecFN.scala 558:16] + node _T_1045 = or(_T_1041, _T_1044) @[MulAddRecFN.scala 557:74] + node _T_1048 = mux(notNaN_isInfOut, UInt<12>("h0c00"), UInt<12>("h00")) @[MulAddRecFN.scala 562:16] + node _T_1049 = or(_T_1045, _T_1048) @[MulAddRecFN.scala 561:15] + node _T_1052 = mux(isNaNOut, UInt<12>("h0e00"), UInt<12>("h00")) @[MulAddRecFN.scala 566:16] + node expOut = or(_T_1049, _T_1052) @[MulAddRecFN.scala 565:15] + node _T_1053 = and(totalUnderflowY, roundMagUp) @[MulAddRecFN.scala 568:30] + node _T_1054 = or(_T_1053, isNaNOut) @[MulAddRecFN.scala 568:45] + node _T_1056 = shl(UInt<1>("h01"), 51) @[MulAddRecFN.scala 569:34] + node _T_1058 = mux(isNaNOut, _T_1056, UInt<1>("h00")) @[MulAddRecFN.scala 569:16] + node _T_1059 = mux(_T_1054, _T_1058, fractY) @[MulAddRecFN.scala 568:12] + node _T_1060 = bits(pegMaxFiniteMagOut, 0, 0) @[Bitwise.scala 71:15] + node _T_1063 = mux(_T_1060, UInt<52>("h0fffffffffffff"), UInt<52>("h00")) @[Bitwise.scala 71:12] + node fractOut = or(_T_1059, _T_1063) @[MulAddRecFN.scala 571:11] + node _T_1064 = cat(signOut, expOut) @[Cat.scala 30:58] + node _T_1065 = cat(_T_1064, fractOut) @[Cat.scala 30:58] + io.out <= _T_1065 @[MulAddRecFN.scala 574:12] + node _T_1067 = cat(underflow, inexact) @[Cat.scala 30:58] + node _T_1068 = cat(invalid, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_1069 = cat(_T_1068, overflow) @[Cat.scala 30:58] + node _T_1070 = cat(_T_1069, _T_1067) @[Cat.scala 30:58] + io.exceptionFlags <= _T_1070 @[MulAddRecFN.scala 575:23] + diff --git a/regress/ICache.fir b/regress/ICache.fir new file mode 100644 index 00000000..d848982e --- /dev/null +++ b/regress/ICache.fir @@ -0,0 +1,569 @@ +circuit ICache : + module ICache : + input clock : Clock + input reset : UInt<1> + output io : {flip req : {valid : UInt<1>, bits : {addr : UInt<39>}}, flip s1_paddr : UInt<32>, flip s1_kill : UInt<1>, flip s2_kill : UInt<1>, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<16>, datablock : UInt<64>}}, flip invalidate : UInt<1>, mem : {0 : {a : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>}}, c : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, data : UInt<64>, error : UInt<1>}}, flip d : {flip ready : UInt<1>, valid : UInt<1>, bits : {opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, addr_lo : UInt<3>, data : UInt<64>, error : UInt<1>}}, e : {flip ready : UInt<1>, valid : UInt<1>, bits : {sink : UInt<4>}}}}} + + io is invalid + io is invalid + reg state : UInt<2>, clock with : (reset => (reset, UInt<2>("h00"))) @[ICache.scala 67:18] + reg invalidated : UInt<1>, clock @[ICache.scala 68:24] + node stall = eq(io.resp.ready, UInt<1>("h00")) @[ICache.scala 69:15] + reg refill_addr : UInt<32>, clock @[ICache.scala 71:24] + wire s1_any_tag_hit : UInt<1> @[ICache.scala 72:28] + s1_any_tag_hit is invalid @[ICache.scala 72:28] + reg s1_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[ICache.scala 74:21] + node _T_221 = eq(io.s1_kill, UInt<1>("h00")) @[ICache.scala 75:31] + node _T_222 = and(s1_valid, _T_221) @[ICache.scala 75:28] + node _T_223 = eq(state, UInt<2>("h00")) @[ICache.scala 75:52] + node out_valid = and(_T_222, _T_223) @[ICache.scala 75:43] + node s1_idx = bits(io.s1_paddr, 11, 6) @[ICache.scala 76:27] + node s1_tag = bits(io.s1_paddr, 31, 12) @[ICache.scala 77:27] + node s1_hit = and(out_valid, s1_any_tag_hit) @[ICache.scala 78:26] + node _T_225 = eq(s1_any_tag_hit, UInt<1>("h00")) @[ICache.scala 79:30] + node s1_miss = and(out_valid, _T_225) @[ICache.scala 79:27] + node _T_226 = eq(state, UInt<2>("h00")) @[ICache.scala 81:40] + node _T_227 = and(io.req.valid, _T_226) @[ICache.scala 81:31] + node _T_228 = and(out_valid, stall) @[ICache.scala 81:67] + node _T_230 = eq(_T_228, UInt<1>("h00")) @[ICache.scala 81:55] + node s0_valid = and(_T_227, _T_230) @[ICache.scala 81:52] + node _T_231 = and(out_valid, stall) @[ICache.scala 84:37] + node _T_232 = or(s0_valid, _T_231) @[ICache.scala 84:24] + s1_valid <= _T_232 @[ICache.scala 84:12] + node _T_233 = eq(state, UInt<2>("h00")) @[ICache.scala 86:26] + node _T_234 = and(s1_miss, _T_233) @[ICache.scala 86:17] + when _T_234 : @[ICache.scala 86:39] + refill_addr <= io.s1_paddr @[ICache.scala 87:17] + skip @[ICache.scala 86:39] + node refill_tag = bits(refill_addr, 31, 12) @[ICache.scala 89:31] + node refill_idx = bits(refill_addr, 11, 6) @[ICache.scala 90:31] + node _T_235 = and(io.mem.0.d.ready, io.mem.0.d.valid) @[Decoupled.scala 30:37] + node _T_237 = asUInt(asSInt(UInt<8>("h0ff"))) @[package.scala 19:64] + node _T_238 = dshl(_T_237, io.mem.0.d.bits.size) @[package.scala 19:71] + node _T_239 = bits(_T_238, 7, 0) @[package.scala 19:76] + node _T_240 = not(_T_239) @[package.scala 19:40] + node _T_241 = shr(_T_240, 3) @[Edges.scala 198:59] + node _T_242 = bits(io.mem.0.d.bits.opcode, 0, 0) @[Edges.scala 90:36] + node _T_244 = mux(_T_242, _T_241, UInt<1>("h00")) @[Edges.scala 199:14] + reg _T_246 : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Reg.scala 26:44] + node _T_248 = sub(_T_246, UInt<1>("h01")) @[Edges.scala 208:28] + node _T_249 = asUInt(_T_248) @[Edges.scala 208:28] + node _T_250 = tail(_T_249, 1) @[Edges.scala 208:28] + node _T_252 = eq(_T_246, UInt<1>("h00")) @[Edges.scala 209:25] + node _T_254 = eq(_T_246, UInt<1>("h01")) @[Edges.scala 210:25] + node _T_256 = eq(_T_244, UInt<1>("h00")) @[Edges.scala 210:47] + node _T_257 = or(_T_254, _T_256) @[Edges.scala 210:37] + node refill_done = and(_T_257, _T_235) @[Edges.scala 211:22] + node _T_258 = not(_T_250) @[Edges.scala 212:27] + node refill_cnt = and(_T_244, _T_258) @[Edges.scala 212:25] + when _T_235 : @[Edges.scala 213:17] + node _T_259 = mux(_T_252, _T_244, _T_250) @[Edges.scala 214:21] + _T_246 <= _T_259 @[Edges.scala 214:15] + skip @[Edges.scala 213:17] + io.mem.0.d.ready <= UInt<1>("h01") @[ICache.scala 92:18] + reg _T_262 : UInt<16>, clock with : (reset => (reset, UInt<16>("h01"))) @[LFSR.scala 22:19] + when s1_miss : @[LFSR.scala 23:22] + node _T_263 = bits(_T_262, 0, 0) @[LFSR.scala 23:40] + node _T_264 = bits(_T_262, 2, 2) @[LFSR.scala 23:48] + node _T_265 = xor(_T_263, _T_264) @[LFSR.scala 23:43] + node _T_266 = bits(_T_262, 3, 3) @[LFSR.scala 23:56] + node _T_267 = xor(_T_265, _T_266) @[LFSR.scala 23:51] + node _T_268 = bits(_T_262, 5, 5) @[LFSR.scala 23:64] + node _T_269 = xor(_T_267, _T_268) @[LFSR.scala 23:59] + node _T_270 = bits(_T_262, 15, 1) @[LFSR.scala 23:73] + node _T_271 = cat(_T_269, _T_270) @[Cat.scala 30:58] + _T_262 <= _T_271 @[LFSR.scala 23:29] + skip @[LFSR.scala 23:22] + node repl_way = bits(_T_262, 1, 0) @[ICache.scala 95:56] + smem tag_array : UInt<20>[4][64] @[ICache.scala 97:25] + node _T_282 = bits(io.req.bits.addr, 11, 6) @[ICache.scala 98:42] + node _T_284 = eq(refill_done, UInt<1>("h00")) @[ICache.scala 98:70] + node _T_285 = and(_T_284, s0_valid) @[ICache.scala 98:83] + wire _T_287 : UInt + _T_287 is invalid + when _T_285 : + _T_287 <= _T_282 + node _T_289 = or(_T_287, UInt<6>("h00")) + node _T_290 = bits(_T_289, 5, 0) + read mport tag_rdata = tag_array[_T_290], clock + skip + when refill_done : @[ICache.scala 99:22] + wire _T_304 : UInt<20>[4] @[ICache.scala 101:48] + _T_304 is invalid @[ICache.scala 101:48] + _T_304[0] <= refill_tag @[ICache.scala 101:48] + _T_304[1] <= refill_tag @[ICache.scala 101:48] + _T_304[2] <= refill_tag @[ICache.scala 101:48] + _T_304[3] <= refill_tag @[ICache.scala 101:48] + node _T_312 = eq(repl_way, UInt<1>("h00")) @[ICache.scala 101:84] + node _T_314 = eq(repl_way, UInt<1>("h01")) @[ICache.scala 101:84] + node _T_316 = eq(repl_way, UInt<2>("h02")) @[ICache.scala 101:84] + node _T_318 = eq(repl_way, UInt<2>("h03")) @[ICache.scala 101:84] + wire _T_321 : UInt<1>[4] @[ICache.scala 101:74] + _T_321 is invalid @[ICache.scala 101:74] + _T_321[0] <= _T_312 @[ICache.scala 101:74] + _T_321[1] <= _T_314 @[ICache.scala 101:74] + _T_321[2] <= _T_316 @[ICache.scala 101:74] + _T_321[3] <= _T_318 @[ICache.scala 101:74] + write mport _T_328 = tag_array[refill_idx], clock + when _T_321[0] : + _T_328[0] <= _T_304[0] + skip + when _T_321[1] : + _T_328[1] <= _T_304[1] + skip + when _T_321[2] : + _T_328[2] <= _T_304[2] + skip + when _T_321[3] : + _T_328[3] <= _T_304[3] + skip + skip @[ICache.scala 99:22] + reg vb_array : UInt<256>, clock with : (reset => (reset, UInt<256>("h00"))) @[ICache.scala 104:21] + node _T_342 = eq(invalidated, UInt<1>("h00")) @[ICache.scala 105:24] + node _T_343 = and(refill_done, _T_342) @[ICache.scala 105:21] + when _T_343 : @[ICache.scala 105:38] + node _T_344 = cat(repl_way, refill_idx) @[Cat.scala 30:58] + node _T_347 = dshl(UInt<1>("h01"), _T_344) @[ICache.scala 106:32] + node _T_348 = or(vb_array, _T_347) @[ICache.scala 106:32] + node _T_349 = not(vb_array) @[ICache.scala 106:32] + node _T_350 = or(_T_349, _T_347) @[ICache.scala 106:32] + node _T_351 = not(_T_350) @[ICache.scala 106:32] + node _T_352 = mux(UInt<1>("h01"), _T_348, _T_351) @[ICache.scala 106:32] + vb_array <= _T_352 @[ICache.scala 106:14] + skip @[ICache.scala 105:38] + when io.invalidate : @[ICache.scala 108:24] + vb_array <= UInt<1>("h00") @[ICache.scala 109:14] + invalidated <= UInt<1>("h01") @[ICache.scala 110:17] + skip @[ICache.scala 108:24] + wire s1_disparity : UInt<1>[4] @[ICache.scala 112:26] + s1_disparity is invalid @[ICache.scala 112:26] + node _T_364 = and(s1_valid, s1_disparity[0]) @[ICache.scala 114:20] + when _T_364 : @[ICache.scala 114:40] + node _T_366 = cat(UInt<1>("h00"), s1_idx) @[Cat.scala 30:58] + node _T_369 = dshl(UInt<1>("h01"), _T_366) @[ICache.scala 114:69] + node _T_370 = or(vb_array, _T_369) @[ICache.scala 114:69] + node _T_371 = not(vb_array) @[ICache.scala 114:69] + node _T_372 = or(_T_371, _T_369) @[ICache.scala 114:69] + node _T_373 = not(_T_372) @[ICache.scala 114:69] + node _T_374 = mux(UInt<1>("h00"), _T_370, _T_373) @[ICache.scala 114:69] + vb_array <= _T_374 @[ICache.scala 114:51] + skip @[ICache.scala 114:40] + node _T_375 = and(s1_valid, s1_disparity[1]) @[ICache.scala 114:20] + when _T_375 : @[ICache.scala 114:40] + node _T_377 = cat(UInt<1>("h01"), s1_idx) @[Cat.scala 30:58] + node _T_380 = dshl(UInt<1>("h01"), _T_377) @[ICache.scala 114:69] + node _T_381 = or(vb_array, _T_380) @[ICache.scala 114:69] + node _T_382 = not(vb_array) @[ICache.scala 114:69] + node _T_383 = or(_T_382, _T_380) @[ICache.scala 114:69] + node _T_384 = not(_T_383) @[ICache.scala 114:69] + node _T_385 = mux(UInt<1>("h00"), _T_381, _T_384) @[ICache.scala 114:69] + vb_array <= _T_385 @[ICache.scala 114:51] + skip @[ICache.scala 114:40] + node _T_386 = and(s1_valid, s1_disparity[2]) @[ICache.scala 114:20] + when _T_386 : @[ICache.scala 114:40] + node _T_388 = cat(UInt<2>("h02"), s1_idx) @[Cat.scala 30:58] + node _T_391 = dshl(UInt<1>("h01"), _T_388) @[ICache.scala 114:69] + node _T_392 = or(vb_array, _T_391) @[ICache.scala 114:69] + node _T_393 = not(vb_array) @[ICache.scala 114:69] + node _T_394 = or(_T_393, _T_391) @[ICache.scala 114:69] + node _T_395 = not(_T_394) @[ICache.scala 114:69] + node _T_396 = mux(UInt<1>("h00"), _T_392, _T_395) @[ICache.scala 114:69] + vb_array <= _T_396 @[ICache.scala 114:51] + skip @[ICache.scala 114:40] + node _T_397 = and(s1_valid, s1_disparity[3]) @[ICache.scala 114:20] + when _T_397 : @[ICache.scala 114:40] + node _T_399 = cat(UInt<2>("h03"), s1_idx) @[Cat.scala 30:58] + node _T_402 = dshl(UInt<1>("h01"), _T_399) @[ICache.scala 114:69] + node _T_403 = or(vb_array, _T_402) @[ICache.scala 114:69] + node _T_404 = not(vb_array) @[ICache.scala 114:69] + node _T_405 = or(_T_404, _T_402) @[ICache.scala 114:69] + node _T_406 = not(_T_405) @[ICache.scala 114:69] + node _T_407 = mux(UInt<1>("h00"), _T_403, _T_406) @[ICache.scala 114:69] + vb_array <= _T_407 @[ICache.scala 114:51] + skip @[ICache.scala 114:40] + wire s1_tag_match : UInt<1>[4] @[ICache.scala 116:26] + s1_tag_match is invalid @[ICache.scala 116:26] + wire s1_tag_hit : UInt<1>[4] @[ICache.scala 117:24] + s1_tag_hit is invalid @[ICache.scala 117:24] + wire s1_dout : UInt<64>[4] @[ICache.scala 118:21] + s1_dout is invalid @[ICache.scala 118:21] + reg s1_dout_valid : UInt<1>, clock @[Reg.scala 14:44] + s1_dout_valid <= s0_valid @[Reg.scala 14:44] + node _T_436 = eq(io.invalidate, UInt<1>("h00")) @[ICache.scala 122:17] + node _T_438 = bits(io.s1_paddr, 11, 6) @[ICache.scala 122:68] + node _T_439 = cat(UInt<1>("h00"), _T_438) @[Cat.scala 30:58] + node _T_440 = dshr(vb_array, _T_439) @[ICache.scala 122:43] + node _T_441 = bits(_T_440, 0, 0) @[ICache.scala 122:43] + node _T_442 = bits(_T_441, 0, 0) @[ICache.scala 122:97] + node _T_443 = and(_T_436, _T_442) @[ICache.scala 122:32] + node _T_446 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] + reg _T_448 : UInt<1>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_448 <= _T_446 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_449 = mux(s1_dout_valid, _T_446, _T_448) @[Package.scala 27:42] + node _T_450 = bits(tag_rdata[0], 19, 0) @[ICache.scala 125:32] + node _T_451 = eq(_T_450, s1_tag) @[ICache.scala 125:46] + reg _T_453 : UInt<1>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_453 <= _T_451 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_454 = mux(s1_dout_valid, _T_451, _T_453) @[Package.scala 27:42] + s1_tag_match[0] <= _T_454 @[ICache.scala 125:21] + node _T_455 = and(_T_443, s1_tag_match[0]) @[ICache.scala 126:28] + s1_tag_hit[0] <= _T_455 @[ICache.scala 126:19] + node _T_458 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] + node _T_459 = or(_T_449, _T_458) @[ICache.scala 127:51] + node _T_460 = and(_T_443, _T_459) @[ICache.scala 127:30] + s1_disparity[0] <= _T_460 @[ICache.scala 127:21] + node _T_462 = eq(io.invalidate, UInt<1>("h00")) @[ICache.scala 122:17] + node _T_464 = bits(io.s1_paddr, 11, 6) @[ICache.scala 122:68] + node _T_465 = cat(UInt<1>("h01"), _T_464) @[Cat.scala 30:58] + node _T_466 = dshr(vb_array, _T_465) @[ICache.scala 122:43] + node _T_467 = bits(_T_466, 0, 0) @[ICache.scala 122:43] + node _T_468 = bits(_T_467, 0, 0) @[ICache.scala 122:97] + node _T_469 = and(_T_462, _T_468) @[ICache.scala 122:32] + node _T_472 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] + reg _T_474 : UInt<1>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_474 <= _T_472 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_475 = mux(s1_dout_valid, _T_472, _T_474) @[Package.scala 27:42] + node _T_476 = bits(tag_rdata[1], 19, 0) @[ICache.scala 125:32] + node _T_477 = eq(_T_476, s1_tag) @[ICache.scala 125:46] + reg _T_479 : UInt<1>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_479 <= _T_477 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_480 = mux(s1_dout_valid, _T_477, _T_479) @[Package.scala 27:42] + s1_tag_match[1] <= _T_480 @[ICache.scala 125:21] + node _T_481 = and(_T_469, s1_tag_match[1]) @[ICache.scala 126:28] + s1_tag_hit[1] <= _T_481 @[ICache.scala 126:19] + node _T_484 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] + node _T_485 = or(_T_475, _T_484) @[ICache.scala 127:51] + node _T_486 = and(_T_469, _T_485) @[ICache.scala 127:30] + s1_disparity[1] <= _T_486 @[ICache.scala 127:21] + node _T_488 = eq(io.invalidate, UInt<1>("h00")) @[ICache.scala 122:17] + node _T_490 = bits(io.s1_paddr, 11, 6) @[ICache.scala 122:68] + node _T_491 = cat(UInt<2>("h02"), _T_490) @[Cat.scala 30:58] + node _T_492 = dshr(vb_array, _T_491) @[ICache.scala 122:43] + node _T_493 = bits(_T_492, 0, 0) @[ICache.scala 122:43] + node _T_494 = bits(_T_493, 0, 0) @[ICache.scala 122:97] + node _T_495 = and(_T_488, _T_494) @[ICache.scala 122:32] + node _T_498 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] + reg _T_500 : UInt<1>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_500 <= _T_498 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_501 = mux(s1_dout_valid, _T_498, _T_500) @[Package.scala 27:42] + node _T_502 = bits(tag_rdata[2], 19, 0) @[ICache.scala 125:32] + node _T_503 = eq(_T_502, s1_tag) @[ICache.scala 125:46] + reg _T_505 : UInt<1>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_505 <= _T_503 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_506 = mux(s1_dout_valid, _T_503, _T_505) @[Package.scala 27:42] + s1_tag_match[2] <= _T_506 @[ICache.scala 125:21] + node _T_507 = and(_T_495, s1_tag_match[2]) @[ICache.scala 126:28] + s1_tag_hit[2] <= _T_507 @[ICache.scala 126:19] + node _T_510 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] + node _T_511 = or(_T_501, _T_510) @[ICache.scala 127:51] + node _T_512 = and(_T_495, _T_511) @[ICache.scala 127:30] + s1_disparity[2] <= _T_512 @[ICache.scala 127:21] + node _T_514 = eq(io.invalidate, UInt<1>("h00")) @[ICache.scala 122:17] + node _T_516 = bits(io.s1_paddr, 11, 6) @[ICache.scala 122:68] + node _T_517 = cat(UInt<2>("h03"), _T_516) @[Cat.scala 30:58] + node _T_518 = dshr(vb_array, _T_517) @[ICache.scala 122:43] + node _T_519 = bits(_T_518, 0, 0) @[ICache.scala 122:43] + node _T_520 = bits(_T_519, 0, 0) @[ICache.scala 122:97] + node _T_521 = and(_T_514, _T_520) @[ICache.scala 122:32] + node _T_524 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] + reg _T_526 : UInt<1>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_526 <= _T_524 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_527 = mux(s1_dout_valid, _T_524, _T_526) @[Package.scala 27:42] + node _T_528 = bits(tag_rdata[3], 19, 0) @[ICache.scala 125:32] + node _T_529 = eq(_T_528, s1_tag) @[ICache.scala 125:46] + reg _T_531 : UInt<1>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_531 <= _T_529 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_532 = mux(s1_dout_valid, _T_529, _T_531) @[Package.scala 27:42] + s1_tag_match[3] <= _T_532 @[ICache.scala 125:21] + node _T_533 = and(_T_521, s1_tag_match[3]) @[ICache.scala 126:28] + s1_tag_hit[3] <= _T_533 @[ICache.scala 126:19] + node _T_536 = or(UInt<1>("h00"), UInt<1>("h00")) @[Ecc.scala 14:27] + node _T_537 = or(_T_527, _T_536) @[ICache.scala 127:51] + node _T_538 = and(_T_521, _T_537) @[ICache.scala 127:30] + s1_disparity[3] <= _T_538 @[ICache.scala 127:21] + node _T_539 = or(s1_tag_hit[0], s1_tag_hit[1]) @[ICache.scala 129:44] + node _T_540 = or(_T_539, s1_tag_hit[2]) @[ICache.scala 129:44] + node _T_541 = or(_T_540, s1_tag_hit[3]) @[ICache.scala 129:44] + node _T_542 = or(s1_disparity[0], s1_disparity[1]) @[ICache.scala 129:78] + node _T_543 = or(_T_542, s1_disparity[2]) @[ICache.scala 129:78] + node _T_544 = or(_T_543, s1_disparity[3]) @[ICache.scala 129:78] + node _T_546 = eq(_T_544, UInt<1>("h00")) @[ICache.scala 129:52] + node _T_547 = and(_T_541, _T_546) @[ICache.scala 129:49] + s1_any_tag_hit <= _T_547 @[ICache.scala 129:18] + smem _T_550 : UInt<64>[512] @[ICache.scala 132:28] + node _T_552 = eq(repl_way, UInt<1>("h00")) @[ICache.scala 133:42] + node _T_553 = and(io.mem.0.d.valid, _T_552) @[ICache.scala 133:30] + when _T_553 : @[ICache.scala 134:16] + node _T_554 = shl(refill_idx, 3) @[ICache.scala 136:36] + node _T_555 = or(_T_554, refill_cnt) @[ICache.scala 136:63] + write mport _T_556 = _T_550[_T_555], clock + _T_556 <= io.mem.0.d.bits.data + skip @[ICache.scala 134:16] + node _T_557 = bits(io.req.bits.addr, 11, 3) @[ICache.scala 138:28] + node _T_559 = eq(_T_553, UInt<1>("h00")) @[ICache.scala 139:45] + node _T_560 = and(_T_559, s0_valid) @[ICache.scala 139:50] + wire _T_562 : UInt + _T_562 is invalid + when _T_560 : + _T_562 <= _T_557 + node _T_564 = or(_T_562, UInt<9>("h00")) + node _T_565 = bits(_T_564, 8, 0) + read mport _T_566 = _T_550[_T_565], clock + skip + reg _T_568 : UInt<64>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_568 <= _T_566 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_569 = mux(s1_dout_valid, _T_566, _T_568) @[Package.scala 27:42] + s1_dout[0] <= _T_569 @[ICache.scala 139:16] + smem _T_572 : UInt<64>[512] @[ICache.scala 132:28] + node _T_574 = eq(repl_way, UInt<1>("h01")) @[ICache.scala 133:42] + node _T_575 = and(io.mem.0.d.valid, _T_574) @[ICache.scala 133:30] + when _T_575 : @[ICache.scala 134:16] + node _T_576 = shl(refill_idx, 3) @[ICache.scala 136:36] + node _T_577 = or(_T_576, refill_cnt) @[ICache.scala 136:63] + write mport _T_578 = _T_572[_T_577], clock + _T_578 <= io.mem.0.d.bits.data + skip @[ICache.scala 134:16] + node _T_579 = bits(io.req.bits.addr, 11, 3) @[ICache.scala 138:28] + node _T_581 = eq(_T_575, UInt<1>("h00")) @[ICache.scala 139:45] + node _T_582 = and(_T_581, s0_valid) @[ICache.scala 139:50] + wire _T_584 : UInt + _T_584 is invalid + when _T_582 : + _T_584 <= _T_579 + node _T_586 = or(_T_584, UInt<9>("h00")) + node _T_587 = bits(_T_586, 8, 0) + read mport _T_588 = _T_572[_T_587], clock + skip + reg _T_590 : UInt<64>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_590 <= _T_588 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_591 = mux(s1_dout_valid, _T_588, _T_590) @[Package.scala 27:42] + s1_dout[1] <= _T_591 @[ICache.scala 139:16] + smem _T_594 : UInt<64>[512] @[ICache.scala 132:28] + node _T_596 = eq(repl_way, UInt<2>("h02")) @[ICache.scala 133:42] + node _T_597 = and(io.mem.0.d.valid, _T_596) @[ICache.scala 133:30] + when _T_597 : @[ICache.scala 134:16] + node _T_598 = shl(refill_idx, 3) @[ICache.scala 136:36] + node _T_599 = or(_T_598, refill_cnt) @[ICache.scala 136:63] + write mport _T_600 = _T_594[_T_599], clock + _T_600 <= io.mem.0.d.bits.data + skip @[ICache.scala 134:16] + node _T_601 = bits(io.req.bits.addr, 11, 3) @[ICache.scala 138:28] + node _T_603 = eq(_T_597, UInt<1>("h00")) @[ICache.scala 139:45] + node _T_604 = and(_T_603, s0_valid) @[ICache.scala 139:50] + wire _T_606 : UInt + _T_606 is invalid + when _T_604 : + _T_606 <= _T_601 + node _T_608 = or(_T_606, UInt<9>("h00")) + node _T_609 = bits(_T_608, 8, 0) + read mport _T_610 = _T_594[_T_609], clock + skip + reg _T_612 : UInt<64>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_612 <= _T_610 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_613 = mux(s1_dout_valid, _T_610, _T_612) @[Package.scala 27:42] + s1_dout[2] <= _T_613 @[ICache.scala 139:16] + smem _T_616 : UInt<64>[512] @[ICache.scala 132:28] + node _T_618 = eq(repl_way, UInt<2>("h03")) @[ICache.scala 133:42] + node _T_619 = and(io.mem.0.d.valid, _T_618) @[ICache.scala 133:30] + when _T_619 : @[ICache.scala 134:16] + node _T_620 = shl(refill_idx, 3) @[ICache.scala 136:36] + node _T_621 = or(_T_620, refill_cnt) @[ICache.scala 136:63] + write mport _T_622 = _T_616[_T_621], clock + _T_622 <= io.mem.0.d.bits.data + skip @[ICache.scala 134:16] + node _T_623 = bits(io.req.bits.addr, 11, 3) @[ICache.scala 138:28] + node _T_625 = eq(_T_619, UInt<1>("h00")) @[ICache.scala 139:45] + node _T_626 = and(_T_625, s0_valid) @[ICache.scala 139:50] + wire _T_628 : UInt + _T_628 is invalid + when _T_626 : + _T_628 <= _T_623 + node _T_630 = or(_T_628, UInt<9>("h00")) + node _T_631 = bits(_T_630, 8, 0) + read mport _T_632 = _T_616[_T_631], clock + skip + reg _T_634 : UInt<64>, clock @[Reg.scala 34:16] + when s1_dout_valid : @[Reg.scala 35:19] + _T_634 <= _T_632 @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_635 = mux(s1_dout_valid, _T_632, _T_634) @[Package.scala 27:42] + s1_dout[3] <= _T_635 @[ICache.scala 139:16] + node _T_638 = eq(stall, UInt<1>("h00")) @[ICache.scala 148:51] + reg _T_639 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44] + when _T_638 : @[Reg.scala 43:19] + _T_639 <= s1_hit @[Reg.scala 43:23] + skip @[Reg.scala 43:19] + node _T_641 = eq(stall, UInt<1>("h00")) @[ICache.scala 149:46] + reg _T_654 : UInt<1>[4], clock @[Reg.scala 34:16] + when _T_641 : @[Reg.scala 35:19] + _T_654 <- s1_tag_hit @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_672 = eq(stall, UInt<1>("h00")) @[ICache.scala 150:40] + reg _T_685 : UInt<64>[4], clock @[Reg.scala 34:16] + when _T_672 : @[Reg.scala 35:19] + _T_685 <- s1_dout @[Reg.scala 35:23] + skip @[Reg.scala 35:19] + node _T_703 = mux(_T_654[0], _T_685[0], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_705 = mux(_T_654[1], _T_685[1], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_707 = mux(_T_654[2], _T_685[2], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_709 = mux(_T_654[3], _T_685[3], UInt<1>("h00")) @[Mux.scala 19:72] + node _T_711 = or(_T_703, _T_705) @[Mux.scala 19:72] + node _T_712 = or(_T_711, _T_707) @[Mux.scala 19:72] + node _T_713 = or(_T_712, _T_709) @[Mux.scala 19:72] + wire _T_715 : UInt<64> @[Mux.scala 19:72] + _T_715 is invalid @[Mux.scala 19:72] + _T_715 <= _T_713 @[Mux.scala 19:72] + io.resp.bits.datablock <= _T_715 @[ICache.scala 151:30] + io.resp.valid <= _T_639 @[ICache.scala 152:21] + node _T_716 = eq(state, UInt<2>("h01")) @[ICache.scala 154:27] + node _T_718 = eq(io.s2_kill, UInt<1>("h00")) @[ICache.scala 154:44] + node _T_719 = and(_T_716, _T_718) @[ICache.scala 154:41] + io.mem.0.a.valid <= _T_719 @[ICache.scala 154:18] + node _T_721 = shr(refill_addr, 6) @[ICache.scala 157:46] + node _T_722 = shl(_T_721, 6) @[ICache.scala 157:63] + node _T_726 = leq(UInt<1>("h00"), UInt<3>("h06")) @[Parameters.scala 63:32] + node _T_728 = leq(UInt<3>("h06"), UInt<3>("h06")) @[Parameters.scala 63:42] + node _T_729 = and(_T_726, _T_728) @[Parameters.scala 63:37] + node _T_730 = or(UInt<1>("h00"), _T_729) @[Parameters.scala 132:31] + node _T_732 = xor(_T_722, UInt<1>("h00")) @[Parameters.scala 117:31] + node _T_733 = cvt(_T_732) @[Parameters.scala 117:49] + node _T_735 = and(_T_733, asSInt(UInt<31>("h020000000"))) @[Parameters.scala 117:52] + node _T_736 = asSInt(_T_735) @[Parameters.scala 117:52] + node _T_738 = eq(_T_736, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_739 = and(_T_730, _T_738) @[Parameters.scala 132:56] + node _T_742 = leq(UInt<1>("h00"), UInt<3>("h06")) @[Parameters.scala 63:32] + node _T_744 = leq(UInt<3>("h06"), UInt<4>("h08")) @[Parameters.scala 63:42] + node _T_745 = and(_T_742, _T_744) @[Parameters.scala 63:37] + node _T_746 = or(UInt<1>("h00"), _T_745) @[Parameters.scala 132:31] + node _T_748 = xor(_T_722, UInt<30>("h020000000")) @[Parameters.scala 117:31] + node _T_749 = cvt(_T_748) @[Parameters.scala 117:49] + node _T_751 = and(_T_749, asSInt(UInt<31>("h020000000"))) @[Parameters.scala 117:52] + node _T_752 = asSInt(_T_751) @[Parameters.scala 117:52] + node _T_754 = eq(_T_752, asSInt(UInt<1>("h00"))) @[Parameters.scala 117:67] + node _T_755 = and(_T_746, _T_754) @[Parameters.scala 132:56] + node _T_757 = or(UInt<1>("h00"), _T_739) @[Parameters.scala 134:30] + node _T_758 = or(_T_757, _T_755) @[Parameters.scala 134:30] + wire _T_767 : {opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>} @[Edges.scala 342:17] + _T_767 is invalid @[Edges.scala 342:17] + _T_767.opcode <= UInt<3>("h04") @[Edges.scala 343:15] + _T_767.param <= UInt<1>("h00") @[Edges.scala 344:15] + _T_767.size <= UInt<3>("h06") @[Edges.scala 345:15] + _T_767.source <= UInt<1>("h00") @[Edges.scala 346:15] + _T_767.address <= _T_722 @[Edges.scala 347:15] + node _T_779 = dshl(UInt<1>("h01"), UInt<2>("h02")) @[OneHot.scala 49:12] + node _T_780 = bits(_T_779, 2, 0) @[OneHot.scala 49:37] + node _T_782 = geq(UInt<3>("h06"), UInt<2>("h03")) @[package.scala 41:21] + node _T_784 = bits(_T_780, 2, 2) @[package.scala 44:26] + node _T_785 = bits(_T_722, 2, 2) @[package.scala 45:26] + node _T_787 = eq(_T_785, UInt<1>("h00")) @[package.scala 46:20] + node _T_788 = and(UInt<1>("h01"), _T_787) @[package.scala 49:27] + node _T_789 = and(_T_784, _T_788) @[package.scala 50:38] + node _T_790 = or(_T_782, _T_789) @[package.scala 50:29] + node _T_791 = and(UInt<1>("h01"), _T_785) @[package.scala 49:27] + node _T_792 = and(_T_784, _T_791) @[package.scala 50:38] + node _T_793 = or(_T_782, _T_792) @[package.scala 50:29] + node _T_794 = bits(_T_780, 1, 1) @[package.scala 44:26] + node _T_795 = bits(_T_722, 1, 1) @[package.scala 45:26] + node _T_797 = eq(_T_795, UInt<1>("h00")) @[package.scala 46:20] + node _T_798 = and(_T_788, _T_797) @[package.scala 49:27] + node _T_799 = and(_T_794, _T_798) @[package.scala 50:38] + node _T_800 = or(_T_790, _T_799) @[package.scala 50:29] + node _T_801 = and(_T_788, _T_795) @[package.scala 49:27] + node _T_802 = and(_T_794, _T_801) @[package.scala 50:38] + node _T_803 = or(_T_790, _T_802) @[package.scala 50:29] + node _T_804 = and(_T_791, _T_797) @[package.scala 49:27] + node _T_805 = and(_T_794, _T_804) @[package.scala 50:38] + node _T_806 = or(_T_793, _T_805) @[package.scala 50:29] + node _T_807 = and(_T_791, _T_795) @[package.scala 49:27] + node _T_808 = and(_T_794, _T_807) @[package.scala 50:38] + node _T_809 = or(_T_793, _T_808) @[package.scala 50:29] + node _T_810 = bits(_T_780, 0, 0) @[package.scala 44:26] + node _T_811 = bits(_T_722, 0, 0) @[package.scala 45:26] + node _T_813 = eq(_T_811, UInt<1>("h00")) @[package.scala 46:20] + node _T_814 = and(_T_798, _T_813) @[package.scala 49:27] + node _T_815 = and(_T_810, _T_814) @[package.scala 50:38] + node _T_816 = or(_T_800, _T_815) @[package.scala 50:29] + node _T_817 = and(_T_798, _T_811) @[package.scala 49:27] + node _T_818 = and(_T_810, _T_817) @[package.scala 50:38] + node _T_819 = or(_T_800, _T_818) @[package.scala 50:29] + node _T_820 = and(_T_801, _T_813) @[package.scala 49:27] + node _T_821 = and(_T_810, _T_820) @[package.scala 50:38] + node _T_822 = or(_T_803, _T_821) @[package.scala 50:29] + node _T_823 = and(_T_801, _T_811) @[package.scala 49:27] + node _T_824 = and(_T_810, _T_823) @[package.scala 50:38] + node _T_825 = or(_T_803, _T_824) @[package.scala 50:29] + node _T_826 = and(_T_804, _T_813) @[package.scala 49:27] + node _T_827 = and(_T_810, _T_826) @[package.scala 50:38] + node _T_828 = or(_T_806, _T_827) @[package.scala 50:29] + node _T_829 = and(_T_804, _T_811) @[package.scala 49:27] + node _T_830 = and(_T_810, _T_829) @[package.scala 50:38] + node _T_831 = or(_T_806, _T_830) @[package.scala 50:29] + node _T_832 = and(_T_807, _T_813) @[package.scala 49:27] + node _T_833 = and(_T_810, _T_832) @[package.scala 50:38] + node _T_834 = or(_T_809, _T_833) @[package.scala 50:29] + node _T_835 = and(_T_807, _T_811) @[package.scala 49:27] + node _T_836 = and(_T_810, _T_835) @[package.scala 50:38] + node _T_837 = or(_T_809, _T_836) @[package.scala 50:29] + node _T_838 = cat(_T_819, _T_816) @[Cat.scala 30:58] + node _T_839 = cat(_T_825, _T_822) @[Cat.scala 30:58] + node _T_840 = cat(_T_839, _T_838) @[Cat.scala 30:58] + node _T_841 = cat(_T_831, _T_828) @[Cat.scala 30:58] + node _T_842 = cat(_T_837, _T_834) @[Cat.scala 30:58] + node _T_843 = cat(_T_842, _T_841) @[Cat.scala 30:58] + node _T_844 = cat(_T_843, _T_840) @[Cat.scala 30:58] + _T_767.mask <= _T_844 @[Edges.scala 348:15] + _T_767.data <= UInt<1>("h00") @[Edges.scala 349:15] + io.mem.0.a.bits <- _T_767 @[ICache.scala 155:17] + io.mem.0.c.valid <= UInt<1>("h00") @[ICache.scala 159:18] + io.mem.0.e.valid <= UInt<1>("h00") @[ICache.scala 160:18] + node _T_848 = eq(UInt<2>("h00"), state) @[Conditional.scala 29:28] + when _T_848 : @[Conditional.scala 29:59] + when s1_miss : @[ICache.scala 165:22] + state <= UInt<2>("h01") @[ICache.scala 165:30] + skip @[ICache.scala 165:22] + invalidated <= UInt<1>("h00") @[ICache.scala 166:19] + skip @[Conditional.scala 29:59] + node _T_850 = eq(UInt<2>("h01"), state) @[Conditional.scala 29:28] + when _T_850 : @[Conditional.scala 29:59] + when io.mem.0.a.ready : @[ICache.scala 169:29] + state <= UInt<2>("h02") @[ICache.scala 169:37] + skip @[ICache.scala 169:29] + when io.s2_kill : @[ICache.scala 170:25] + state <= UInt<2>("h00") @[ICache.scala 170:33] + skip @[ICache.scala 170:25] + skip @[Conditional.scala 29:59] + node _T_851 = eq(UInt<2>("h02"), state) @[Conditional.scala 29:28] + when _T_851 : @[Conditional.scala 29:59] + when io.mem.0.d.valid : @[ICache.scala 173:29] + state <= UInt<2>("h03") @[ICache.scala 173:37] + skip @[ICache.scala 173:29] + skip @[Conditional.scala 29:59] + node _T_852 = eq(UInt<2>("h03"), state) @[Conditional.scala 29:28] + when _T_852 : @[Conditional.scala 29:59] + when refill_done : @[ICache.scala 176:26] + state <= UInt<2>("h00") @[ICache.scala 176:34] + skip @[ICache.scala 176:26] + skip @[Conditional.scala 29:59] + diff --git a/regress/RocketCore.fir b/regress/RocketCore.fir new file mode 100644 index 00000000..e1ef9025 --- /dev/null +++ b/regress/RocketCore.fir @@ -0,0 +1,6154 @@ +circuit RocketCore : + module RocketCore : + input clock : Clock + input reset : UInt<1> + output io : {flip interrupts : {debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, seip : UInt<1>}, flip hartid : UInt<64>, imem : {req : {valid : UInt<1>, bits : {pc : UInt<40>, speculative : UInt<1>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {btb : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt_if : UInt<1>, replay : UInt<1>}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, flush_icache : UInt<1>, flush_tlb : UInt<1>, flip npc : UInt<40>, flip acquire : UInt<1>}, dmem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip acquire : UInt<1>, flip release : UInt<1>, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, flip ptw : {flip ptbr : {mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip invalidate : UInt<1>, flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, flip fpu : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>}, flip rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, phys : UInt<1>, data : UInt<64>}}, s1_kill : UInt<1>, s1_data : UInt<64>, flip s2_nack : UInt<1>, flip acquire : UInt<1>, flip release : UInt<1>, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, interrupt : UInt<1>, flip exception : UInt<1>}} + + io is invalid + io is invalid + reg ex_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>}, clock @[Rocket.scala 115:20] + reg mem_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>}, clock @[Rocket.scala 116:21] + reg wb_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>}, clock @[Rocket.scala 117:20] + reg ex_reg_xcpt_interrupt : UInt<1>, clock @[Rocket.scala 119:35] + reg ex_reg_valid : UInt<1>, clock @[Rocket.scala 120:35] + reg ex_reg_rvc : UInt<1>, clock @[Rocket.scala 121:35] + reg ex_reg_btb_hit : UInt<1>, clock @[Rocket.scala 122:35] + reg ex_reg_btb_resp : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clock @[Rocket.scala 123:35] + reg ex_reg_xcpt : UInt<1>, clock @[Rocket.scala 124:35] + reg ex_reg_flush_pipe : UInt<1>, clock @[Rocket.scala 125:35] + reg ex_reg_load_use : UInt<1>, clock @[Rocket.scala 126:35] + reg ex_cause : UInt, clock @[Rocket.scala 127:35] + reg ex_reg_replay : UInt<1>, clock @[Rocket.scala 128:26] + reg ex_reg_pc : UInt, clock @[Rocket.scala 129:22] + reg ex_reg_inst : UInt, clock @[Rocket.scala 130:24] + reg mem_reg_xcpt_interrupt : UInt<1>, clock @[Rocket.scala 132:36] + reg mem_reg_valid : UInt<1>, clock @[Rocket.scala 133:36] + reg mem_reg_rvc : UInt<1>, clock @[Rocket.scala 134:36] + reg mem_reg_btb_hit : UInt<1>, clock @[Rocket.scala 135:36] + reg mem_reg_btb_resp : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clock @[Rocket.scala 136:36] + reg mem_reg_xcpt : UInt<1>, clock @[Rocket.scala 137:36] + reg mem_reg_replay : UInt<1>, clock @[Rocket.scala 138:36] + reg mem_reg_flush_pipe : UInt<1>, clock @[Rocket.scala 139:36] + reg mem_reg_cause : UInt, clock @[Rocket.scala 140:36] + reg mem_reg_slow_bypass : UInt<1>, clock @[Rocket.scala 141:36] + reg mem_reg_load : UInt<1>, clock @[Rocket.scala 142:36] + reg mem_reg_store : UInt<1>, clock @[Rocket.scala 143:36] + reg mem_reg_pc : UInt, clock @[Rocket.scala 144:23] + reg mem_reg_inst : UInt, clock @[Rocket.scala 145:25] + reg mem_reg_wdata : UInt, clock @[Rocket.scala 146:26] + reg mem_reg_rs2 : UInt, clock @[Rocket.scala 147:24] + wire take_pc_mem : UInt<1> @[Rocket.scala 148:25] + take_pc_mem is invalid @[Rocket.scala 148:25] + reg wb_reg_valid : UInt<1>, clock @[Rocket.scala 150:35] + reg wb_reg_xcpt : UInt<1>, clock @[Rocket.scala 151:35] + reg wb_reg_replay : UInt<1>, clock @[Rocket.scala 152:35] + reg wb_reg_cause : UInt, clock @[Rocket.scala 153:35] + reg wb_reg_pc : UInt, clock @[Rocket.scala 154:22] + reg wb_reg_inst : UInt, clock @[Rocket.scala 155:24] + reg wb_reg_wdata : UInt, clock @[Rocket.scala 156:25] + reg wb_reg_rs2 : UInt, clock @[Rocket.scala 157:23] + wire take_pc_wb : UInt<1> @[Rocket.scala 158:24] + take_pc_wb is invalid @[Rocket.scala 158:24] + wire take_pc_id : UInt<1> @[Rocket.scala 160:24] + take_pc_id is invalid @[Rocket.scala 160:24] + node take_pc_mem_wb = or(take_pc_wb, take_pc_mem) @[Rocket.scala 161:35] + node take_pc = or(take_pc_mem_wb, take_pc_id) @[Rocket.scala 162:32] + inst ibuf of IBuf @[Rocket.scala 165:20] + ibuf.io is invalid + ibuf.clock <= clock + ibuf.reset <= reset + ibuf.io.imem <- io.imem.resp @[Rocket.scala 168:16] + ibuf.io.kill <= take_pc @[Rocket.scala 169:16] + wire id_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>} @[Rocket.scala 172:21] + id_ctrl is invalid @[Rocket.scala 172:21] + node _T_2603 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0207f")) @[Decode.scala 13:65] + node _T_2605 = eq(_T_2603, UInt<32>("h03")) @[Decode.scala 13:121] + node _T_2607 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0106f")) @[Decode.scala 13:65] + node _T_2609 = eq(_T_2607, UInt<32>("h03")) @[Decode.scala 13:121] + node _T_2611 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0607f")) @[Decode.scala 13:65] + node _T_2613 = eq(_T_2611, UInt<32>("h0f")) @[Decode.scala 13:121] + node _T_2615 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07077")) @[Decode.scala 13:65] + node _T_2617 = eq(_T_2615, UInt<32>("h013")) @[Decode.scala 13:121] + node _T_2619 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h05f")) @[Decode.scala 13:65] + node _T_2621 = eq(_T_2619, UInt<32>("h017")) @[Decode.scala 13:121] + node _T_2623 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fc00007f")) @[Decode.scala 13:65] + node _T_2625 = eq(_T_2623, UInt<32>("h033")) @[Decode.scala 13:121] + node _T_2627 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0be007077")) @[Decode.scala 13:65] + node _T_2629 = eq(_T_2627, UInt<32>("h033")) @[Decode.scala 13:121] + node _T_2631 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04000073")) @[Decode.scala 13:65] + node _T_2633 = eq(_T_2631, UInt<32>("h043")) @[Decode.scala 13:121] + node _T_2635 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0e400007f")) @[Decode.scala 13:65] + node _T_2637 = eq(_T_2635, UInt<32>("h053")) @[Decode.scala 13:121] + node _T_2639 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0707b")) @[Decode.scala 13:65] + node _T_2641 = eq(_T_2639, UInt<32>("h063")) @[Decode.scala 13:121] + node _T_2643 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07f")) @[Decode.scala 13:65] + node _T_2645 = eq(_T_2643, UInt<32>("h06f")) @[Decode.scala 13:121] + node _T_2647 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0ffefffff")) @[Decode.scala 13:65] + node _T_2649 = eq(_T_2647, UInt<32>("h073")) @[Decode.scala 13:121] + node _T_2651 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fc00305f")) @[Decode.scala 13:65] + node _T_2653 = eq(_T_2651, UInt<32>("h01013")) @[Decode.scala 13:121] + node _T_2655 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fe00305f")) @[Decode.scala 13:65] + node _T_2657 = eq(_T_2655, UInt<32>("h0101b")) @[Decode.scala 13:121] + node _T_2659 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0605b")) @[Decode.scala 13:65] + node _T_2661 = eq(_T_2659, UInt<32>("h02003")) @[Decode.scala 13:121] + node _T_2663 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0207f")) @[Decode.scala 13:65] + node _T_2665 = eq(_T_2663, UInt<32>("h02013")) @[Decode.scala 13:121] + node _T_2667 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01800607f")) @[Decode.scala 13:65] + node _T_2669 = eq(_T_2667, UInt<32>("h0202f")) @[Decode.scala 13:121] + node _T_2671 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0207f")) @[Decode.scala 13:65] + node _T_2673 = eq(_T_2671, UInt<32>("h02073")) @[Decode.scala 13:121] + node _T_2675 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0bc00707f")) @[Decode.scala 13:65] + node _T_2677 = eq(_T_2675, UInt<32>("h05013")) @[Decode.scala 13:121] + node _T_2679 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0be00705f")) @[Decode.scala 13:65] + node _T_2681 = eq(_T_2679, UInt<32>("h0501b")) @[Decode.scala 13:121] + node _T_2683 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0be007077")) @[Decode.scala 13:65] + node _T_2685 = eq(_T_2683, UInt<32>("h05033")) @[Decode.scala 13:121] + node _T_2687 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fe004077")) @[Decode.scala 13:65] + node _T_2689 = eq(_T_2687, UInt<32>("h02004033")) @[Decode.scala 13:121] + node _T_2691 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0e800607f")) @[Decode.scala 13:65] + node _T_2693 = eq(_T_2691, UInt<32>("h0800202f")) @[Decode.scala 13:121] + node _T_2695 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0f9f0607f")) @[Decode.scala 13:65] + node _T_2697 = eq(_T_2695, UInt<32>("h01000202f")) @[Decode.scala 13:121] + node _T_2699 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0dfffffff")) @[Decode.scala 13:65] + node _T_2701 = eq(_T_2699, UInt<32>("h010200073")) @[Decode.scala 13:121] + node _T_2703 = eq(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010500073")) @[Decode.scala 13:121] + node _T_2705 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fe007fff")) @[Decode.scala 13:65] + node _T_2707 = eq(_T_2705, UInt<32>("h012000073")) @[Decode.scala 13:121] + node _T_2709 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0f400607f")) @[Decode.scala 13:65] + node _T_2711 = eq(_T_2709, UInt<32>("h020000053")) @[Decode.scala 13:121] + node _T_2713 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07c00607f")) @[Decode.scala 13:65] + node _T_2715 = eq(_T_2713, UInt<32>("h020000053")) @[Decode.scala 13:121] + node _T_2717 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07c00507f")) @[Decode.scala 13:65] + node _T_2719 = eq(_T_2717, UInt<32>("h020000053")) @[Decode.scala 13:121] + node _T_2721 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07ff0007f")) @[Decode.scala 13:65] + node _T_2723 = eq(_T_2721, UInt<32>("h040100053")) @[Decode.scala 13:121] + node _T_2725 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07ff0007f")) @[Decode.scala 13:65] + node _T_2727 = eq(_T_2725, UInt<32>("h042000053")) @[Decode.scala 13:121] + node _T_2729 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fdf0007f")) @[Decode.scala 13:65] + node _T_2731 = eq(_T_2729, UInt<32>("h058000053")) @[Decode.scala 13:121] + node _T_2733 = eq(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07b200073")) @[Decode.scala 13:121] + node _T_2735 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0edc0007f")) @[Decode.scala 13:65] + node _T_2737 = eq(_T_2735, UInt<32>("h0c0000053")) @[Decode.scala 13:121] + node _T_2739 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fdf0607f")) @[Decode.scala 13:65] + node _T_2741 = eq(_T_2739, UInt<32>("h0e0000053")) @[Decode.scala 13:121] + node _T_2743 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0edf0707f")) @[Decode.scala 13:65] + node _T_2745 = eq(_T_2743, UInt<32>("h0e0000053")) @[Decode.scala 13:121] + node _T_2747 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0603f")) @[Decode.scala 13:65] + node _T_2749 = eq(_T_2747, UInt<32>("h023")) @[Decode.scala 13:121] + node _T_2751 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0306f")) @[Decode.scala 13:65] + node _T_2753 = eq(_T_2751, UInt<32>("h01063")) @[Decode.scala 13:121] + node _T_2755 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0407f")) @[Decode.scala 13:65] + node _T_2757 = eq(_T_2755, UInt<32>("h04063")) @[Decode.scala 13:121] + node _T_2759 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0fc007077")) @[Decode.scala 13:65] + node _T_2761 = eq(_T_2759, UInt<32>("h033")) @[Decode.scala 13:121] + node _T_2763 = or(UInt<1>("h00"), _T_2605) @[Decode.scala 14:30] + node _T_2764 = or(_T_2763, _T_2609) @[Decode.scala 14:30] + node _T_2765 = or(_T_2764, _T_2613) @[Decode.scala 14:30] + node _T_2766 = or(_T_2765, _T_2617) @[Decode.scala 14:30] + node _T_2767 = or(_T_2766, _T_2621) @[Decode.scala 14:30] + node _T_2768 = or(_T_2767, _T_2625) @[Decode.scala 14:30] + node _T_2769 = or(_T_2768, _T_2629) @[Decode.scala 14:30] + node _T_2770 = or(_T_2769, _T_2633) @[Decode.scala 14:30] + node _T_2771 = or(_T_2770, _T_2637) @[Decode.scala 14:30] + node _T_2772 = or(_T_2771, _T_2641) @[Decode.scala 14:30] + node _T_2773 = or(_T_2772, _T_2645) @[Decode.scala 14:30] + node _T_2774 = or(_T_2773, _T_2649) @[Decode.scala 14:30] + node _T_2775 = or(_T_2774, _T_2653) @[Decode.scala 14:30] + node _T_2776 = or(_T_2775, _T_2657) @[Decode.scala 14:30] + node _T_2777 = or(_T_2776, _T_2661) @[Decode.scala 14:30] + node _T_2778 = or(_T_2777, _T_2665) @[Decode.scala 14:30] + node _T_2779 = or(_T_2778, _T_2669) @[Decode.scala 14:30] + node _T_2780 = or(_T_2779, _T_2673) @[Decode.scala 14:30] + node _T_2781 = or(_T_2780, _T_2677) @[Decode.scala 14:30] + node _T_2782 = or(_T_2781, _T_2681) @[Decode.scala 14:30] + node _T_2783 = or(_T_2782, _T_2685) @[Decode.scala 14:30] + node _T_2784 = or(_T_2783, _T_2689) @[Decode.scala 14:30] + node _T_2785 = or(_T_2784, _T_2693) @[Decode.scala 14:30] + node _T_2786 = or(_T_2785, _T_2697) @[Decode.scala 14:30] + node _T_2787 = or(_T_2786, _T_2701) @[Decode.scala 14:30] + node _T_2788 = or(_T_2787, _T_2703) @[Decode.scala 14:30] + node _T_2789 = or(_T_2788, _T_2707) @[Decode.scala 14:30] + node _T_2790 = or(_T_2789, _T_2711) @[Decode.scala 14:30] + node _T_2791 = or(_T_2790, _T_2715) @[Decode.scala 14:30] + node _T_2792 = or(_T_2791, _T_2719) @[Decode.scala 14:30] + node _T_2793 = or(_T_2792, _T_2723) @[Decode.scala 14:30] + node _T_2794 = or(_T_2793, _T_2727) @[Decode.scala 14:30] + node _T_2795 = or(_T_2794, _T_2731) @[Decode.scala 14:30] + node _T_2796 = or(_T_2795, _T_2733) @[Decode.scala 14:30] + node _T_2797 = or(_T_2796, _T_2737) @[Decode.scala 14:30] + node _T_2798 = or(_T_2797, _T_2741) @[Decode.scala 14:30] + node _T_2799 = or(_T_2798, _T_2745) @[Decode.scala 14:30] + node _T_2800 = or(_T_2799, _T_2749) @[Decode.scala 14:30] + node _T_2801 = or(_T_2800, _T_2753) @[Decode.scala 14:30] + node _T_2802 = or(_T_2801, _T_2757) @[Decode.scala 14:30] + node _T_2803 = or(_T_2802, _T_2761) @[Decode.scala 14:30] + node _T_2805 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h05c")) @[Decode.scala 13:65] + node _T_2807 = eq(_T_2805, UInt<32>("h04")) @[Decode.scala 13:121] + node _T_2809 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h060")) @[Decode.scala 13:65] + node _T_2811 = eq(_T_2809, UInt<32>("h040")) @[Decode.scala 13:121] + node _T_2813 = or(UInt<1>("h00"), _T_2807) @[Decode.scala 14:30] + node _T_2814 = or(_T_2813, _T_2811) @[Decode.scala 14:30] + node _T_2817 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h074")) @[Decode.scala 13:65] + node _T_2819 = eq(_T_2817, UInt<32>("h060")) @[Decode.scala 13:121] + node _T_2821 = or(UInt<1>("h00"), _T_2819) @[Decode.scala 14:30] + node _T_2823 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h068")) @[Decode.scala 13:65] + node _T_2825 = eq(_T_2823, UInt<32>("h068")) @[Decode.scala 13:121] + node _T_2827 = or(UInt<1>("h00"), _T_2825) @[Decode.scala 14:30] + node _T_2829 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0203c")) @[Decode.scala 13:65] + node _T_2831 = eq(_T_2829, UInt<32>("h024")) @[Decode.scala 13:121] + node _T_2833 = or(UInt<1>("h00"), _T_2831) @[Decode.scala 14:30] + node _T_2835 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h064")) @[Decode.scala 13:65] + node _T_2837 = eq(_T_2835, UInt<32>("h020")) @[Decode.scala 13:121] + node _T_2839 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h034")) @[Decode.scala 13:65] + node _T_2841 = eq(_T_2839, UInt<32>("h020")) @[Decode.scala 13:121] + node _T_2843 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02048")) @[Decode.scala 13:65] + node _T_2845 = eq(_T_2843, UInt<32>("h02008")) @[Decode.scala 13:121] + node _T_2847 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h042003024")) @[Decode.scala 13:65] + node _T_2849 = eq(_T_2847, UInt<32>("h02000020")) @[Decode.scala 13:121] + node _T_2851 = or(UInt<1>("h00"), _T_2837) @[Decode.scala 14:30] + node _T_2852 = or(_T_2851, _T_2841) @[Decode.scala 14:30] + node _T_2853 = or(_T_2852, _T_2845) @[Decode.scala 14:30] + node _T_2854 = or(_T_2853, _T_2849) @[Decode.scala 14:30] + node _T_2856 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h044")) @[Decode.scala 13:65] + node _T_2858 = eq(_T_2856, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2860 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04024")) @[Decode.scala 13:65] + node _T_2862 = eq(_T_2860, UInt<32>("h020")) @[Decode.scala 13:121] + node _T_2864 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h038")) @[Decode.scala 13:65] + node _T_2866 = eq(_T_2864, UInt<32>("h020")) @[Decode.scala 13:121] + node _T_2868 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02050")) @[Decode.scala 13:65] + node _T_2870 = eq(_T_2868, UInt<32>("h02000")) @[Decode.scala 13:121] + node _T_2872 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h090000034")) @[Decode.scala 13:65] + node _T_2874 = eq(_T_2872, UInt<32>("h090000010")) @[Decode.scala 13:121] + node _T_2876 = or(UInt<1>("h00"), _T_2858) @[Decode.scala 14:30] + node _T_2877 = or(_T_2876, _T_2862) @[Decode.scala 14:30] + node _T_2878 = or(_T_2877, _T_2866) @[Decode.scala 14:30] + node _T_2879 = or(_T_2878, _T_2870) @[Decode.scala 14:30] + node _T_2880 = or(_T_2879, _T_2874) @[Decode.scala 14:30] + node _T_2882 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h058")) @[Decode.scala 13:65] + node _T_2884 = eq(_T_2882, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2886 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h020")) @[Decode.scala 13:65] + node _T_2888 = eq(_T_2886, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2890 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0c")) @[Decode.scala 13:65] + node _T_2892 = eq(_T_2890, UInt<32>("h04")) @[Decode.scala 13:121] + node _T_2894 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h048")) @[Decode.scala 13:65] + node _T_2896 = eq(_T_2894, UInt<32>("h048")) @[Decode.scala 13:121] + node _T_2898 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04050")) @[Decode.scala 13:65] + node _T_2900 = eq(_T_2898, UInt<32>("h04050")) @[Decode.scala 13:121] + node _T_2902 = or(UInt<1>("h00"), _T_2884) @[Decode.scala 14:30] + node _T_2903 = or(_T_2902, _T_2888) @[Decode.scala 14:30] + node _T_2904 = or(_T_2903, _T_2892) @[Decode.scala 14:30] + node _T_2905 = or(_T_2904, _T_2896) @[Decode.scala 14:30] + node _T_2906 = or(_T_2905, _T_2900) @[Decode.scala 14:30] + node _T_2908 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h048")) @[Decode.scala 13:65] + node _T_2910 = eq(_T_2908, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2912 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h018")) @[Decode.scala 13:65] + node _T_2914 = eq(_T_2912, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2916 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04008")) @[Decode.scala 13:65] + node _T_2918 = eq(_T_2916, UInt<32>("h04000")) @[Decode.scala 13:121] + node _T_2920 = or(UInt<1>("h00"), _T_2910) @[Decode.scala 14:30] + node _T_2921 = or(_T_2920, _T_2858) @[Decode.scala 14:30] + node _T_2922 = or(_T_2921, _T_2914) @[Decode.scala 14:30] + node _T_2923 = or(_T_2922, _T_2918) @[Decode.scala 14:30] + node _T_2924 = cat(_T_2923, _T_2906) @[Cat.scala 30:58] + node _T_2926 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04004")) @[Decode.scala 13:65] + node _T_2928 = eq(_T_2926, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2930 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h050")) @[Decode.scala 13:65] + node _T_2932 = eq(_T_2930, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2934 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h024")) @[Decode.scala 13:65] + node _T_2936 = eq(_T_2934, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2938 = or(UInt<1>("h00"), _T_2928) @[Decode.scala 14:30] + node _T_2939 = or(_T_2938, _T_2932) @[Decode.scala 14:30] + node _T_2940 = or(_T_2939, _T_2858) @[Decode.scala 14:30] + node _T_2941 = or(_T_2940, _T_2936) @[Decode.scala 14:30] + node _T_2942 = or(_T_2941, _T_2914) @[Decode.scala 14:30] + node _T_2944 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h034")) @[Decode.scala 13:65] + node _T_2946 = eq(_T_2944, UInt<32>("h014")) @[Decode.scala 13:121] + node _T_2948 = or(UInt<1>("h00"), _T_2946) @[Decode.scala 14:30] + node _T_2949 = or(_T_2948, _T_2896) @[Decode.scala 14:30] + node _T_2950 = cat(_T_2949, _T_2942) @[Cat.scala 30:58] + node _T_2952 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h018")) @[Decode.scala 13:65] + node _T_2954 = eq(_T_2952, UInt<32>("h08")) @[Decode.scala 13:121] + node _T_2956 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h044")) @[Decode.scala 13:65] + node _T_2958 = eq(_T_2956, UInt<32>("h040")) @[Decode.scala 13:121] + node _T_2960 = or(UInt<1>("h00"), _T_2954) @[Decode.scala 14:30] + node _T_2961 = or(_T_2960, _T_2958) @[Decode.scala 14:30] + node _T_2963 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h014")) @[Decode.scala 13:65] + node _T_2965 = eq(_T_2963, UInt<32>("h014")) @[Decode.scala 13:121] + node _T_2967 = or(UInt<1>("h00"), _T_2954) @[Decode.scala 14:30] + node _T_2968 = or(_T_2967, _T_2965) @[Decode.scala 14:30] + node _T_2970 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h030")) @[Decode.scala 13:65] + node _T_2972 = eq(_T_2970, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2974 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0201c")) @[Decode.scala 13:65] + node _T_2976 = eq(_T_2974, UInt<32>("h04")) @[Decode.scala 13:121] + node _T_2978 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h014")) @[Decode.scala 13:65] + node _T_2980 = eq(_T_2978, UInt<32>("h010")) @[Decode.scala 13:121] + node _T_2982 = or(UInt<1>("h00"), _T_2972) @[Decode.scala 14:30] + node _T_2983 = or(_T_2982, _T_2976) @[Decode.scala 14:30] + node _T_2984 = or(_T_2983, _T_2980) @[Decode.scala 14:30] + node _T_2985 = cat(_T_2984, _T_2968) @[Cat.scala 30:58] + node _T_2986 = cat(_T_2985, _T_2961) @[Cat.scala 30:58] + node _T_2988 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010")) @[Decode.scala 13:65] + node _T_2990 = eq(_T_2988, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2992 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h08")) @[Decode.scala 13:65] + node _T_2994 = eq(_T_2992, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_2996 = or(UInt<1>("h00"), _T_2990) @[Decode.scala 14:30] + node _T_2997 = or(_T_2996, _T_2994) @[Decode.scala 14:30] + node _T_2999 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03054")) @[Decode.scala 13:65] + node _T_3001 = eq(_T_2999, UInt<32>("h01010")) @[Decode.scala 13:121] + node _T_3003 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01058")) @[Decode.scala 13:65] + node _T_3005 = eq(_T_3003, UInt<32>("h01040")) @[Decode.scala 13:121] + node _T_3007 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07044")) @[Decode.scala 13:65] + node _T_3009 = eq(_T_3007, UInt<32>("h07000")) @[Decode.scala 13:121] + node _T_3011 = or(UInt<1>("h00"), _T_3001) @[Decode.scala 14:30] + node _T_3012 = or(_T_3011, _T_3005) @[Decode.scala 14:30] + node _T_3013 = or(_T_3012, _T_3009) @[Decode.scala 14:30] + node _T_3015 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04054")) @[Decode.scala 13:65] + node _T_3017 = eq(_T_3015, UInt<32>("h040")) @[Decode.scala 13:121] + node _T_3019 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02058")) @[Decode.scala 13:65] + node _T_3021 = eq(_T_3019, UInt<32>("h02040")) @[Decode.scala 13:121] + node _T_3023 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03054")) @[Decode.scala 13:65] + node _T_3025 = eq(_T_3023, UInt<32>("h03010")) @[Decode.scala 13:121] + node _T_3027 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h06054")) @[Decode.scala 13:65] + node _T_3029 = eq(_T_3027, UInt<32>("h06010")) @[Decode.scala 13:121] + node _T_3031 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040003034")) @[Decode.scala 13:65] + node _T_3033 = eq(_T_3031, UInt<32>("h040000030")) @[Decode.scala 13:121] + node _T_3035 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040001054")) @[Decode.scala 13:65] + node _T_3037 = eq(_T_3035, UInt<32>("h040001010")) @[Decode.scala 13:121] + node _T_3039 = or(UInt<1>("h00"), _T_3017) @[Decode.scala 14:30] + node _T_3040 = or(_T_3039, _T_3021) @[Decode.scala 14:30] + node _T_3041 = or(_T_3040, _T_3025) @[Decode.scala 14:30] + node _T_3042 = or(_T_3041, _T_3029) @[Decode.scala 14:30] + node _T_3043 = or(_T_3042, _T_3033) @[Decode.scala 14:30] + node _T_3044 = or(_T_3043, _T_3037) @[Decode.scala 14:30] + node _T_3046 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02054")) @[Decode.scala 13:65] + node _T_3048 = eq(_T_3046, UInt<32>("h02010")) @[Decode.scala 13:121] + node _T_3050 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040004054")) @[Decode.scala 13:65] + node _T_3052 = eq(_T_3050, UInt<32>("h04010")) @[Decode.scala 13:121] + node _T_3054 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h05054")) @[Decode.scala 13:65] + node _T_3056 = eq(_T_3054, UInt<32>("h04010")) @[Decode.scala 13:121] + node _T_3058 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04058")) @[Decode.scala 13:65] + node _T_3060 = eq(_T_3058, UInt<32>("h04040")) @[Decode.scala 13:121] + node _T_3062 = or(UInt<1>("h00"), _T_3048) @[Decode.scala 14:30] + node _T_3063 = or(_T_3062, _T_3052) @[Decode.scala 14:30] + node _T_3064 = or(_T_3063, _T_3056) @[Decode.scala 14:30] + node _T_3065 = or(_T_3064, _T_3060) @[Decode.scala 14:30] + node _T_3067 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h06054")) @[Decode.scala 13:65] + node _T_3069 = eq(_T_3067, UInt<32>("h02010")) @[Decode.scala 13:121] + node _T_3071 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040003054")) @[Decode.scala 13:65] + node _T_3073 = eq(_T_3071, UInt<32>("h040001010")) @[Decode.scala 13:121] + node _T_3075 = or(UInt<1>("h00"), _T_3069) @[Decode.scala 14:30] + node _T_3076 = or(_T_3075, _T_3060) @[Decode.scala 14:30] + node _T_3077 = or(_T_3076, _T_3033) @[Decode.scala 14:30] + node _T_3078 = or(_T_3077, _T_3073) @[Decode.scala 14:30] + node _T_3079 = cat(_T_3044, _T_3013) @[Cat.scala 30:58] + node _T_3080 = cat(_T_3078, _T_3065) @[Cat.scala 30:58] + node _T_3081 = cat(_T_3080, _T_3079) @[Cat.scala 30:58] + node _T_3083 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0405f")) @[Decode.scala 13:65] + node _T_3085 = eq(_T_3083, UInt<32>("h03")) @[Decode.scala 13:121] + node _T_3087 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0107f")) @[Decode.scala 13:65] + node _T_3089 = eq(_T_3087, UInt<32>("h03")) @[Decode.scala 13:121] + node _T_3091 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0707f")) @[Decode.scala 13:65] + node _T_3093 = eq(_T_3091, UInt<32>("h0100f")) @[Decode.scala 13:121] + node _T_3095 = or(UInt<1>("h00"), _T_3085) @[Decode.scala 14:30] + node _T_3096 = or(_T_3095, _T_2605) @[Decode.scala 14:30] + node _T_3097 = or(_T_3096, _T_3089) @[Decode.scala 14:30] + node _T_3098 = or(_T_3097, _T_3093) @[Decode.scala 14:30] + node _T_3099 = or(_T_3098, _T_2661) @[Decode.scala 14:30] + node _T_3100 = or(_T_3099, _T_2669) @[Decode.scala 14:30] + node _T_3101 = or(_T_3100, _T_2693) @[Decode.scala 14:30] + node _T_3102 = or(_T_3101, _T_2697) @[Decode.scala 14:30] + node _T_3104 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02008")) @[Decode.scala 13:65] + node _T_3106 = eq(_T_3104, UInt<32>("h08")) @[Decode.scala 13:121] + node _T_3108 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h028")) @[Decode.scala 13:65] + node _T_3110 = eq(_T_3108, UInt<32>("h020")) @[Decode.scala 13:121] + node _T_3112 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h018000020")) @[Decode.scala 13:65] + node _T_3114 = eq(_T_3112, UInt<32>("h018000020")) @[Decode.scala 13:121] + node _T_3116 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h020000020")) @[Decode.scala 13:65] + node _T_3118 = eq(_T_3116, UInt<32>("h020000020")) @[Decode.scala 13:121] + node _T_3120 = or(UInt<1>("h00"), _T_3106) @[Decode.scala 14:30] + node _T_3121 = or(_T_3120, _T_3110) @[Decode.scala 14:30] + node _T_3122 = or(_T_3121, _T_3114) @[Decode.scala 14:30] + node _T_3123 = or(_T_3122, _T_3118) @[Decode.scala 14:30] + node _T_3125 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010002008")) @[Decode.scala 13:65] + node _T_3127 = eq(_T_3125, UInt<32>("h010002008")) @[Decode.scala 13:121] + node _T_3129 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040002008")) @[Decode.scala 13:65] + node _T_3131 = eq(_T_3129, UInt<32>("h040002008")) @[Decode.scala 13:121] + node _T_3133 = or(UInt<1>("h00"), _T_3127) @[Decode.scala 14:30] + node _T_3134 = or(_T_3133, _T_3131) @[Decode.scala 14:30] + node _T_3136 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h08000008")) @[Decode.scala 13:65] + node _T_3138 = eq(_T_3136, UInt<32>("h08000008")) @[Decode.scala 13:121] + node _T_3140 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010000008")) @[Decode.scala 13:65] + node _T_3142 = eq(_T_3140, UInt<32>("h010000008")) @[Decode.scala 13:121] + node _T_3144 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h080000008")) @[Decode.scala 13:65] + node _T_3146 = eq(_T_3144, UInt<32>("h080000008")) @[Decode.scala 13:121] + node _T_3148 = or(UInt<1>("h00"), _T_3106) @[Decode.scala 14:30] + node _T_3149 = or(_T_3148, _T_3138) @[Decode.scala 14:30] + node _T_3150 = or(_T_3149, _T_3142) @[Decode.scala 14:30] + node _T_3151 = or(_T_3150, _T_3146) @[Decode.scala 14:30] + node _T_3153 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h018002008")) @[Decode.scala 13:65] + node _T_3155 = eq(_T_3153, UInt<32>("h02008")) @[Decode.scala 13:121] + node _T_3157 = or(UInt<1>("h00"), _T_3155) @[Decode.scala 14:30] + node _T_3159 = cat(_T_3134, _T_3123) @[Cat.scala 30:58] + node _T_3160 = cat(UInt<1>("h00"), _T_3157) @[Cat.scala 30:58] + node _T_3161 = cat(_T_3160, _T_3151) @[Cat.scala 30:58] + node _T_3162 = cat(_T_3161, _T_3159) @[Cat.scala 30:58] + node _T_3164 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01000")) @[Decode.scala 13:65] + node _T_3166 = eq(_T_3164, UInt<32>("h01000")) @[Decode.scala 13:121] + node _T_3168 = or(UInt<1>("h00"), _T_3166) @[Decode.scala 14:30] + node _T_3170 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02000")) @[Decode.scala 13:65] + node _T_3172 = eq(_T_3170, UInt<32>("h02000")) @[Decode.scala 13:121] + node _T_3174 = or(UInt<1>("h00"), _T_3172) @[Decode.scala 14:30] + node _T_3176 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h04000")) @[Decode.scala 13:65] + node _T_3178 = eq(_T_3176, UInt<32>("h04000")) @[Decode.scala 13:121] + node _T_3180 = or(UInt<1>("h00"), _T_3178) @[Decode.scala 14:30] + node _T_3181 = cat(_T_3180, _T_3174) @[Cat.scala 30:58] + node _T_3182 = cat(_T_3181, _T_3168) @[Cat.scala 30:58] + node _T_3184 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h080000060")) @[Decode.scala 13:65] + node _T_3186 = eq(_T_3184, UInt<32>("h040")) @[Decode.scala 13:121] + node _T_3188 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010000060")) @[Decode.scala 13:65] + node _T_3190 = eq(_T_3188, UInt<32>("h040")) @[Decode.scala 13:121] + node _T_3192 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h070")) @[Decode.scala 13:65] + node _T_3194 = eq(_T_3192, UInt<32>("h040")) @[Decode.scala 13:121] + node _T_3196 = or(UInt<1>("h00"), _T_3186) @[Decode.scala 14:30] + node _T_3197 = or(_T_3196, _T_3190) @[Decode.scala 14:30] + node _T_3198 = or(_T_3197, _T_3194) @[Decode.scala 14:30] + node _T_3200 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h07c")) @[Decode.scala 13:65] + node _T_3202 = eq(_T_3200, UInt<32>("h024")) @[Decode.scala 13:121] + node _T_3204 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h040000060")) @[Decode.scala 13:65] + node _T_3206 = eq(_T_3204, UInt<32>("h040")) @[Decode.scala 13:121] + node _T_3208 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h090000060")) @[Decode.scala 13:65] + node _T_3210 = eq(_T_3208, UInt<32>("h010000040")) @[Decode.scala 13:121] + node _T_3212 = or(UInt<1>("h00"), _T_3202) @[Decode.scala 14:30] + node _T_3213 = or(_T_3212, _T_3206) @[Decode.scala 14:30] + node _T_3214 = or(_T_3213, _T_3194) @[Decode.scala 14:30] + node _T_3215 = or(_T_3214, _T_3210) @[Decode.scala 14:30] + node _T_3217 = or(UInt<1>("h00"), _T_3194) @[Decode.scala 14:30] + node _T_3219 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03c")) @[Decode.scala 13:65] + node _T_3221 = eq(_T_3219, UInt<32>("h04")) @[Decode.scala 13:121] + node _T_3223 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h010000060")) @[Decode.scala 13:65] + node _T_3225 = eq(_T_3223, UInt<32>("h010000040")) @[Decode.scala 13:121] + node _T_3227 = or(UInt<1>("h00"), _T_3221) @[Decode.scala 14:30] + node _T_3228 = or(_T_3227, _T_3186) @[Decode.scala 14:30] + node _T_3229 = or(_T_3228, _T_3194) @[Decode.scala 14:30] + node _T_3230 = or(_T_3229, _T_3225) @[Decode.scala 14:30] + node _T_3232 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02000074")) @[Decode.scala 13:65] + node _T_3234 = eq(_T_3232, UInt<32>("h02000030")) @[Decode.scala 13:121] + node _T_3236 = or(UInt<1>("h00"), _T_3234) @[Decode.scala 14:30] + node _T_3238 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h064")) @[Decode.scala 13:65] + node _T_3240 = eq(_T_3238, UInt<32>("h00")) @[Decode.scala 13:121] + node _T_3242 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h050")) @[Decode.scala 13:65] + node _T_3244 = eq(_T_3242, UInt<32>("h010")) @[Decode.scala 13:121] + node _T_3246 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02024")) @[Decode.scala 13:65] + node _T_3248 = eq(_T_3246, UInt<32>("h024")) @[Decode.scala 13:121] + node _T_3250 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h028")) @[Decode.scala 13:65] + node _T_3252 = eq(_T_3250, UInt<32>("h028")) @[Decode.scala 13:121] + node _T_3254 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01030")) @[Decode.scala 13:65] + node _T_3256 = eq(_T_3254, UInt<32>("h01030")) @[Decode.scala 13:121] + node _T_3258 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02030")) @[Decode.scala 13:65] + node _T_3260 = eq(_T_3258, UInt<32>("h02030")) @[Decode.scala 13:121] + node _T_3262 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h090000010")) @[Decode.scala 13:65] + node _T_3264 = eq(_T_3262, UInt<32>("h080000010")) @[Decode.scala 13:121] + node _T_3266 = or(UInt<1>("h00"), _T_3240) @[Decode.scala 14:30] + node _T_3267 = or(_T_3266, _T_3244) @[Decode.scala 14:30] + node _T_3268 = or(_T_3267, _T_3248) @[Decode.scala 14:30] + node _T_3269 = or(_T_3268, _T_3252) @[Decode.scala 14:30] + node _T_3270 = or(_T_3269, _T_3256) @[Decode.scala 14:30] + node _T_3271 = or(_T_3270, _T_3260) @[Decode.scala 14:30] + node _T_3272 = or(_T_3271, _T_3264) @[Decode.scala 14:30] + node _T_3274 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h01070")) @[Decode.scala 13:65] + node _T_3276 = eq(_T_3274, UInt<32>("h01070")) @[Decode.scala 13:121] + node _T_3278 = or(UInt<1>("h00"), _T_3276) @[Decode.scala 14:30] + node _T_3280 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02070")) @[Decode.scala 13:65] + node _T_3282 = eq(_T_3280, UInt<32>("h02070")) @[Decode.scala 13:121] + node _T_3284 = or(UInt<1>("h00"), _T_3282) @[Decode.scala 14:30] + node _T_3286 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03070")) @[Decode.scala 13:65] + node _T_3288 = eq(_T_3286, UInt<32>("h070")) @[Decode.scala 13:121] + node _T_3290 = or(UInt<1>("h00"), _T_3288) @[Decode.scala 14:30] + node _T_3291 = cat(_T_3290, _T_3284) @[Cat.scala 30:58] + node _T_3292 = cat(_T_3291, _T_3278) @[Cat.scala 30:58] + node _T_3294 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03058")) @[Decode.scala 13:65] + node _T_3296 = eq(_T_3294, UInt<32>("h01008")) @[Decode.scala 13:121] + node _T_3298 = or(UInt<1>("h00"), _T_3296) @[Decode.scala 14:30] + node _T_3300 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h03058")) @[Decode.scala 13:65] + node _T_3302 = eq(_T_3300, UInt<32>("h08")) @[Decode.scala 13:121] + node _T_3304 = or(UInt<1>("h00"), _T_3302) @[Decode.scala 14:30] + node _T_3306 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h06048")) @[Decode.scala 13:65] + node _T_3308 = eq(_T_3306, UInt<32>("h02008")) @[Decode.scala 13:121] + node _T_3310 = or(UInt<1>("h00"), _T_3308) @[Decode.scala 14:30] + node _T_3312 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0105c")) @[Decode.scala 13:65] + node _T_3314 = eq(_T_3312, UInt<32>("h01004")) @[Decode.scala 13:121] + node _T_3316 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h02000060")) @[Decode.scala 13:65] + node _T_3318 = eq(_T_3316, UInt<32>("h02000040")) @[Decode.scala 13:121] + node _T_3320 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>("h0d0000070")) @[Decode.scala 13:65] + node _T_3322 = eq(_T_3320, UInt<32>("h040000050")) @[Decode.scala 13:121] + node _T_3324 = or(UInt<1>("h00"), _T_3314) @[Decode.scala 14:30] + node _T_3325 = or(_T_3324, _T_3318) @[Decode.scala 14:30] + node _T_3326 = or(_T_3325, _T_3322) @[Decode.scala 14:30] + id_ctrl.legal <= _T_2803 @[IDecode.scala 65:42] + id_ctrl.fp <= _T_2814 @[IDecode.scala 65:42] + id_ctrl.rocc <= UInt<1>("h00") @[IDecode.scala 65:42] + id_ctrl.branch <= _T_2821 @[IDecode.scala 65:42] + id_ctrl.jal <= _T_2827 @[IDecode.scala 65:42] + id_ctrl.jalr <= _T_2833 @[IDecode.scala 65:42] + id_ctrl.rxs2 <= _T_2854 @[IDecode.scala 65:42] + id_ctrl.rxs1 <= _T_2880 @[IDecode.scala 65:42] + id_ctrl.sel_alu2 <= _T_2924 @[IDecode.scala 65:42] + id_ctrl.sel_alu1 <= _T_2950 @[IDecode.scala 65:42] + id_ctrl.sel_imm <= _T_2986 @[IDecode.scala 65:42] + id_ctrl.alu_dw <= _T_2997 @[IDecode.scala 65:42] + id_ctrl.alu_fn <= _T_3081 @[IDecode.scala 65:42] + id_ctrl.mem <= _T_3102 @[IDecode.scala 65:42] + id_ctrl.mem_cmd <= _T_3162 @[IDecode.scala 65:42] + id_ctrl.mem_type <= _T_3182 @[IDecode.scala 65:42] + id_ctrl.rfs1 <= _T_3198 @[IDecode.scala 65:42] + id_ctrl.rfs2 <= _T_3215 @[IDecode.scala 65:42] + id_ctrl.rfs3 <= _T_3217 @[IDecode.scala 65:42] + id_ctrl.wfd <= _T_3230 @[IDecode.scala 65:42] + id_ctrl.div <= _T_3236 @[IDecode.scala 65:42] + id_ctrl.wxd <= _T_3272 @[IDecode.scala 65:42] + id_ctrl.csr <= _T_3292 @[IDecode.scala 65:42] + id_ctrl.fence_i <= _T_3298 @[IDecode.scala 65:42] + id_ctrl.fence <= _T_3304 @[IDecode.scala 65:42] + id_ctrl.amo <= _T_3310 @[IDecode.scala 65:42] + id_ctrl.dp <= _T_3326 @[IDecode.scala 65:42] + wire id_load_use : UInt<1> @[Rocket.scala 177:25] + id_load_use is invalid @[Rocket.scala 177:25] + reg id_reg_fence : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Rocket.scala 178:25] + cmem _T_3331 : UInt<64>[31] @[Rocket.scala 682:23] + wire id_rs_0 : UInt @[Rocket.scala 688:26] + id_rs_0 is invalid @[Rocket.scala 688:26] + node _T_3335 = eq(ibuf.io.inst[0].bits.inst.rs1, UInt<1>("h00")) @[Rocket.scala 689:45] + node _T_3336 = and(UInt<1>("h00"), _T_3335) @[Rocket.scala 689:37] + node _T_3338 = bits(ibuf.io.inst[0].bits.inst.rs1, 4, 0) @[Rocket.scala 683:44] + node _T_3339 = not(_T_3338) @[Rocket.scala 683:39] + infer mport _T_3340 = _T_3331[_T_3339], clock + node _T_3341 = mux(_T_3336, UInt<1>("h00"), _T_3340) @[Rocket.scala 689:25] + id_rs_0 <= _T_3341 @[Rocket.scala 689:19] + wire id_rs_1 : UInt @[Rocket.scala 688:26] + id_rs_1 is invalid @[Rocket.scala 688:26] + node _T_3345 = eq(ibuf.io.inst[0].bits.inst.rs2, UInt<1>("h00")) @[Rocket.scala 689:45] + node _T_3346 = and(UInt<1>("h00"), _T_3345) @[Rocket.scala 689:37] + node _T_3348 = bits(ibuf.io.inst[0].bits.inst.rs2, 4, 0) @[Rocket.scala 683:44] + node _T_3349 = not(_T_3348) @[Rocket.scala 683:39] + infer mport _T_3350 = _T_3331[_T_3349], clock + node _T_3351 = mux(_T_3346, UInt<1>("h00"), _T_3350) @[Rocket.scala 689:25] + id_rs_1 <= _T_3351 @[Rocket.scala 689:19] + wire ctrl_killd : UInt<1> @[Rocket.scala 183:24] + ctrl_killd is invalid @[Rocket.scala 183:24] + node _T_3353 = asSInt(ibuf.io.pc) @[Rocket.scala 184:28] + node _T_3356 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 704:24] + node _T_3358 = bits(ibuf.io.inst[0].bits.inst.bits, 31, 31) @[Rocket.scala 704:48] + node _T_3359 = asSInt(_T_3358) @[Rocket.scala 704:53] + node _T_3360 = mux(_T_3356, asSInt(UInt<1>("h00")), _T_3359) @[Rocket.scala 704:19] + node _T_3362 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 705:26] + node _T_3363 = bits(ibuf.io.inst[0].bits.inst.bits, 30, 20) @[Rocket.scala 705:41] + node _T_3364 = asSInt(_T_3363) @[Rocket.scala 705:49] + node _T_3365 = mux(_T_3362, _T_3364, _T_3360) @[Rocket.scala 705:21] + node _T_3367 = neq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 706:26] + node _T_3369 = neq(UInt<3>("h03"), UInt<3>("h03")) @[Rocket.scala 706:43] + node _T_3370 = and(_T_3367, _T_3369) @[Rocket.scala 706:36] + node _T_3371 = bits(ibuf.io.inst[0].bits.inst.bits, 19, 12) @[Rocket.scala 706:65] + node _T_3372 = asSInt(_T_3371) @[Rocket.scala 706:73] + node _T_3373 = mux(_T_3370, _T_3360, _T_3372) @[Rocket.scala 706:21] + node _T_3375 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 707:23] + node _T_3377 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 707:40] + node _T_3378 = or(_T_3375, _T_3377) @[Rocket.scala 707:33] + node _T_3381 = eq(UInt<3>("h03"), UInt<3>("h03")) @[Rocket.scala 708:23] + node _T_3382 = bits(ibuf.io.inst[0].bits.inst.bits, 20, 20) @[Rocket.scala 708:39] + node _T_3383 = asSInt(_T_3382) @[Rocket.scala 708:44] + node _T_3385 = eq(UInt<3>("h03"), UInt<3>("h01")) @[Rocket.scala 709:23] + node _T_3386 = bits(ibuf.io.inst[0].bits.inst.bits, 7, 7) @[Rocket.scala 709:39] + node _T_3387 = asSInt(_T_3386) @[Rocket.scala 709:43] + node _T_3388 = mux(_T_3385, _T_3387, _T_3360) @[Rocket.scala 709:18] + node _T_3389 = mux(_T_3381, _T_3383, _T_3388) @[Rocket.scala 708:18] + node _T_3390 = mux(_T_3378, asSInt(UInt<1>("h00")), _T_3389) @[Rocket.scala 707:18] + node _T_3392 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 710:25] + node _T_3394 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 710:42] + node _T_3395 = or(_T_3392, _T_3394) @[Rocket.scala 710:35] + node _T_3397 = bits(ibuf.io.inst[0].bits.inst.bits, 30, 25) @[Rocket.scala 710:66] + node _T_3398 = mux(_T_3395, UInt<1>("h00"), _T_3397) @[Rocket.scala 710:20] + node _T_3400 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 711:24] + node _T_3403 = eq(UInt<3>("h03"), UInt<3>("h00")) @[Rocket.scala 712:24] + node _T_3405 = eq(UInt<3>("h03"), UInt<3>("h01")) @[Rocket.scala 712:41] + node _T_3406 = or(_T_3403, _T_3405) @[Rocket.scala 712:34] + node _T_3407 = bits(ibuf.io.inst[0].bits.inst.bits, 11, 8) @[Rocket.scala 712:57] + node _T_3409 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 713:24] + node _T_3410 = bits(ibuf.io.inst[0].bits.inst.bits, 19, 16) @[Rocket.scala 713:39] + node _T_3411 = bits(ibuf.io.inst[0].bits.inst.bits, 24, 21) @[Rocket.scala 713:52] + node _T_3412 = mux(_T_3409, _T_3410, _T_3411) @[Rocket.scala 713:19] + node _T_3413 = mux(_T_3406, _T_3407, _T_3412) @[Rocket.scala 712:19] + node _T_3414 = mux(_T_3400, UInt<1>("h00"), _T_3413) @[Rocket.scala 711:19] + node _T_3416 = eq(UInt<3>("h03"), UInt<3>("h00")) @[Rocket.scala 714:22] + node _T_3417 = bits(ibuf.io.inst[0].bits.inst.bits, 7, 7) @[Rocket.scala 714:37] + node _T_3419 = eq(UInt<3>("h03"), UInt<3>("h04")) @[Rocket.scala 715:22] + node _T_3420 = bits(ibuf.io.inst[0].bits.inst.bits, 20, 20) @[Rocket.scala 715:37] + node _T_3422 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 716:22] + node _T_3423 = bits(ibuf.io.inst[0].bits.inst.bits, 15, 15) @[Rocket.scala 716:37] + node _T_3425 = mux(_T_3422, _T_3423, UInt<1>("h00")) @[Rocket.scala 716:17] + node _T_3426 = mux(_T_3419, _T_3420, _T_3425) @[Rocket.scala 715:17] + node _T_3427 = mux(_T_3416, _T_3417, _T_3426) @[Rocket.scala 714:17] + node _T_3428 = cat(_T_3398, _T_3414) @[Cat.scala 30:58] + node _T_3429 = cat(_T_3428, _T_3427) @[Cat.scala 30:58] + node _T_3430 = asUInt(_T_3390) @[Cat.scala 30:58] + node _T_3431 = asUInt(_T_3373) @[Cat.scala 30:58] + node _T_3432 = cat(_T_3431, _T_3430) @[Cat.scala 30:58] + node _T_3433 = asUInt(_T_3365) @[Cat.scala 30:58] + node _T_3434 = asUInt(_T_3360) @[Cat.scala 30:58] + node _T_3435 = cat(_T_3434, _T_3433) @[Cat.scala 30:58] + node _T_3436 = cat(_T_3435, _T_3432) @[Cat.scala 30:58] + node _T_3437 = cat(_T_3436, _T_3429) @[Cat.scala 30:58] + node _T_3438 = asSInt(_T_3437) @[Rocket.scala 718:53] + node _T_3439 = add(_T_3353, _T_3438) @[Rocket.scala 184:35] + node _T_3440 = tail(_T_3439, 1) @[Rocket.scala 184:35] + node _T_3441 = asSInt(_T_3440) @[Rocket.scala 184:35] + node id_npc = asUInt(_T_3441) @[Rocket.scala 184:65] + node _T_3444 = eq(ctrl_killd, UInt<1>("h00")) @[Rocket.scala 185:34] + node _T_3445 = and(UInt<1>("h00"), _T_3444) @[Rocket.scala 185:31] + node _T_3446 = and(_T_3445, id_ctrl.jal) @[Rocket.scala 185:46] + take_pc_id <= _T_3446 @[Rocket.scala 185:14] + inst csr of CSRFile @[Rocket.scala 187:19] + csr.io is invalid + csr.clock <= clock + csr.reset <= reset + node _T_3450 = eq(id_ctrl.csr, UInt<3>("h02")) @[Package.scala 7:47] + node _T_3451 = eq(id_ctrl.csr, UInt<3>("h03")) @[Package.scala 7:47] + node _T_3452 = eq(id_ctrl.csr, UInt<3>("h01")) @[Package.scala 7:47] + node _T_3453 = or(_T_3450, _T_3451) @[Package.scala 7:62] + node id_csr_en = or(_T_3453, _T_3452) @[Package.scala 7:62] + node id_system_insn = geq(id_ctrl.csr, UInt<3>("h04")) @[Rocket.scala 189:36] + node _T_3457 = eq(id_ctrl.csr, UInt<3>("h02")) @[Package.scala 7:47] + node _T_3458 = eq(id_ctrl.csr, UInt<3>("h03")) @[Package.scala 7:47] + node _T_3459 = or(_T_3457, _T_3458) @[Package.scala 7:62] + node _T_3461 = eq(ibuf.io.inst[0].bits.inst.rs1, UInt<1>("h00")) @[Rocket.scala 190:67] + node id_csr_ren = and(_T_3459, _T_3461) @[Rocket.scala 190:54] + node id_csr = mux(id_csr_ren, UInt<3>("h05"), id_ctrl.csr) @[Rocket.scala 191:19] + node _T_3464 = eq(id_csr_ren, UInt<1>("h00")) @[Rocket.scala 192:54] + node _T_3465 = and(id_csr_en, _T_3464) @[Rocket.scala 192:51] + node _T_3466 = and(_T_3465, csr.io.decode.write_flush) @[Rocket.scala 192:66] + node id_csr_flush = or(id_system_insn, _T_3466) @[Rocket.scala 192:37] + node _T_3468 = eq(id_ctrl.legal, UInt<1>("h00")) @[Rocket.scala 194:25] + node _T_3469 = bits(csr.io.status.isa, 12, 12) @[Rocket.scala 195:38] + node _T_3471 = eq(_T_3469, UInt<1>("h00")) @[Rocket.scala 195:20] + node _T_3472 = and(id_ctrl.div, _T_3471) @[Rocket.scala 195:17] + node _T_3473 = or(_T_3468, _T_3472) @[Rocket.scala 194:40] + node _T_3474 = bits(csr.io.status.isa, 0, 0) @[Rocket.scala 196:38] + node _T_3476 = eq(_T_3474, UInt<1>("h00")) @[Rocket.scala 196:20] + node _T_3477 = and(id_ctrl.amo, _T_3476) @[Rocket.scala 196:17] + node _T_3478 = or(_T_3473, _T_3477) @[Rocket.scala 195:48] + node _T_3479 = or(csr.io.decode.fp_illegal, io.fpu.illegal_rm) @[Rocket.scala 197:45] + node _T_3480 = and(id_ctrl.fp, _T_3479) @[Rocket.scala 197:16] + node _T_3481 = or(_T_3478, _T_3480) @[Rocket.scala 196:48] + node _T_3482 = bits(csr.io.status.isa, 3, 3) @[Rocket.scala 198:37] + node _T_3484 = eq(_T_3482, UInt<1>("h00")) @[Rocket.scala 198:19] + node _T_3485 = and(id_ctrl.dp, _T_3484) @[Rocket.scala 198:16] + node _T_3486 = or(_T_3481, _T_3485) @[Rocket.scala 197:67] + node _T_3487 = bits(csr.io.status.isa, 2, 2) @[Rocket.scala 199:51] + node _T_3489 = eq(_T_3487, UInt<1>("h00")) @[Rocket.scala 199:33] + node _T_3490 = and(ibuf.io.inst[0].bits.rvc, _T_3489) @[Rocket.scala 199:30] + node _T_3491 = or(_T_3486, _T_3490) @[Rocket.scala 198:47] + node _T_3492 = and(id_ctrl.rocc, csr.io.decode.rocc_illegal) @[Rocket.scala 200:18] + node _T_3493 = or(_T_3491, _T_3492) @[Rocket.scala 199:61] + node _T_3495 = eq(id_csr_ren, UInt<1>("h00")) @[Rocket.scala 201:49] + node _T_3496 = and(_T_3495, csr.io.decode.write_illegal) @[Rocket.scala 201:61] + node _T_3497 = or(csr.io.decode.read_illegal, _T_3496) @[Rocket.scala 201:46] + node _T_3498 = and(id_csr_en, _T_3497) @[Rocket.scala 201:15] + node _T_3499 = or(_T_3493, _T_3498) @[Rocket.scala 200:48] + node _T_3500 = and(id_system_insn, csr.io.decode.system_illegal) @[Rocket.scala 202:20] + node id_illegal_insn = or(_T_3499, _T_3500) @[Rocket.scala 201:93] + node id_amo_aq = bits(ibuf.io.inst[0].bits.inst.bits, 26, 26) @[Rocket.scala 204:29] + node id_amo_rl = bits(ibuf.io.inst[0].bits.inst.bits, 25, 25) @[Rocket.scala 205:29] + node _T_3501 = and(id_ctrl.amo, id_amo_rl) @[Rocket.scala 206:52] + node id_fence_next = or(id_ctrl.fence, _T_3501) @[Rocket.scala 206:37] + node _T_3503 = eq(io.dmem.ordered, UInt<1>("h00")) @[Rocket.scala 207:21] + node id_mem_busy = or(_T_3503, io.dmem.req.valid) @[Rocket.scala 207:38] + node _T_3505 = and(ex_reg_valid, ex_ctrl.rocc) @[Rocket.scala 209:35] + node _T_3506 = or(io.rocc.busy, _T_3505) @[Rocket.scala 209:19] + node _T_3507 = and(mem_reg_valid, mem_ctrl.rocc) @[Rocket.scala 210:20] + node _T_3508 = or(_T_3506, _T_3507) @[Rocket.scala 209:51] + node _T_3509 = and(wb_reg_valid, wb_ctrl.rocc) @[Rocket.scala 210:53] + node _T_3510 = or(_T_3508, _T_3509) @[Rocket.scala 210:37] + node id_rocc_busy = and(UInt<1>("h00"), _T_3510) @[Rocket.scala 208:38] + node _T_3511 = and(id_reg_fence, id_mem_busy) @[Rocket.scala 211:49] + node _T_3512 = or(id_fence_next, _T_3511) @[Rocket.scala 211:33] + id_reg_fence <= _T_3512 @[Rocket.scala 211:16] + node _T_3513 = and(id_rocc_busy, id_ctrl.fence) @[Rocket.scala 212:34] + node _T_3514 = and(id_ctrl.amo, id_amo_aq) @[Rocket.scala 213:33] + node _T_3515 = or(_T_3514, id_ctrl.fence_i) @[Rocket.scala 213:46] + node _T_3516 = or(id_ctrl.mem, id_ctrl.rocc) @[Rocket.scala 213:97] + node _T_3517 = and(id_reg_fence, _T_3516) @[Rocket.scala 213:81] + node _T_3518 = or(_T_3515, _T_3517) @[Rocket.scala 213:65] + node _T_3519 = and(id_mem_busy, _T_3518) @[Rocket.scala 213:17] + node id_do_fence = or(_T_3513, _T_3519) @[Rocket.scala 212:51] + inst bpu of BreakpointUnit @[Rocket.scala 215:19] + bpu.io is invalid + bpu.clock <= clock + bpu.reset <= reset + bpu.io.status <- csr.io.status @[Rocket.scala 216:17] + bpu.io.bp <- csr.io.bp @[Rocket.scala 217:13] + bpu.io.pc <= ibuf.io.pc @[Rocket.scala 218:13] + bpu.io.ea <= mem_reg_wdata @[Rocket.scala 219:13] + node id_xcpt_if = or(ibuf.io.inst[0].bits.pf0, ibuf.io.inst[0].bits.pf1) @[Rocket.scala 221:45] + node _T_3552 = or(csr.io.interrupt, bpu.io.debug_if) @[Rocket.scala 645:26] + node _T_3553 = or(_T_3552, bpu.io.xcpt_if) @[Rocket.scala 645:26] + node _T_3554 = or(_T_3553, id_xcpt_if) @[Rocket.scala 645:26] + node id_xcpt = or(_T_3554, id_illegal_insn) @[Rocket.scala 645:26] + node _T_3555 = mux(id_xcpt_if, UInt<1>("h01"), UInt<2>("h02")) @[Mux.scala 31:69] + node _T_3556 = mux(bpu.io.xcpt_if, UInt<2>("h03"), _T_3555) @[Mux.scala 31:69] + node _T_3557 = mux(bpu.io.debug_if, UInt<4>("h0d"), _T_3556) @[Mux.scala 31:69] + node id_cause = mux(csr.io.interrupt, csr.io.interrupt_cause, _T_3557) @[Mux.scala 31:69] + node ex_waddr = bits(ex_reg_inst, 11, 7) @[Rocket.scala 235:29] + node mem_waddr = bits(mem_reg_inst, 11, 7) @[Rocket.scala 236:31] + node wb_waddr = bits(wb_reg_inst, 11, 7) @[Rocket.scala 237:29] + node _T_3561 = and(ex_reg_valid, ex_ctrl.wxd) @[Rocket.scala 240:19] + node _T_3562 = and(mem_reg_valid, mem_ctrl.wxd) @[Rocket.scala 241:20] + node _T_3564 = eq(mem_ctrl.mem, UInt<1>("h00")) @[Rocket.scala 241:39] + node _T_3565 = and(_T_3562, _T_3564) @[Rocket.scala 241:36] + node _T_3566 = and(mem_reg_valid, mem_ctrl.wxd) @[Rocket.scala 242:20] + node _T_3567 = eq(UInt<1>("h00"), ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 243:82] + node id_bypass_src_0_0 = and(UInt<1>("h01"), _T_3567) @[Rocket.scala 243:74] + node _T_3568 = eq(ex_waddr, ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 243:82] + node id_bypass_src_0_1 = and(_T_3561, _T_3568) @[Rocket.scala 243:74] + node _T_3569 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 243:82] + node id_bypass_src_0_2 = and(_T_3565, _T_3569) @[Rocket.scala 243:74] + node _T_3570 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 243:82] + node id_bypass_src_0_3 = and(_T_3566, _T_3570) @[Rocket.scala 243:74] + node _T_3571 = eq(UInt<1>("h00"), ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 243:82] + node id_bypass_src_1_0 = and(UInt<1>("h01"), _T_3571) @[Rocket.scala 243:74] + node _T_3572 = eq(ex_waddr, ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 243:82] + node id_bypass_src_1_1 = and(_T_3561, _T_3572) @[Rocket.scala 243:74] + node _T_3573 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 243:82] + node id_bypass_src_1_2 = and(_T_3565, _T_3573) @[Rocket.scala 243:74] + node _T_3574 = eq(mem_waddr, ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 243:82] + node id_bypass_src_1_3 = and(_T_3566, _T_3574) @[Rocket.scala 243:74] + wire bypass_mux : UInt[4] @[Rocket.scala 246:23] + bypass_mux is invalid @[Rocket.scala 246:23] + bypass_mux[0] <= UInt<1>("h00") @[Rocket.scala 246:23] + bypass_mux[1] <= mem_reg_wdata @[Rocket.scala 246:23] + bypass_mux[2] <= wb_reg_wdata @[Rocket.scala 246:23] + bypass_mux[3] <= io.dmem.resp.bits.data_word_bypass @[Rocket.scala 246:23] + reg ex_reg_rs_bypass : UInt<1>[2], clock @[Rocket.scala 247:29] + reg ex_reg_rs_lsb : UInt<2>[2], clock @[Rocket.scala 248:26] + reg ex_reg_rs_msb : UInt[2], clock @[Rocket.scala 249:26] + node _T_3605 = cat(ex_reg_rs_msb[0], ex_reg_rs_lsb[0]) @[Cat.scala 30:58] + node ex_rs_0 = mux(ex_reg_rs_bypass[0], bypass_mux[ex_reg_rs_lsb[0]], _T_3605) @[Rocket.scala 251:14] + node _T_3607 = cat(ex_reg_rs_msb[1], ex_reg_rs_lsb[1]) @[Cat.scala 30:58] + node ex_rs_1 = mux(ex_reg_rs_bypass[1], bypass_mux[ex_reg_rs_lsb[1]], _T_3607) @[Rocket.scala 251:14] + node _T_3609 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[Rocket.scala 704:24] + node _T_3611 = bits(ex_reg_inst, 31, 31) @[Rocket.scala 704:48] + node _T_3612 = asSInt(_T_3611) @[Rocket.scala 704:53] + node _T_3613 = mux(_T_3609, asSInt(UInt<1>("h00")), _T_3612) @[Rocket.scala 704:19] + node _T_3615 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) @[Rocket.scala 705:26] + node _T_3616 = bits(ex_reg_inst, 30, 20) @[Rocket.scala 705:41] + node _T_3617 = asSInt(_T_3616) @[Rocket.scala 705:49] + node _T_3618 = mux(_T_3615, _T_3617, _T_3613) @[Rocket.scala 705:21] + node _T_3620 = neq(ex_ctrl.sel_imm, UInt<3>("h02")) @[Rocket.scala 706:26] + node _T_3622 = neq(ex_ctrl.sel_imm, UInt<3>("h03")) @[Rocket.scala 706:43] + node _T_3623 = and(_T_3620, _T_3622) @[Rocket.scala 706:36] + node _T_3624 = bits(ex_reg_inst, 19, 12) @[Rocket.scala 706:65] + node _T_3625 = asSInt(_T_3624) @[Rocket.scala 706:73] + node _T_3626 = mux(_T_3623, _T_3613, _T_3625) @[Rocket.scala 706:21] + node _T_3628 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) @[Rocket.scala 707:23] + node _T_3630 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[Rocket.scala 707:40] + node _T_3631 = or(_T_3628, _T_3630) @[Rocket.scala 707:33] + node _T_3634 = eq(ex_ctrl.sel_imm, UInt<3>("h03")) @[Rocket.scala 708:23] + node _T_3635 = bits(ex_reg_inst, 20, 20) @[Rocket.scala 708:39] + node _T_3636 = asSInt(_T_3635) @[Rocket.scala 708:44] + node _T_3638 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) @[Rocket.scala 709:23] + node _T_3639 = bits(ex_reg_inst, 7, 7) @[Rocket.scala 709:39] + node _T_3640 = asSInt(_T_3639) @[Rocket.scala 709:43] + node _T_3641 = mux(_T_3638, _T_3640, _T_3613) @[Rocket.scala 709:18] + node _T_3642 = mux(_T_3634, _T_3636, _T_3641) @[Rocket.scala 708:18] + node _T_3643 = mux(_T_3631, asSInt(UInt<1>("h00")), _T_3642) @[Rocket.scala 707:18] + node _T_3645 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) @[Rocket.scala 710:25] + node _T_3647 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[Rocket.scala 710:42] + node _T_3648 = or(_T_3645, _T_3647) @[Rocket.scala 710:35] + node _T_3650 = bits(ex_reg_inst, 30, 25) @[Rocket.scala 710:66] + node _T_3651 = mux(_T_3648, UInt<1>("h00"), _T_3650) @[Rocket.scala 710:20] + node _T_3653 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) @[Rocket.scala 711:24] + node _T_3656 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) @[Rocket.scala 712:24] + node _T_3658 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) @[Rocket.scala 712:41] + node _T_3659 = or(_T_3656, _T_3658) @[Rocket.scala 712:34] + node _T_3660 = bits(ex_reg_inst, 11, 8) @[Rocket.scala 712:57] + node _T_3662 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[Rocket.scala 713:24] + node _T_3663 = bits(ex_reg_inst, 19, 16) @[Rocket.scala 713:39] + node _T_3664 = bits(ex_reg_inst, 24, 21) @[Rocket.scala 713:52] + node _T_3665 = mux(_T_3662, _T_3663, _T_3664) @[Rocket.scala 713:19] + node _T_3666 = mux(_T_3659, _T_3660, _T_3665) @[Rocket.scala 712:19] + node _T_3667 = mux(_T_3653, UInt<1>("h00"), _T_3666) @[Rocket.scala 711:19] + node _T_3669 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) @[Rocket.scala 714:22] + node _T_3670 = bits(ex_reg_inst, 7, 7) @[Rocket.scala 714:37] + node _T_3672 = eq(ex_ctrl.sel_imm, UInt<3>("h04")) @[Rocket.scala 715:22] + node _T_3673 = bits(ex_reg_inst, 20, 20) @[Rocket.scala 715:37] + node _T_3675 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) @[Rocket.scala 716:22] + node _T_3676 = bits(ex_reg_inst, 15, 15) @[Rocket.scala 716:37] + node _T_3678 = mux(_T_3675, _T_3676, UInt<1>("h00")) @[Rocket.scala 716:17] + node _T_3679 = mux(_T_3672, _T_3673, _T_3678) @[Rocket.scala 715:17] + node _T_3680 = mux(_T_3669, _T_3670, _T_3679) @[Rocket.scala 714:17] + node _T_3681 = cat(_T_3651, _T_3667) @[Cat.scala 30:58] + node _T_3682 = cat(_T_3681, _T_3680) @[Cat.scala 30:58] + node _T_3683 = asUInt(_T_3643) @[Cat.scala 30:58] + node _T_3684 = asUInt(_T_3626) @[Cat.scala 30:58] + node _T_3685 = cat(_T_3684, _T_3683) @[Cat.scala 30:58] + node _T_3686 = asUInt(_T_3618) @[Cat.scala 30:58] + node _T_3687 = asUInt(_T_3613) @[Cat.scala 30:58] + node _T_3688 = cat(_T_3687, _T_3686) @[Cat.scala 30:58] + node _T_3689 = cat(_T_3688, _T_3685) @[Cat.scala 30:58] + node _T_3690 = cat(_T_3689, _T_3682) @[Cat.scala 30:58] + node ex_imm = asSInt(_T_3690) @[Rocket.scala 718:53] + node _T_3693 = asSInt(ex_rs_0) @[Rocket.scala 254:24] + node _T_3695 = asSInt(ex_reg_pc) @[Rocket.scala 255:24] + node _T_3696 = eq(UInt<2>("h02"), ex_ctrl.sel_alu1) @[Mux.scala 46:19] + node _T_3697 = mux(_T_3696, _T_3695, asSInt(UInt<1>("h00"))) @[Mux.scala 46:16] + node _T_3698 = eq(UInt<2>("h01"), ex_ctrl.sel_alu1) @[Mux.scala 46:19] + node ex_op1 = mux(_T_3698, _T_3693, _T_3697) @[Mux.scala 46:16] + node _T_3701 = asSInt(ex_rs_1) @[Rocket.scala 257:24] + node _T_3706 = mux(ex_reg_rvc, asSInt(UInt<3>("h02")), asSInt(UInt<4>("h04"))) @[Rocket.scala 259:19] + node _T_3707 = eq(UInt<2>("h01"), ex_ctrl.sel_alu2) @[Mux.scala 46:19] + node _T_3708 = mux(_T_3707, _T_3706, asSInt(UInt<1>("h00"))) @[Mux.scala 46:16] + node _T_3709 = eq(UInt<2>("h03"), ex_ctrl.sel_alu2) @[Mux.scala 46:19] + node _T_3710 = mux(_T_3709, ex_imm, _T_3708) @[Mux.scala 46:16] + node _T_3711 = eq(UInt<2>("h02"), ex_ctrl.sel_alu2) @[Mux.scala 46:19] + node ex_op2 = mux(_T_3711, _T_3701, _T_3710) @[Mux.scala 46:16] + inst alu of ALU @[Rocket.scala 261:19] + alu.io is invalid + alu.clock <= clock + alu.reset <= reset + alu.io.dw <= ex_ctrl.alu_dw @[Rocket.scala 262:13] + alu.io.fn <= ex_ctrl.alu_fn @[Rocket.scala 263:13] + node _T_3712 = asUInt(ex_op2) @[Rocket.scala 264:24] + alu.io.in2 <= _T_3712 @[Rocket.scala 264:14] + node _T_3713 = asUInt(ex_op1) @[Rocket.scala 265:24] + alu.io.in1 <= _T_3713 @[Rocket.scala 265:14] + inst div of MulDiv @[Rocket.scala 268:19] + div.io is invalid + div.clock <= clock + div.reset <= reset + node _T_3714 = and(ex_reg_valid, ex_ctrl.div) @[Rocket.scala 269:36] + div.io.req.valid <= _T_3714 @[Rocket.scala 269:20] + div.io.req.bits.dw <= ex_ctrl.alu_dw @[Rocket.scala 270:22] + div.io.req.bits.fn <= ex_ctrl.alu_fn @[Rocket.scala 271:22] + div.io.req.bits.in1 <= ex_rs_0 @[Rocket.scala 272:23] + div.io.req.bits.in2 <= ex_rs_1 @[Rocket.scala 273:23] + div.io.req.bits.tag <= ex_waddr @[Rocket.scala 274:23] + node _T_3716 = eq(ctrl_killd, UInt<1>("h00")) @[Rocket.scala 276:19] + ex_reg_valid <= _T_3716 @[Rocket.scala 276:16] + node _T_3718 = eq(take_pc, UInt<1>("h00")) @[Rocket.scala 277:20] + node _T_3719 = and(_T_3718, ibuf.io.inst[0].valid) @[Rocket.scala 277:29] + node _T_3720 = and(_T_3719, ibuf.io.inst[0].bits.replay) @[Rocket.scala 277:54] + ex_reg_replay <= _T_3720 @[Rocket.scala 277:17] + node _T_3722 = eq(ctrl_killd, UInt<1>("h00")) @[Rocket.scala 278:18] + node _T_3723 = and(_T_3722, id_xcpt) @[Rocket.scala 278:30] + ex_reg_xcpt <= _T_3723 @[Rocket.scala 278:15] + node _T_3725 = eq(take_pc, UInt<1>("h00")) @[Rocket.scala 279:28] + node _T_3726 = and(_T_3725, ibuf.io.inst[0].valid) @[Rocket.scala 279:37] + node _T_3727 = and(_T_3726, csr.io.interrupt) @[Rocket.scala 279:62] + ex_reg_xcpt_interrupt <= _T_3727 @[Rocket.scala 279:25] + when id_xcpt : @[Rocket.scala 280:18] + ex_cause <= id_cause @[Rocket.scala 280:33] + skip @[Rocket.scala 280:18] + ex_reg_btb_hit <= ibuf.io.inst[0].bits.btb_hit @[Rocket.scala 281:18] + when ibuf.io.inst[0].bits.btb_hit : @[Rocket.scala 282:39] + ex_reg_btb_resp <- ibuf.io.btb_resp @[Rocket.scala 282:57] + skip @[Rocket.scala 282:39] + node _T_3729 = eq(ctrl_killd, UInt<1>("h00")) @[Rocket.scala 284:9] + when _T_3729 : @[Rocket.scala 284:22] + ex_ctrl <- id_ctrl @[Rocket.scala 285:13] + ex_reg_rvc <= ibuf.io.inst[0].bits.rvc @[Rocket.scala 286:16] + ex_ctrl.csr <= id_csr @[Rocket.scala 287:17] + when id_xcpt : @[Rocket.scala 288:20] + ex_ctrl.alu_fn <= UInt<1>("h00") @[Rocket.scala 289:22] + ex_ctrl.alu_dw <= UInt<1>("h01") @[Rocket.scala 290:22] + ex_ctrl.sel_alu1 <= UInt<2>("h02") @[Rocket.scala 291:24] + ex_ctrl.sel_alu2 <= UInt<2>("h00") @[Rocket.scala 292:24] + node _T_3735 = eq(bpu.io.xcpt_if, UInt<1>("h00")) @[Rocket.scala 293:13] + node _T_3737 = eq(ibuf.io.inst[0].bits.pf0, UInt<1>("h00")) @[Rocket.scala 293:32] + node _T_3738 = and(_T_3735, _T_3737) @[Rocket.scala 293:29] + node _T_3739 = and(_T_3738, ibuf.io.inst[0].bits.pf1) @[Rocket.scala 293:58] + when _T_3739 : @[Rocket.scala 293:87] + ex_ctrl.sel_alu2 <= UInt<2>("h01") @[Rocket.scala 294:26] + ex_reg_rvc <= UInt<1>("h01") @[Rocket.scala 295:20] + skip @[Rocket.scala 293:87] + skip @[Rocket.scala 288:20] + node _T_3742 = or(id_ctrl.fence_i, id_csr_flush) @[Rocket.scala 298:42] + node _T_3743 = or(_T_3742, csr.io.singleStep) @[Rocket.scala 298:58] + ex_reg_flush_pipe <= _T_3743 @[Rocket.scala 298:23] + ex_reg_load_use <= id_load_use @[Rocket.scala 299:21] + node _T_3744 = and(id_ctrl.jalr, csr.io.status.debug) @[Rocket.scala 301:24] + when _T_3744 : @[Rocket.scala 301:48] + ex_reg_flush_pipe <= UInt<1>("h01") @[Rocket.scala 302:25] + ex_ctrl.fence_i <= UInt<1>("h01") @[Rocket.scala 303:23] + skip @[Rocket.scala 301:48] + node _T_3747 = or(id_bypass_src_0_0, id_bypass_src_0_1) @[Rocket.scala 307:48] + node _T_3748 = or(_T_3747, id_bypass_src_0_2) @[Rocket.scala 307:48] + node _T_3749 = or(_T_3748, id_bypass_src_0_3) @[Rocket.scala 307:48] + node _T_3754 = mux(id_bypass_src_0_2, UInt<2>("h02"), UInt<2>("h03")) @[Mux.scala 31:69] + node _T_3755 = mux(id_bypass_src_0_1, UInt<1>("h01"), _T_3754) @[Mux.scala 31:69] + node _T_3756 = mux(id_bypass_src_0_0, UInt<1>("h00"), _T_3755) @[Mux.scala 31:69] + ex_reg_rs_bypass[0] <= _T_3749 @[Rocket.scala 309:27] + ex_reg_rs_lsb[0] <= _T_3756 @[Rocket.scala 310:24] + node _T_3758 = eq(_T_3749, UInt<1>("h00")) @[Rocket.scala 311:26] + node _T_3759 = and(id_ctrl.rxs1, _T_3758) @[Rocket.scala 311:23] + when _T_3759 : @[Rocket.scala 311:38] + node _T_3760 = bits(id_rs_0, 1, 0) @[Rocket.scala 312:37] + ex_reg_rs_lsb[0] <= _T_3760 @[Rocket.scala 312:26] + node _T_3761 = shr(id_rs_0, 2) @[Rocket.scala 313:38] + ex_reg_rs_msb[0] <= _T_3761 @[Rocket.scala 313:26] + skip @[Rocket.scala 311:38] + node _T_3762 = or(id_bypass_src_1_0, id_bypass_src_1_1) @[Rocket.scala 307:48] + node _T_3763 = or(_T_3762, id_bypass_src_1_2) @[Rocket.scala 307:48] + node _T_3764 = or(_T_3763, id_bypass_src_1_3) @[Rocket.scala 307:48] + node _T_3769 = mux(id_bypass_src_1_2, UInt<2>("h02"), UInt<2>("h03")) @[Mux.scala 31:69] + node _T_3770 = mux(id_bypass_src_1_1, UInt<1>("h01"), _T_3769) @[Mux.scala 31:69] + node _T_3771 = mux(id_bypass_src_1_0, UInt<1>("h00"), _T_3770) @[Mux.scala 31:69] + ex_reg_rs_bypass[1] <= _T_3764 @[Rocket.scala 309:27] + ex_reg_rs_lsb[1] <= _T_3771 @[Rocket.scala 310:24] + node _T_3773 = eq(_T_3764, UInt<1>("h00")) @[Rocket.scala 311:26] + node _T_3774 = and(id_ctrl.rxs2, _T_3773) @[Rocket.scala 311:23] + when _T_3774 : @[Rocket.scala 311:38] + node _T_3775 = bits(id_rs_1, 1, 0) @[Rocket.scala 312:37] + ex_reg_rs_lsb[1] <= _T_3775 @[Rocket.scala 312:26] + node _T_3776 = shr(id_rs_1, 2) @[Rocket.scala 313:38] + ex_reg_rs_msb[1] <= _T_3776 @[Rocket.scala 313:26] + skip @[Rocket.scala 311:38] + skip @[Rocket.scala 284:22] + node _T_3778 = eq(ctrl_killd, UInt<1>("h00")) @[Rocket.scala 317:9] + node _T_3779 = or(_T_3778, csr.io.interrupt) @[Rocket.scala 317:21] + node _T_3780 = or(_T_3779, ibuf.io.inst[0].bits.replay) @[Rocket.scala 317:41] + when _T_3780 : @[Rocket.scala 317:73] + ex_reg_inst <= ibuf.io.inst[0].bits.inst.bits @[Rocket.scala 318:17] + ex_reg_pc <= ibuf.io.pc @[Rocket.scala 319:15] + skip @[Rocket.scala 317:73] + node _T_3781 = or(ex_reg_valid, ex_reg_replay) @[Rocket.scala 323:34] + node ex_pc_valid = or(_T_3781, ex_reg_xcpt_interrupt) @[Rocket.scala 323:51] + node _T_3783 = eq(io.dmem.resp.valid, UInt<1>("h00")) @[Rocket.scala 324:39] + node wb_dcache_miss = and(wb_ctrl.mem, _T_3783) @[Rocket.scala 324:36] + node _T_3785 = eq(io.dmem.req.ready, UInt<1>("h00")) @[Rocket.scala 325:45] + node _T_3786 = and(ex_ctrl.mem, _T_3785) @[Rocket.scala 325:42] + node _T_3788 = eq(div.io.req.ready, UInt<1>("h00")) @[Rocket.scala 326:45] + node _T_3789 = and(ex_ctrl.div, _T_3788) @[Rocket.scala 326:42] + node replay_ex_structural = or(_T_3786, _T_3789) @[Rocket.scala 325:64] + node replay_ex_load_use = and(wb_dcache_miss, ex_reg_load_use) @[Rocket.scala 327:43] + node _T_3790 = or(replay_ex_structural, replay_ex_load_use) @[Rocket.scala 328:75] + node _T_3791 = and(ex_reg_valid, _T_3790) @[Rocket.scala 328:50] + node replay_ex = or(ex_reg_replay, _T_3791) @[Rocket.scala 328:33] + node _T_3792 = or(take_pc_mem_wb, replay_ex) @[Rocket.scala 329:35] + node _T_3794 = eq(ex_reg_valid, UInt<1>("h00")) @[Rocket.scala 329:51] + node ctrl_killx = or(_T_3792, _T_3794) @[Rocket.scala 329:48] + node _T_3796 = eq(ex_ctrl.mem_cmd, UInt<3>("h07")) @[Rocket.scala 331:40] + wire _T_3803 : UInt<3>[4] @[Rocket.scala 331:56] + _T_3803 is invalid @[Rocket.scala 331:56] + _T_3803[0] <= UInt<1>("h00") @[Rocket.scala 331:56] + _T_3803[1] <= UInt<3>("h04") @[Rocket.scala 331:56] + _T_3803[2] <= UInt<1>("h01") @[Rocket.scala 331:56] + _T_3803[3] <= UInt<3>("h05") @[Rocket.scala 331:56] + node _T_3810 = eq(_T_3803[0], ex_ctrl.mem_type) @[Rocket.scala 331:91] + node _T_3811 = eq(_T_3803[1], ex_ctrl.mem_type) @[Rocket.scala 331:91] + node _T_3812 = eq(_T_3803[2], ex_ctrl.mem_type) @[Rocket.scala 331:91] + node _T_3813 = eq(_T_3803[3], ex_ctrl.mem_type) @[Rocket.scala 331:91] + node _T_3815 = or(UInt<1>("h00"), _T_3810) @[Rocket.scala 331:91] + node _T_3816 = or(_T_3815, _T_3811) @[Rocket.scala 331:91] + node _T_3817 = or(_T_3816, _T_3812) @[Rocket.scala 331:91] + node _T_3818 = or(_T_3817, _T_3813) @[Rocket.scala 331:91] + node ex_slow_bypass = or(_T_3796, _T_3818) @[Rocket.scala 331:50] + node ex_xcpt = or(ex_reg_xcpt_interrupt, ex_reg_xcpt) @[Rocket.scala 334:28] + node _T_3819 = or(mem_reg_valid, mem_reg_replay) @[Rocket.scala 337:36] + node mem_pc_valid = or(_T_3819, mem_reg_xcpt_interrupt) @[Rocket.scala 337:54] + node mem_br_taken = bits(mem_reg_wdata, 0, 0) @[Rocket.scala 338:35] + node _T_3820 = asSInt(mem_reg_pc) @[Rocket.scala 339:34] + node _T_3821 = and(mem_ctrl.branch, mem_br_taken) @[Rocket.scala 340:25] + node _T_3824 = eq(UInt<3>("h01"), UInt<3>("h05")) @[Rocket.scala 704:24] + node _T_3826 = bits(mem_reg_inst, 31, 31) @[Rocket.scala 704:48] + node _T_3827 = asSInt(_T_3826) @[Rocket.scala 704:53] + node _T_3828 = mux(_T_3824, asSInt(UInt<1>("h00")), _T_3827) @[Rocket.scala 704:19] + node _T_3830 = eq(UInt<3>("h01"), UInt<3>("h02")) @[Rocket.scala 705:26] + node _T_3831 = bits(mem_reg_inst, 30, 20) @[Rocket.scala 705:41] + node _T_3832 = asSInt(_T_3831) @[Rocket.scala 705:49] + node _T_3833 = mux(_T_3830, _T_3832, _T_3828) @[Rocket.scala 705:21] + node _T_3835 = neq(UInt<3>("h01"), UInt<3>("h02")) @[Rocket.scala 706:26] + node _T_3837 = neq(UInt<3>("h01"), UInt<3>("h03")) @[Rocket.scala 706:43] + node _T_3838 = and(_T_3835, _T_3837) @[Rocket.scala 706:36] + node _T_3839 = bits(mem_reg_inst, 19, 12) @[Rocket.scala 706:65] + node _T_3840 = asSInt(_T_3839) @[Rocket.scala 706:73] + node _T_3841 = mux(_T_3838, _T_3828, _T_3840) @[Rocket.scala 706:21] + node _T_3843 = eq(UInt<3>("h01"), UInt<3>("h02")) @[Rocket.scala 707:23] + node _T_3845 = eq(UInt<3>("h01"), UInt<3>("h05")) @[Rocket.scala 707:40] + node _T_3846 = or(_T_3843, _T_3845) @[Rocket.scala 707:33] + node _T_3849 = eq(UInt<3>("h01"), UInt<3>("h03")) @[Rocket.scala 708:23] + node _T_3850 = bits(mem_reg_inst, 20, 20) @[Rocket.scala 708:39] + node _T_3851 = asSInt(_T_3850) @[Rocket.scala 708:44] + node _T_3853 = eq(UInt<3>("h01"), UInt<3>("h01")) @[Rocket.scala 709:23] + node _T_3854 = bits(mem_reg_inst, 7, 7) @[Rocket.scala 709:39] + node _T_3855 = asSInt(_T_3854) @[Rocket.scala 709:43] + node _T_3856 = mux(_T_3853, _T_3855, _T_3828) @[Rocket.scala 709:18] + node _T_3857 = mux(_T_3849, _T_3851, _T_3856) @[Rocket.scala 708:18] + node _T_3858 = mux(_T_3846, asSInt(UInt<1>("h00")), _T_3857) @[Rocket.scala 707:18] + node _T_3860 = eq(UInt<3>("h01"), UInt<3>("h02")) @[Rocket.scala 710:25] + node _T_3862 = eq(UInt<3>("h01"), UInt<3>("h05")) @[Rocket.scala 710:42] + node _T_3863 = or(_T_3860, _T_3862) @[Rocket.scala 710:35] + node _T_3865 = bits(mem_reg_inst, 30, 25) @[Rocket.scala 710:66] + node _T_3866 = mux(_T_3863, UInt<1>("h00"), _T_3865) @[Rocket.scala 710:20] + node _T_3868 = eq(UInt<3>("h01"), UInt<3>("h02")) @[Rocket.scala 711:24] + node _T_3871 = eq(UInt<3>("h01"), UInt<3>("h00")) @[Rocket.scala 712:24] + node _T_3873 = eq(UInt<3>("h01"), UInt<3>("h01")) @[Rocket.scala 712:41] + node _T_3874 = or(_T_3871, _T_3873) @[Rocket.scala 712:34] + node _T_3875 = bits(mem_reg_inst, 11, 8) @[Rocket.scala 712:57] + node _T_3877 = eq(UInt<3>("h01"), UInt<3>("h05")) @[Rocket.scala 713:24] + node _T_3878 = bits(mem_reg_inst, 19, 16) @[Rocket.scala 713:39] + node _T_3879 = bits(mem_reg_inst, 24, 21) @[Rocket.scala 713:52] + node _T_3880 = mux(_T_3877, _T_3878, _T_3879) @[Rocket.scala 713:19] + node _T_3881 = mux(_T_3874, _T_3875, _T_3880) @[Rocket.scala 712:19] + node _T_3882 = mux(_T_3868, UInt<1>("h00"), _T_3881) @[Rocket.scala 711:19] + node _T_3884 = eq(UInt<3>("h01"), UInt<3>("h00")) @[Rocket.scala 714:22] + node _T_3885 = bits(mem_reg_inst, 7, 7) @[Rocket.scala 714:37] + node _T_3887 = eq(UInt<3>("h01"), UInt<3>("h04")) @[Rocket.scala 715:22] + node _T_3888 = bits(mem_reg_inst, 20, 20) @[Rocket.scala 715:37] + node _T_3890 = eq(UInt<3>("h01"), UInt<3>("h05")) @[Rocket.scala 716:22] + node _T_3891 = bits(mem_reg_inst, 15, 15) @[Rocket.scala 716:37] + node _T_3893 = mux(_T_3890, _T_3891, UInt<1>("h00")) @[Rocket.scala 716:17] + node _T_3894 = mux(_T_3887, _T_3888, _T_3893) @[Rocket.scala 715:17] + node _T_3895 = mux(_T_3884, _T_3885, _T_3894) @[Rocket.scala 714:17] + node _T_3896 = cat(_T_3866, _T_3882) @[Cat.scala 30:58] + node _T_3897 = cat(_T_3896, _T_3895) @[Cat.scala 30:58] + node _T_3898 = asUInt(_T_3858) @[Cat.scala 30:58] + node _T_3899 = asUInt(_T_3841) @[Cat.scala 30:58] + node _T_3900 = cat(_T_3899, _T_3898) @[Cat.scala 30:58] + node _T_3901 = asUInt(_T_3833) @[Cat.scala 30:58] + node _T_3902 = asUInt(_T_3828) @[Cat.scala 30:58] + node _T_3903 = cat(_T_3902, _T_3901) @[Cat.scala 30:58] + node _T_3904 = cat(_T_3903, _T_3900) @[Cat.scala 30:58] + node _T_3905 = cat(_T_3904, _T_3897) @[Cat.scala 30:58] + node _T_3906 = asSInt(_T_3905) @[Rocket.scala 718:53] + node _T_3908 = and(UInt<1>("h01"), mem_ctrl.jal) @[Rocket.scala 341:24] + node _T_3911 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 704:24] + node _T_3913 = bits(mem_reg_inst, 31, 31) @[Rocket.scala 704:48] + node _T_3914 = asSInt(_T_3913) @[Rocket.scala 704:53] + node _T_3915 = mux(_T_3911, asSInt(UInt<1>("h00")), _T_3914) @[Rocket.scala 704:19] + node _T_3917 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 705:26] + node _T_3918 = bits(mem_reg_inst, 30, 20) @[Rocket.scala 705:41] + node _T_3919 = asSInt(_T_3918) @[Rocket.scala 705:49] + node _T_3920 = mux(_T_3917, _T_3919, _T_3915) @[Rocket.scala 705:21] + node _T_3922 = neq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 706:26] + node _T_3924 = neq(UInt<3>("h03"), UInt<3>("h03")) @[Rocket.scala 706:43] + node _T_3925 = and(_T_3922, _T_3924) @[Rocket.scala 706:36] + node _T_3926 = bits(mem_reg_inst, 19, 12) @[Rocket.scala 706:65] + node _T_3927 = asSInt(_T_3926) @[Rocket.scala 706:73] + node _T_3928 = mux(_T_3925, _T_3915, _T_3927) @[Rocket.scala 706:21] + node _T_3930 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 707:23] + node _T_3932 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 707:40] + node _T_3933 = or(_T_3930, _T_3932) @[Rocket.scala 707:33] + node _T_3936 = eq(UInt<3>("h03"), UInt<3>("h03")) @[Rocket.scala 708:23] + node _T_3937 = bits(mem_reg_inst, 20, 20) @[Rocket.scala 708:39] + node _T_3938 = asSInt(_T_3937) @[Rocket.scala 708:44] + node _T_3940 = eq(UInt<3>("h03"), UInt<3>("h01")) @[Rocket.scala 709:23] + node _T_3941 = bits(mem_reg_inst, 7, 7) @[Rocket.scala 709:39] + node _T_3942 = asSInt(_T_3941) @[Rocket.scala 709:43] + node _T_3943 = mux(_T_3940, _T_3942, _T_3915) @[Rocket.scala 709:18] + node _T_3944 = mux(_T_3936, _T_3938, _T_3943) @[Rocket.scala 708:18] + node _T_3945 = mux(_T_3933, asSInt(UInt<1>("h00")), _T_3944) @[Rocket.scala 707:18] + node _T_3947 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 710:25] + node _T_3949 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 710:42] + node _T_3950 = or(_T_3947, _T_3949) @[Rocket.scala 710:35] + node _T_3952 = bits(mem_reg_inst, 30, 25) @[Rocket.scala 710:66] + node _T_3953 = mux(_T_3950, UInt<1>("h00"), _T_3952) @[Rocket.scala 710:20] + node _T_3955 = eq(UInt<3>("h03"), UInt<3>("h02")) @[Rocket.scala 711:24] + node _T_3958 = eq(UInt<3>("h03"), UInt<3>("h00")) @[Rocket.scala 712:24] + node _T_3960 = eq(UInt<3>("h03"), UInt<3>("h01")) @[Rocket.scala 712:41] + node _T_3961 = or(_T_3958, _T_3960) @[Rocket.scala 712:34] + node _T_3962 = bits(mem_reg_inst, 11, 8) @[Rocket.scala 712:57] + node _T_3964 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 713:24] + node _T_3965 = bits(mem_reg_inst, 19, 16) @[Rocket.scala 713:39] + node _T_3966 = bits(mem_reg_inst, 24, 21) @[Rocket.scala 713:52] + node _T_3967 = mux(_T_3964, _T_3965, _T_3966) @[Rocket.scala 713:19] + node _T_3968 = mux(_T_3961, _T_3962, _T_3967) @[Rocket.scala 712:19] + node _T_3969 = mux(_T_3955, UInt<1>("h00"), _T_3968) @[Rocket.scala 711:19] + node _T_3971 = eq(UInt<3>("h03"), UInt<3>("h00")) @[Rocket.scala 714:22] + node _T_3972 = bits(mem_reg_inst, 7, 7) @[Rocket.scala 714:37] + node _T_3974 = eq(UInt<3>("h03"), UInt<3>("h04")) @[Rocket.scala 715:22] + node _T_3975 = bits(mem_reg_inst, 20, 20) @[Rocket.scala 715:37] + node _T_3977 = eq(UInt<3>("h03"), UInt<3>("h05")) @[Rocket.scala 716:22] + node _T_3978 = bits(mem_reg_inst, 15, 15) @[Rocket.scala 716:37] + node _T_3980 = mux(_T_3977, _T_3978, UInt<1>("h00")) @[Rocket.scala 716:17] + node _T_3981 = mux(_T_3974, _T_3975, _T_3980) @[Rocket.scala 715:17] + node _T_3982 = mux(_T_3971, _T_3972, _T_3981) @[Rocket.scala 714:17] + node _T_3983 = cat(_T_3953, _T_3969) @[Cat.scala 30:58] + node _T_3984 = cat(_T_3983, _T_3982) @[Cat.scala 30:58] + node _T_3985 = asUInt(_T_3945) @[Cat.scala 30:58] + node _T_3986 = asUInt(_T_3928) @[Cat.scala 30:58] + node _T_3987 = cat(_T_3986, _T_3985) @[Cat.scala 30:58] + node _T_3988 = asUInt(_T_3920) @[Cat.scala 30:58] + node _T_3989 = asUInt(_T_3915) @[Cat.scala 30:58] + node _T_3990 = cat(_T_3989, _T_3988) @[Cat.scala 30:58] + node _T_3991 = cat(_T_3990, _T_3987) @[Cat.scala 30:58] + node _T_3992 = cat(_T_3991, _T_3984) @[Cat.scala 30:58] + node _T_3993 = asSInt(_T_3992) @[Rocket.scala 718:53] + node _T_3996 = mux(mem_reg_rvc, asSInt(UInt<3>("h02")), asSInt(UInt<4>("h04"))) @[Rocket.scala 342:8] + node _T_3997 = mux(_T_3908, _T_3993, _T_3996) @[Rocket.scala 341:8] + node _T_3998 = mux(_T_3821, _T_3906, _T_3997) @[Rocket.scala 340:8] + node _T_3999 = add(_T_3820, _T_3998) @[Rocket.scala 339:41] + node _T_4000 = tail(_T_3999, 1) @[Rocket.scala 339:41] + node mem_br_target = asSInt(_T_4000) @[Rocket.scala 339:41] + node _T_4001 = shr(mem_reg_wdata, 38) @[Rocket.scala 653:16] + node _T_4002 = bits(mem_reg_wdata, 39, 38) @[Rocket.scala 654:15] + node _T_4003 = asSInt(_T_4002) @[Rocket.scala 654:39] + node _T_4005 = eq(_T_4001, UInt<1>("h00")) @[Rocket.scala 656:13] + node _T_4007 = eq(_T_4001, UInt<1>("h01")) @[Rocket.scala 656:30] + node _T_4008 = or(_T_4005, _T_4007) @[Rocket.scala 656:25] + node _T_4010 = neq(_T_4003, asSInt(UInt<1>("h00"))) @[Rocket.scala 656:45] + node _T_4011 = asSInt(_T_4001) @[Rocket.scala 657:13] + node _T_4013 = eq(_T_4011, asSInt(UInt<1>("h01"))) @[Rocket.scala 657:20] + node _T_4014 = asSInt(_T_4001) @[Rocket.scala 657:38] + node _T_4016 = eq(_T_4014, asSInt(UInt<2>("h02"))) @[Rocket.scala 657:45] + node _T_4017 = or(_T_4013, _T_4016) @[Rocket.scala 657:33] + node _T_4019 = eq(_T_4003, asSInt(UInt<1>("h01"))) @[Rocket.scala 657:61] + node _T_4020 = bits(_T_4003, 0, 0) @[Rocket.scala 657:76] + node _T_4021 = mux(_T_4017, _T_4019, _T_4020) @[Rocket.scala 657:10] + node _T_4022 = mux(_T_4008, _T_4010, _T_4021) @[Rocket.scala 656:10] + node _T_4023 = bits(mem_reg_wdata, 38, 0) @[Rocket.scala 658:16] + node _T_4024 = cat(_T_4022, _T_4023) @[Cat.scala 30:58] + node _T_4025 = asSInt(_T_4024) @[Rocket.scala 343:88] + node _T_4026 = mux(mem_ctrl.jalr, _T_4025, mem_br_target) @[Rocket.scala 343:21] + node _T_4028 = and(_T_4026, asSInt(UInt<2>("h02"))) @[Rocket.scala 343:111] + node _T_4029 = asSInt(_T_4028) @[Rocket.scala 343:111] + node mem_npc = asUInt(_T_4029) @[Rocket.scala 343:123] + node _T_4030 = neq(mem_npc, ex_reg_pc) @[Rocket.scala 344:48] + node _T_4031 = neq(mem_npc, ibuf.io.pc) @[Rocket.scala 344:98] + node _T_4033 = mux(ibuf.io.inst[0].valid, _T_4031, UInt<1>("h01")) @[Rocket.scala 344:66] + node mem_misprediction = mux(ex_pc_valid, _T_4030, _T_4033) @[Rocket.scala 344:26] + node _T_4034 = bits(csr.io.status.isa, 2, 2) @[Rocket.scala 345:46] + node _T_4036 = eq(_T_4034, UInt<1>("h00")) @[Rocket.scala 345:28] + node _T_4037 = bits(mem_npc, 1, 1) @[Rocket.scala 345:66] + node mem_npc_misaligned = and(_T_4036, _T_4037) @[Rocket.scala 345:56] + node _T_4039 = eq(mem_reg_xcpt, UInt<1>("h00")) @[Rocket.scala 346:27] + node _T_4040 = xor(mem_ctrl.jalr, mem_npc_misaligned) @[Rocket.scala 346:59] + node _T_4041 = and(_T_4039, _T_4040) @[Rocket.scala 346:41] + node _T_4042 = asSInt(mem_reg_wdata) @[Rocket.scala 346:111] + node _T_4043 = mux(_T_4041, mem_br_target, _T_4042) @[Rocket.scala 346:26] + node mem_int_wdata = asUInt(_T_4043) @[Rocket.scala 346:119] + node _T_4044 = or(mem_ctrl.branch, mem_ctrl.jalr) @[Rocket.scala 347:33] + node mem_cfi = or(_T_4044, mem_ctrl.jal) @[Rocket.scala 347:50] + node _T_4045 = and(mem_ctrl.branch, mem_br_taken) @[Rocket.scala 348:40] + node _T_4046 = or(_T_4045, mem_ctrl.jalr) @[Rocket.scala 348:57] + node _T_4048 = and(UInt<1>("h01"), mem_ctrl.jal) @[Rocket.scala 348:93] + node mem_cfi_taken = or(_T_4046, _T_4048) @[Rocket.scala 348:74] + node _T_4049 = and(mem_reg_btb_hit, mem_ctrl.branch) @[Rocket.scala 349:53] + node _T_4050 = neq(mem_br_taken, mem_reg_btb_resp.taken) @[Rocket.scala 349:88] + node mem_direction_misprediction = and(_T_4049, _T_4050) @[Rocket.scala 349:72] + node _T_4051 = or(mem_misprediction, mem_reg_flush_pipe) @[Rocket.scala 351:54] + node _T_4052 = and(mem_reg_valid, _T_4051) @[Rocket.scala 351:32] + take_pc_mem <= _T_4052 @[Rocket.scala 351:15] + node _T_4054 = eq(ctrl_killx, UInt<1>("h00")) @[Rocket.scala 353:20] + mem_reg_valid <= _T_4054 @[Rocket.scala 353:17] + node _T_4056 = eq(take_pc_mem_wb, UInt<1>("h00")) @[Rocket.scala 354:21] + node _T_4057 = and(_T_4056, replay_ex) @[Rocket.scala 354:37] + mem_reg_replay <= _T_4057 @[Rocket.scala 354:18] + node _T_4059 = eq(ctrl_killx, UInt<1>("h00")) @[Rocket.scala 355:19] + node _T_4060 = and(_T_4059, ex_xcpt) @[Rocket.scala 355:31] + mem_reg_xcpt <= _T_4060 @[Rocket.scala 355:16] + node _T_4062 = eq(take_pc_mem_wb, UInt<1>("h00")) @[Rocket.scala 356:29] + node _T_4063 = and(_T_4062, ex_reg_xcpt_interrupt) @[Rocket.scala 356:45] + mem_reg_xcpt_interrupt <= _T_4063 @[Rocket.scala 356:26] + when ex_xcpt : @[Rocket.scala 357:18] + mem_reg_cause <= ex_cause @[Rocket.scala 357:34] + skip @[Rocket.scala 357:18] + when ex_pc_valid : @[Rocket.scala 359:22] + mem_ctrl <- ex_ctrl @[Rocket.scala 360:14] + mem_reg_rvc <= ex_reg_rvc @[Rocket.scala 361:17] + node _T_4065 = eq(ex_ctrl.mem_cmd, UInt<1>("h00")) @[Consts.scala 35:31] + node _T_4067 = eq(ex_ctrl.mem_cmd, UInt<3>("h06")) @[Consts.scala 35:48] + node _T_4068 = or(_T_4065, _T_4067) @[Consts.scala 35:41] + node _T_4070 = eq(ex_ctrl.mem_cmd, UInt<3>("h07")) @[Consts.scala 35:65] + node _T_4071 = or(_T_4068, _T_4070) @[Consts.scala 35:58] + node _T_4072 = bits(ex_ctrl.mem_cmd, 3, 3) @[Consts.scala 33:29] + node _T_4074 = eq(ex_ctrl.mem_cmd, UInt<3>("h04")) @[Consts.scala 33:40] + node _T_4075 = or(_T_4072, _T_4074) @[Consts.scala 33:33] + node _T_4076 = or(_T_4071, _T_4075) @[Consts.scala 35:75] + node _T_4077 = and(ex_ctrl.mem, _T_4076) @[Rocket.scala 362:33] + mem_reg_load <= _T_4077 @[Rocket.scala 362:18] + node _T_4079 = eq(ex_ctrl.mem_cmd, UInt<1>("h01")) @[Consts.scala 36:32] + node _T_4081 = eq(ex_ctrl.mem_cmd, UInt<3>("h07")) @[Consts.scala 36:49] + node _T_4082 = or(_T_4079, _T_4081) @[Consts.scala 36:42] + node _T_4083 = bits(ex_ctrl.mem_cmd, 3, 3) @[Consts.scala 33:29] + node _T_4085 = eq(ex_ctrl.mem_cmd, UInt<3>("h04")) @[Consts.scala 33:40] + node _T_4086 = or(_T_4083, _T_4085) @[Consts.scala 33:33] + node _T_4087 = or(_T_4082, _T_4086) @[Consts.scala 36:59] + node _T_4088 = and(ex_ctrl.mem, _T_4087) @[Rocket.scala 363:34] + mem_reg_store <= _T_4088 @[Rocket.scala 363:19] + mem_reg_btb_hit <= ex_reg_btb_hit @[Rocket.scala 364:21] + when ex_reg_btb_hit : @[Rocket.scala 365:27] + mem_reg_btb_resp <- ex_reg_btb_resp @[Rocket.scala 365:46] + skip @[Rocket.scala 365:27] + mem_reg_flush_pipe <= ex_reg_flush_pipe @[Rocket.scala 366:24] + mem_reg_slow_bypass <= ex_slow_bypass @[Rocket.scala 367:25] + mem_reg_inst <= ex_reg_inst @[Rocket.scala 369:18] + mem_reg_pc <= ex_reg_pc @[Rocket.scala 370:16] + mem_reg_wdata <= alu.io.out @[Rocket.scala 371:19] + node _T_4089 = or(ex_ctrl.mem, ex_ctrl.rocc) @[Rocket.scala 372:40] + node _T_4090 = and(ex_ctrl.rxs2, _T_4089) @[Rocket.scala 372:24] + when _T_4090 : @[Rocket.scala 372:58] + mem_reg_rs2 <= ex_rs_1 @[Rocket.scala 373:19] + skip @[Rocket.scala 372:58] + skip @[Rocket.scala 359:22] + node _T_4091 = and(mem_reg_load, bpu.io.xcpt_ld) @[Rocket.scala 377:38] + node _T_4092 = and(mem_reg_store, bpu.io.xcpt_st) @[Rocket.scala 377:75] + node mem_breakpoint = or(_T_4091, _T_4092) @[Rocket.scala 377:57] + node _T_4093 = and(mem_reg_load, bpu.io.debug_ld) @[Rocket.scala 378:44] + node _T_4094 = and(mem_reg_store, bpu.io.debug_st) @[Rocket.scala 378:82] + node mem_debug_breakpoint = or(_T_4093, _T_4094) @[Rocket.scala 378:64] + node _T_4126 = and(mem_ctrl.mem, io.dmem.xcpt.ma.st) @[Rocket.scala 383:19] + node _T_4128 = and(mem_ctrl.mem, io.dmem.xcpt.ma.ld) @[Rocket.scala 384:19] + node _T_4130 = and(mem_ctrl.mem, io.dmem.xcpt.pf.st) @[Rocket.scala 385:19] + node _T_4132 = and(mem_ctrl.mem, io.dmem.xcpt.pf.ld) @[Rocket.scala 386:19] + node _T_4134 = or(mem_debug_breakpoint, mem_breakpoint) @[Rocket.scala 645:26] + node _T_4135 = or(_T_4134, mem_npc_misaligned) @[Rocket.scala 645:26] + node _T_4136 = or(_T_4135, _T_4126) @[Rocket.scala 645:26] + node _T_4137 = or(_T_4136, _T_4128) @[Rocket.scala 645:26] + node _T_4138 = or(_T_4137, _T_4130) @[Rocket.scala 645:26] + node mem_new_xcpt = or(_T_4138, _T_4132) @[Rocket.scala 645:26] + node _T_4139 = mux(_T_4130, UInt<3>("h07"), UInt<3>("h05")) @[Mux.scala 31:69] + node _T_4140 = mux(_T_4128, UInt<3>("h04"), _T_4139) @[Mux.scala 31:69] + node _T_4141 = mux(_T_4126, UInt<3>("h06"), _T_4140) @[Mux.scala 31:69] + node _T_4142 = mux(mem_npc_misaligned, UInt<1>("h00"), _T_4141) @[Mux.scala 31:69] + node _T_4143 = mux(mem_breakpoint, UInt<2>("h03"), _T_4142) @[Mux.scala 31:69] + node mem_new_cause = mux(mem_debug_breakpoint, UInt<4>("h0d"), _T_4143) @[Mux.scala 31:69] + node _T_4144 = or(mem_reg_xcpt_interrupt, mem_reg_xcpt) @[Rocket.scala 389:29] + node _T_4145 = and(mem_reg_valid, mem_new_xcpt) @[Rocket.scala 390:20] + node mem_xcpt = or(_T_4144, _T_4145) @[Rocket.scala 645:26] + node mem_cause = mux(_T_4144, mem_reg_cause, mem_new_cause) @[Mux.scala 31:69] + node _T_4146 = and(mem_reg_valid, mem_ctrl.wxd) @[Rocket.scala 392:39] + node dcache_kill_mem = and(_T_4146, io.dmem.replay_next) @[Rocket.scala 392:55] + node _T_4147 = and(mem_reg_valid, mem_ctrl.fp) @[Rocket.scala 393:36] + node fpu_kill_mem = and(_T_4147, io.fpu.nack_mem) @[Rocket.scala 393:51] + node _T_4148 = or(dcache_kill_mem, mem_reg_replay) @[Rocket.scala 394:37] + node replay_mem = or(_T_4148, fpu_kill_mem) @[Rocket.scala 394:55] + node _T_4149 = or(dcache_kill_mem, take_pc_wb) @[Rocket.scala 395:38] + node _T_4150 = or(_T_4149, mem_reg_xcpt) @[Rocket.scala 395:52] + node _T_4152 = eq(mem_reg_valid, UInt<1>("h00")) @[Rocket.scala 395:71] + node killm_common = or(_T_4150, _T_4152) @[Rocket.scala 395:68] + node _T_4153 = and(div.io.req.ready, div.io.req.valid) @[Decoupled.scala 30:37] + reg _T_4154 : UInt<1>, clock @[Rocket.scala 396:37] + _T_4154 <= _T_4153 @[Rocket.scala 396:37] + node _T_4155 = and(killm_common, _T_4154) @[Rocket.scala 396:31] + div.io.kill <= _T_4155 @[Rocket.scala 396:15] + node _T_4156 = or(killm_common, mem_xcpt) @[Rocket.scala 397:33] + node ctrl_killm = or(_T_4156, fpu_kill_mem) @[Rocket.scala 397:45] + node _T_4158 = eq(ctrl_killm, UInt<1>("h00")) @[Rocket.scala 400:19] + wb_reg_valid <= _T_4158 @[Rocket.scala 400:16] + node _T_4160 = eq(take_pc_wb, UInt<1>("h00")) @[Rocket.scala 401:34] + node _T_4161 = and(replay_mem, _T_4160) @[Rocket.scala 401:31] + wb_reg_replay <= _T_4161 @[Rocket.scala 401:17] + node _T_4163 = eq(take_pc_wb, UInt<1>("h00")) @[Rocket.scala 402:30] + node _T_4164 = and(mem_xcpt, _T_4163) @[Rocket.scala 402:27] + wb_reg_xcpt <= _T_4164 @[Rocket.scala 402:15] + when mem_xcpt : @[Rocket.scala 403:19] + wb_reg_cause <= mem_cause @[Rocket.scala 403:34] + skip @[Rocket.scala 403:19] + when mem_pc_valid : @[Rocket.scala 404:23] + wb_ctrl <- mem_ctrl @[Rocket.scala 405:13] + node _T_4166 = eq(mem_reg_xcpt, UInt<1>("h00")) @[Rocket.scala 406:25] + node _T_4167 = and(_T_4166, mem_ctrl.fp) @[Rocket.scala 406:39] + node _T_4168 = and(_T_4167, mem_ctrl.wxd) @[Rocket.scala 406:54] + node _T_4169 = mux(_T_4168, io.fpu.toint_data, mem_int_wdata) @[Rocket.scala 406:24] + wb_reg_wdata <= _T_4169 @[Rocket.scala 406:18] + when mem_ctrl.rocc : @[Rocket.scala 407:26] + wb_reg_rs2 <= mem_reg_rs2 @[Rocket.scala 408:18] + skip @[Rocket.scala 407:26] + wb_reg_inst <= mem_reg_inst @[Rocket.scala 410:17] + wb_reg_pc <= mem_reg_pc @[Rocket.scala 411:15] + skip @[Rocket.scala 404:23] + node wb_wxd = and(wb_reg_valid, wb_ctrl.wxd) @[Rocket.scala 414:29] + node _T_4170 = or(wb_ctrl.div, wb_dcache_miss) @[Rocket.scala 415:35] + node wb_set_sboard = or(_T_4170, wb_ctrl.rocc) @[Rocket.scala 415:53] + node replay_wb_common = or(io.dmem.s2_nack, wb_reg_replay) @[Rocket.scala 416:42] + node _T_4171 = and(wb_reg_valid, wb_ctrl.rocc) @[Rocket.scala 417:37] + node _T_4173 = eq(io.rocc.cmd.ready, UInt<1>("h00")) @[Rocket.scala 417:56] + node replay_wb_rocc = and(_T_4171, _T_4173) @[Rocket.scala 417:53] + node replay_wb = or(replay_wb_common, replay_wb_rocc) @[Rocket.scala 418:36] + node _T_4174 = or(replay_wb, wb_reg_xcpt) @[Rocket.scala 420:27] + node _T_4175 = or(_T_4174, csr.io.eret) @[Rocket.scala 420:38] + take_pc_wb <= _T_4175 @[Rocket.scala 420:14] + node _T_4176 = bits(io.dmem.resp.bits.tag, 0, 0) @[Rocket.scala 423:45] + node _T_4177 = bits(_T_4176, 0, 0) @[Rocket.scala 423:49] + node dmem_resp_xpu = eq(_T_4177, UInt<1>("h00")) @[Rocket.scala 423:23] + node _T_4179 = bits(io.dmem.resp.bits.tag, 0, 0) @[Rocket.scala 424:45] + node dmem_resp_fpu = bits(_T_4179, 0, 0) @[Rocket.scala 424:49] + node dmem_resp_waddr = bits(io.dmem.resp.bits.tag, 5, 1) @[Rocket.scala 425:46] + node dmem_resp_valid = and(io.dmem.resp.valid, io.dmem.resp.bits.has_data) @[Rocket.scala 426:44] + node dmem_resp_replay = and(dmem_resp_valid, io.dmem.resp.bits.replay) @[Rocket.scala 427:42] + node _T_4181 = eq(wb_wxd, UInt<1>("h00")) @[Rocket.scala 429:24] + div.io.resp.ready <= _T_4181 @[Rocket.scala 429:21] + wire ll_wdata : UInt + ll_wdata is invalid + ll_wdata <= div.io.resp.bits.data + wire ll_waddr : UInt + ll_waddr is invalid + ll_waddr <= div.io.resp.bits.tag + node _T_4182 = and(div.io.resp.ready, div.io.resp.valid) @[Decoupled.scala 30:37] + wire ll_wen : UInt<1> + ll_wen is invalid + ll_wen <= _T_4182 + node _T_4183 = and(dmem_resp_replay, dmem_resp_xpu) @[Rocket.scala 442:26] + when _T_4183 : @[Rocket.scala 442:44] + div.io.resp.ready <= UInt<1>("h00") @[Rocket.scala 443:23] + ll_waddr <= dmem_resp_waddr @[Rocket.scala 446:14] + ll_wen <= UInt<1>("h01") @[Rocket.scala 447:12] + skip @[Rocket.scala 442:44] + node _T_4187 = eq(replay_wb, UInt<1>("h00")) @[Rocket.scala 450:34] + node _T_4188 = and(wb_reg_valid, _T_4187) @[Rocket.scala 450:31] + node _T_4190 = eq(wb_reg_xcpt, UInt<1>("h00")) @[Rocket.scala 450:48] + node wb_valid = and(_T_4188, _T_4190) @[Rocket.scala 450:45] + node wb_wen = and(wb_valid, wb_ctrl.wxd) @[Rocket.scala 451:25] + node rf_wen = or(wb_wen, ll_wen) @[Rocket.scala 452:23] + node rf_waddr = mux(ll_wen, ll_waddr, wb_waddr) @[Rocket.scala 453:21] + node _T_4191 = and(dmem_resp_valid, dmem_resp_xpu) @[Rocket.scala 454:38] + node _T_4193 = neq(wb_ctrl.csr, UInt<3>("h00")) @[Rocket.scala 456:34] + node _T_4194 = mux(_T_4193, csr.io.rw.rdata, wb_reg_wdata) @[Rocket.scala 456:21] + node _T_4195 = mux(ll_wen, ll_wdata, _T_4194) @[Rocket.scala 455:21] + node rf_wdata = mux(_T_4191, io.dmem.resp.bits.data, _T_4195) @[Rocket.scala 454:21] + when rf_wen : @[Rocket.scala 458:17] + node _T_4197 = neq(rf_waddr, UInt<1>("h00")) @[Rocket.scala 694:16] + when _T_4197 : @[Rocket.scala 694:29] + node _T_4198 = bits(rf_waddr, 4, 0) @[Rocket.scala 683:44] + node _T_4199 = not(_T_4198) @[Rocket.scala 683:39] + infer mport _T_4200 = _T_3331[_T_4199], clock + _T_4200 <= rf_wdata @[Rocket.scala 695:20] + node _T_4201 = eq(rf_waddr, ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 697:20] + when _T_4201 : @[Rocket.scala 697:31] + id_rs_0 <= rf_wdata @[Rocket.scala 697:39] + skip @[Rocket.scala 697:31] + node _T_4202 = eq(rf_waddr, ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 697:20] + when _T_4202 : @[Rocket.scala 697:31] + id_rs_1 <= rf_wdata @[Rocket.scala 697:39] + skip @[Rocket.scala 697:31] + skip @[Rocket.scala 694:29] + skip @[Rocket.scala 458:17] + node _T_4203 = bits(ibuf.io.inst[0].bits.raw, 31, 20) @[Rocket.scala 461:48] + csr.io.decode.csr <= _T_4203 @[Rocket.scala 461:21] + csr.io.exception <= wb_reg_xcpt @[Rocket.scala 462:20] + csr.io.cause <= wb_reg_cause @[Rocket.scala 463:16] + csr.io.retire <= wb_valid @[Rocket.scala 464:17] + csr.io.interrupts <- io.interrupts @[Rocket.scala 465:21] + csr.io.hartid <= io.hartid @[Rocket.scala 466:17] + io.fpu.fcsr_rm <= csr.io.fcsr_rm @[Rocket.scala 467:18] + csr.io.fcsr_flags <- io.fpu.fcsr_flags @[Rocket.scala 468:21] + csr.io.rocc_interrupt <= io.rocc.interrupt @[Rocket.scala 469:25] + csr.io.pc <= wb_reg_pc @[Rocket.scala 470:13] + node _T_4204 = shr(wb_reg_wdata, 38) @[Rocket.scala 653:16] + node _T_4205 = bits(wb_reg_wdata, 39, 38) @[Rocket.scala 654:15] + node _T_4206 = asSInt(_T_4205) @[Rocket.scala 654:39] + node _T_4208 = eq(_T_4204, UInt<1>("h00")) @[Rocket.scala 656:13] + node _T_4210 = eq(_T_4204, UInt<1>("h01")) @[Rocket.scala 656:30] + node _T_4211 = or(_T_4208, _T_4210) @[Rocket.scala 656:25] + node _T_4213 = neq(_T_4206, asSInt(UInt<1>("h00"))) @[Rocket.scala 656:45] + node _T_4214 = asSInt(_T_4204) @[Rocket.scala 657:13] + node _T_4216 = eq(_T_4214, asSInt(UInt<1>("h01"))) @[Rocket.scala 657:20] + node _T_4217 = asSInt(_T_4204) @[Rocket.scala 657:38] + node _T_4219 = eq(_T_4217, asSInt(UInt<2>("h02"))) @[Rocket.scala 657:45] + node _T_4220 = or(_T_4216, _T_4219) @[Rocket.scala 657:33] + node _T_4222 = eq(_T_4206, asSInt(UInt<1>("h01"))) @[Rocket.scala 657:61] + node _T_4223 = bits(_T_4206, 0, 0) @[Rocket.scala 657:76] + node _T_4224 = mux(_T_4220, _T_4222, _T_4223) @[Rocket.scala 657:10] + node _T_4225 = mux(_T_4211, _T_4213, _T_4224) @[Rocket.scala 656:10] + node _T_4226 = bits(wb_reg_wdata, 38, 0) @[Rocket.scala 658:16] + node _T_4227 = cat(_T_4225, _T_4226) @[Cat.scala 30:58] + csr.io.badaddr <= _T_4227 @[Rocket.scala 471:18] + io.ptw.ptbr <- csr.io.ptbr @[Rocket.scala 472:15] + io.ptw.invalidate <= csr.io.fatc @[Rocket.scala 473:21] + io.ptw.status <- csr.io.status @[Rocket.scala 474:17] + node _T_4228 = bits(wb_reg_inst, 31, 20) @[Rocket.scala 475:32] + csr.io.rw.addr <= _T_4228 @[Rocket.scala 475:18] + node _T_4230 = mux(wb_reg_valid, wb_ctrl.csr, UInt<3>("h00")) @[Rocket.scala 476:23] + csr.io.rw.cmd <= _T_4230 @[Rocket.scala 476:17] + csr.io.rw.wdata <= wb_reg_wdata @[Rocket.scala 477:19] + node _T_4232 = neq(ibuf.io.inst[0].bits.inst.rs1, UInt<1>("h00")) @[Rocket.scala 479:55] + node _T_4233 = and(id_ctrl.rxs1, _T_4232) @[Rocket.scala 479:42] + node _T_4235 = neq(ibuf.io.inst[0].bits.inst.rs2, UInt<1>("h00")) @[Rocket.scala 480:55] + node _T_4236 = and(id_ctrl.rxs2, _T_4235) @[Rocket.scala 480:42] + node _T_4238 = neq(ibuf.io.inst[0].bits.inst.rd, UInt<1>("h00")) @[Rocket.scala 481:55] + node _T_4239 = and(id_ctrl.wxd, _T_4238) @[Rocket.scala 481:42] + reg _T_4241 : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Rocket.scala 668:25] + node _T_4242 = shr(_T_4241, 1) @[Rocket.scala 669:35] + node _T_4243 = shl(_T_4242, 1) @[Rocket.scala 669:40] + node _T_4246 = dshl(UInt<1>("h01"), ll_waddr) @[Rocket.scala 672:62] + node _T_4248 = mux(ll_wen, _T_4246, UInt<1>("h00")) @[Rocket.scala 672:49] + node _T_4249 = not(_T_4248) @[Rocket.scala 664:64] + node _T_4250 = and(_T_4243, _T_4249) @[Rocket.scala 664:62] + node _T_4251 = or(UInt<1>("h00"), ll_wen) @[Rocket.scala 675:17] + when _T_4251 : @[Rocket.scala 676:18] + _T_4241 <= _T_4250 @[Rocket.scala 676:23] + skip @[Rocket.scala 676:18] + node _T_4252 = dshr(_T_4243, ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 665:35] + node _T_4253 = bits(_T_4252, 0, 0) @[Rocket.scala 665:35] + node _T_4254 = and(_T_4233, _T_4253) @[Rocket.scala 648:27] + node _T_4255 = dshr(_T_4243, ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 665:35] + node _T_4256 = bits(_T_4255, 0, 0) @[Rocket.scala 665:35] + node _T_4257 = and(_T_4236, _T_4256) @[Rocket.scala 648:27] + node _T_4258 = dshr(_T_4243, ibuf.io.inst[0].bits.inst.rd) @[Rocket.scala 665:35] + node _T_4259 = bits(_T_4258, 0, 0) @[Rocket.scala 665:35] + node _T_4260 = and(_T_4239, _T_4259) @[Rocket.scala 648:27] + node _T_4261 = or(_T_4254, _T_4257) @[Rocket.scala 648:50] + node id_sboard_hazard = or(_T_4261, _T_4260) @[Rocket.scala 648:50] + node _T_4262 = and(wb_set_sboard, wb_wen) @[Rocket.scala 490:28] + node _T_4264 = dshl(UInt<1>("h01"), wb_waddr) @[Rocket.scala 672:62] + node _T_4266 = mux(_T_4262, _T_4264, UInt<1>("h00")) @[Rocket.scala 672:49] + node _T_4267 = or(_T_4250, _T_4266) @[Rocket.scala 663:60] + node _T_4268 = or(_T_4251, _T_4262) @[Rocket.scala 675:17] + when _T_4268 : @[Rocket.scala 676:18] + _T_4241 <= _T_4267 @[Rocket.scala 676:23] + skip @[Rocket.scala 676:18] + node _T_4270 = neq(ex_ctrl.csr, UInt<3>("h00")) @[Rocket.scala 493:38] + node _T_4271 = or(_T_4270, ex_ctrl.jalr) @[Rocket.scala 493:48] + node _T_4272 = or(_T_4271, ex_ctrl.mem) @[Rocket.scala 493:64] + node _T_4273 = or(_T_4272, ex_ctrl.div) @[Rocket.scala 493:79] + node _T_4274 = or(_T_4273, ex_ctrl.fp) @[Rocket.scala 493:94] + node ex_cannot_bypass = or(_T_4274, ex_ctrl.rocc) @[Rocket.scala 493:108] + node _T_4275 = eq(ibuf.io.inst[0].bits.inst.rs1, ex_waddr) @[Rocket.scala 494:70] + node _T_4276 = and(_T_4233, _T_4275) @[Rocket.scala 648:27] + node _T_4277 = eq(ibuf.io.inst[0].bits.inst.rs2, ex_waddr) @[Rocket.scala 494:70] + node _T_4278 = and(_T_4236, _T_4277) @[Rocket.scala 648:27] + node _T_4279 = eq(ibuf.io.inst[0].bits.inst.rd, ex_waddr) @[Rocket.scala 494:70] + node _T_4280 = and(_T_4239, _T_4279) @[Rocket.scala 648:27] + node _T_4281 = or(_T_4276, _T_4278) @[Rocket.scala 648:50] + node _T_4282 = or(_T_4281, _T_4280) @[Rocket.scala 648:50] + node data_hazard_ex = and(ex_ctrl.wxd, _T_4282) @[Rocket.scala 494:36] + node _T_4283 = eq(ibuf.io.inst[0].bits.inst.rs1, ex_waddr) @[Rocket.scala 495:76] + node _T_4284 = and(io.fpu.dec.ren1, _T_4283) @[Rocket.scala 648:27] + node _T_4285 = eq(ibuf.io.inst[0].bits.inst.rs2, ex_waddr) @[Rocket.scala 495:76] + node _T_4286 = and(io.fpu.dec.ren2, _T_4285) @[Rocket.scala 648:27] + node _T_4287 = eq(ibuf.io.inst[0].bits.inst.rs3, ex_waddr) @[Rocket.scala 495:76] + node _T_4288 = and(io.fpu.dec.ren3, _T_4287) @[Rocket.scala 648:27] + node _T_4289 = eq(ibuf.io.inst[0].bits.inst.rd, ex_waddr) @[Rocket.scala 495:76] + node _T_4290 = and(io.fpu.dec.wen, _T_4289) @[Rocket.scala 648:27] + node _T_4291 = or(_T_4284, _T_4286) @[Rocket.scala 648:50] + node _T_4292 = or(_T_4291, _T_4288) @[Rocket.scala 648:50] + node _T_4293 = or(_T_4292, _T_4290) @[Rocket.scala 648:50] + node fp_data_hazard_ex = and(ex_ctrl.wfd, _T_4293) @[Rocket.scala 495:39] + node _T_4294 = and(data_hazard_ex, ex_cannot_bypass) @[Rocket.scala 496:54] + node _T_4295 = or(_T_4294, fp_data_hazard_ex) @[Rocket.scala 496:74] + node id_ex_hazard = and(ex_reg_valid, _T_4295) @[Rocket.scala 496:35] + node mem_mem_cmd_bh = and(UInt<1>("h01"), mem_reg_slow_bypass) @[Rocket.scala 500:43] + node _T_4298 = neq(mem_ctrl.csr, UInt<3>("h00")) @[Rocket.scala 502:40] + node _T_4299 = and(mem_ctrl.mem, mem_mem_cmd_bh) @[Rocket.scala 502:66] + node _T_4300 = or(_T_4298, _T_4299) @[Rocket.scala 502:50] + node _T_4301 = or(_T_4300, mem_ctrl.div) @[Rocket.scala 502:84] + node _T_4302 = or(_T_4301, mem_ctrl.fp) @[Rocket.scala 502:100] + node mem_cannot_bypass = or(_T_4302, mem_ctrl.rocc) @[Rocket.scala 502:115] + node _T_4303 = eq(ibuf.io.inst[0].bits.inst.rs1, mem_waddr) @[Rocket.scala 503:72] + node _T_4304 = and(_T_4233, _T_4303) @[Rocket.scala 648:27] + node _T_4305 = eq(ibuf.io.inst[0].bits.inst.rs2, mem_waddr) @[Rocket.scala 503:72] + node _T_4306 = and(_T_4236, _T_4305) @[Rocket.scala 648:27] + node _T_4307 = eq(ibuf.io.inst[0].bits.inst.rd, mem_waddr) @[Rocket.scala 503:72] + node _T_4308 = and(_T_4239, _T_4307) @[Rocket.scala 648:27] + node _T_4309 = or(_T_4304, _T_4306) @[Rocket.scala 648:50] + node _T_4310 = or(_T_4309, _T_4308) @[Rocket.scala 648:50] + node data_hazard_mem = and(mem_ctrl.wxd, _T_4310) @[Rocket.scala 503:38] + node _T_4311 = eq(ibuf.io.inst[0].bits.inst.rs1, mem_waddr) @[Rocket.scala 504:78] + node _T_4312 = and(io.fpu.dec.ren1, _T_4311) @[Rocket.scala 648:27] + node _T_4313 = eq(ibuf.io.inst[0].bits.inst.rs2, mem_waddr) @[Rocket.scala 504:78] + node _T_4314 = and(io.fpu.dec.ren2, _T_4313) @[Rocket.scala 648:27] + node _T_4315 = eq(ibuf.io.inst[0].bits.inst.rs3, mem_waddr) @[Rocket.scala 504:78] + node _T_4316 = and(io.fpu.dec.ren3, _T_4315) @[Rocket.scala 648:27] + node _T_4317 = eq(ibuf.io.inst[0].bits.inst.rd, mem_waddr) @[Rocket.scala 504:78] + node _T_4318 = and(io.fpu.dec.wen, _T_4317) @[Rocket.scala 648:27] + node _T_4319 = or(_T_4312, _T_4314) @[Rocket.scala 648:50] + node _T_4320 = or(_T_4319, _T_4316) @[Rocket.scala 648:50] + node _T_4321 = or(_T_4320, _T_4318) @[Rocket.scala 648:50] + node fp_data_hazard_mem = and(mem_ctrl.wfd, _T_4321) @[Rocket.scala 504:41] + node _T_4322 = and(data_hazard_mem, mem_cannot_bypass) @[Rocket.scala 505:57] + node _T_4323 = or(_T_4322, fp_data_hazard_mem) @[Rocket.scala 505:78] + node id_mem_hazard = and(mem_reg_valid, _T_4323) @[Rocket.scala 505:37] + node _T_4324 = and(mem_reg_valid, data_hazard_mem) @[Rocket.scala 506:32] + node _T_4325 = and(_T_4324, mem_ctrl.mem) @[Rocket.scala 506:51] + id_load_use <= _T_4325 @[Rocket.scala 506:15] + node _T_4326 = eq(ibuf.io.inst[0].bits.inst.rs1, wb_waddr) @[Rocket.scala 509:70] + node _T_4327 = and(_T_4233, _T_4326) @[Rocket.scala 648:27] + node _T_4328 = eq(ibuf.io.inst[0].bits.inst.rs2, wb_waddr) @[Rocket.scala 509:70] + node _T_4329 = and(_T_4236, _T_4328) @[Rocket.scala 648:27] + node _T_4330 = eq(ibuf.io.inst[0].bits.inst.rd, wb_waddr) @[Rocket.scala 509:70] + node _T_4331 = and(_T_4239, _T_4330) @[Rocket.scala 648:27] + node _T_4332 = or(_T_4327, _T_4329) @[Rocket.scala 648:50] + node _T_4333 = or(_T_4332, _T_4331) @[Rocket.scala 648:50] + node data_hazard_wb = and(wb_ctrl.wxd, _T_4333) @[Rocket.scala 509:36] + node _T_4334 = eq(ibuf.io.inst[0].bits.inst.rs1, wb_waddr) @[Rocket.scala 510:76] + node _T_4335 = and(io.fpu.dec.ren1, _T_4334) @[Rocket.scala 648:27] + node _T_4336 = eq(ibuf.io.inst[0].bits.inst.rs2, wb_waddr) @[Rocket.scala 510:76] + node _T_4337 = and(io.fpu.dec.ren2, _T_4336) @[Rocket.scala 648:27] + node _T_4338 = eq(ibuf.io.inst[0].bits.inst.rs3, wb_waddr) @[Rocket.scala 510:76] + node _T_4339 = and(io.fpu.dec.ren3, _T_4338) @[Rocket.scala 648:27] + node _T_4340 = eq(ibuf.io.inst[0].bits.inst.rd, wb_waddr) @[Rocket.scala 510:76] + node _T_4341 = and(io.fpu.dec.wen, _T_4340) @[Rocket.scala 648:27] + node _T_4342 = or(_T_4335, _T_4337) @[Rocket.scala 648:50] + node _T_4343 = or(_T_4342, _T_4339) @[Rocket.scala 648:50] + node _T_4344 = or(_T_4343, _T_4341) @[Rocket.scala 648:50] + node fp_data_hazard_wb = and(wb_ctrl.wfd, _T_4344) @[Rocket.scala 510:39] + node _T_4345 = and(data_hazard_wb, wb_set_sboard) @[Rocket.scala 511:54] + node _T_4346 = or(_T_4345, fp_data_hazard_wb) @[Rocket.scala 511:71] + node id_wb_hazard = and(wb_reg_valid, _T_4346) @[Rocket.scala 511:35] + reg _T_4348 : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Rocket.scala 668:25] + node _T_4350 = and(wb_dcache_miss, wb_ctrl.wfd) @[Rocket.scala 515:35] + node _T_4351 = or(_T_4350, io.fpu.sboard_set) @[Rocket.scala 515:50] + node _T_4352 = and(_T_4351, wb_valid) @[Rocket.scala 515:72] + node _T_4354 = dshl(UInt<1>("h01"), wb_waddr) @[Rocket.scala 672:62] + node _T_4356 = mux(_T_4352, _T_4354, UInt<1>("h00")) @[Rocket.scala 672:49] + node _T_4357 = or(_T_4348, _T_4356) @[Rocket.scala 663:60] + node _T_4358 = or(UInt<1>("h00"), _T_4352) @[Rocket.scala 675:17] + when _T_4358 : @[Rocket.scala 676:18] + _T_4348 <= _T_4357 @[Rocket.scala 676:23] + skip @[Rocket.scala 676:18] + node _T_4359 = and(dmem_resp_replay, dmem_resp_fpu) @[Rocket.scala 516:38] + node _T_4361 = dshl(UInt<1>("h01"), dmem_resp_waddr) @[Rocket.scala 672:62] + node _T_4363 = mux(_T_4359, _T_4361, UInt<1>("h00")) @[Rocket.scala 672:49] + node _T_4364 = not(_T_4363) @[Rocket.scala 664:64] + node _T_4365 = and(_T_4357, _T_4364) @[Rocket.scala 664:62] + node _T_4366 = or(_T_4358, _T_4359) @[Rocket.scala 675:17] + when _T_4366 : @[Rocket.scala 676:18] + _T_4348 <= _T_4365 @[Rocket.scala 676:23] + skip @[Rocket.scala 676:18] + node _T_4368 = dshl(UInt<1>("h01"), io.fpu.sboard_clra) @[Rocket.scala 672:62] + node _T_4370 = mux(io.fpu.sboard_clr, _T_4368, UInt<1>("h00")) @[Rocket.scala 672:49] + node _T_4371 = not(_T_4370) @[Rocket.scala 664:64] + node _T_4372 = and(_T_4365, _T_4371) @[Rocket.scala 664:62] + node _T_4373 = or(_T_4366, io.fpu.sboard_clr) @[Rocket.scala 675:17] + when _T_4373 : @[Rocket.scala 676:18] + _T_4348 <= _T_4372 @[Rocket.scala 676:23] + skip @[Rocket.scala 676:18] + node _T_4375 = eq(io.fpu.fcsr_rdy, UInt<1>("h00")) @[Rocket.scala 519:18] + node _T_4376 = and(id_csr_en, _T_4375) @[Rocket.scala 519:15] + node _T_4377 = dshr(_T_4348, ibuf.io.inst[0].bits.inst.rs1) @[Rocket.scala 665:35] + node _T_4378 = bits(_T_4377, 0, 0) @[Rocket.scala 665:35] + node _T_4379 = and(io.fpu.dec.ren1, _T_4378) @[Rocket.scala 648:27] + node _T_4380 = dshr(_T_4348, ibuf.io.inst[0].bits.inst.rs2) @[Rocket.scala 665:35] + node _T_4381 = bits(_T_4380, 0, 0) @[Rocket.scala 665:35] + node _T_4382 = and(io.fpu.dec.ren2, _T_4381) @[Rocket.scala 648:27] + node _T_4383 = dshr(_T_4348, ibuf.io.inst[0].bits.inst.rs3) @[Rocket.scala 665:35] + node _T_4384 = bits(_T_4383, 0, 0) @[Rocket.scala 665:35] + node _T_4385 = and(io.fpu.dec.ren3, _T_4384) @[Rocket.scala 648:27] + node _T_4386 = dshr(_T_4348, ibuf.io.inst[0].bits.inst.rd) @[Rocket.scala 665:35] + node _T_4387 = bits(_T_4386, 0, 0) @[Rocket.scala 665:35] + node _T_4388 = and(io.fpu.dec.wen, _T_4387) @[Rocket.scala 648:27] + node _T_4389 = or(_T_4379, _T_4382) @[Rocket.scala 648:50] + node _T_4390 = or(_T_4389, _T_4385) @[Rocket.scala 648:50] + node _T_4391 = or(_T_4390, _T_4388) @[Rocket.scala 648:50] + node id_stall_fpu = or(_T_4376, _T_4391) @[Rocket.scala 519:35] + reg dcache_blocked : UInt<1>, clock @[Rocket.scala 522:27] + node _T_4394 = eq(io.dmem.req.ready, UInt<1>("h00")) @[Rocket.scala 523:21] + node _T_4395 = or(io.dmem.req.valid, dcache_blocked) @[Rocket.scala 523:62] + node _T_4396 = and(_T_4394, _T_4395) @[Rocket.scala 523:40] + dcache_blocked <= _T_4396 @[Rocket.scala 523:18] + reg rocc_blocked : UInt<1>, clock @[Rocket.scala 524:25] + node _T_4399 = eq(wb_reg_xcpt, UInt<1>("h00")) @[Rocket.scala 525:19] + node _T_4401 = eq(io.rocc.cmd.ready, UInt<1>("h00")) @[Rocket.scala 525:35] + node _T_4402 = and(_T_4399, _T_4401) @[Rocket.scala 525:32] + node _T_4403 = or(io.rocc.cmd.valid, rocc_blocked) @[Rocket.scala 525:76] + node _T_4404 = and(_T_4402, _T_4403) @[Rocket.scala 525:54] + rocc_blocked <= _T_4404 @[Rocket.scala 525:16] + node _T_4405 = or(id_ex_hazard, id_mem_hazard) @[Rocket.scala 528:18] + node _T_4406 = or(_T_4405, id_wb_hazard) @[Rocket.scala 528:35] + node _T_4407 = or(_T_4406, id_sboard_hazard) @[Rocket.scala 528:51] + node _T_4408 = and(id_ctrl.fp, id_stall_fpu) @[Rocket.scala 529:16] + node _T_4409 = or(_T_4407, _T_4408) @[Rocket.scala 528:71] + node _T_4410 = and(id_ctrl.mem, dcache_blocked) @[Rocket.scala 530:17] + node _T_4411 = or(_T_4409, _T_4410) @[Rocket.scala 529:32] + node _T_4412 = and(id_ctrl.rocc, rocc_blocked) @[Rocket.scala 531:18] + node _T_4413 = or(_T_4411, _T_4412) @[Rocket.scala 530:35] + node _T_4415 = eq(wb_wxd, UInt<1>("h00")) @[Rocket.scala 532:65] + node _T_4416 = and(div.io.resp.valid, _T_4415) @[Rocket.scala 532:62] + node _T_4417 = or(div.io.req.ready, _T_4416) @[Rocket.scala 532:40] + node _T_4419 = eq(_T_4417, UInt<1>("h00")) @[Rocket.scala 532:21] + node _T_4420 = or(_T_4419, div.io.req.valid) @[Rocket.scala 532:75] + node _T_4421 = and(id_ctrl.div, _T_4420) @[Rocket.scala 532:17] + node _T_4422 = or(_T_4413, _T_4421) @[Rocket.scala 531:34] + node _T_4423 = or(_T_4422, id_do_fence) @[Rocket.scala 532:96] + node ctrl_stalld = or(_T_4423, csr.io.csr_stall) @[Rocket.scala 533:17] + node _T_4425 = eq(ibuf.io.inst[0].valid, UInt<1>("h00")) @[Rocket.scala 535:17] + node _T_4426 = or(_T_4425, ibuf.io.inst[0].bits.replay) @[Rocket.scala 535:40] + node _T_4427 = or(_T_4426, take_pc_mem_wb) @[Rocket.scala 535:71] + node _T_4428 = or(_T_4427, ctrl_stalld) @[Rocket.scala 535:89] + node _T_4429 = or(_T_4428, csr.io.interrupt) @[Rocket.scala 535:104] + ctrl_killd <= _T_4429 @[Rocket.scala 535:14] + io.imem.req.valid <= take_pc @[Rocket.scala 537:21] + node _T_4431 = eq(take_pc_wb, UInt<1>("h00")) @[Rocket.scala 538:35] + io.imem.req.bits.speculative <= _T_4431 @[Rocket.scala 538:32] + node _T_4432 = or(wb_reg_xcpt, csr.io.eret) @[Rocket.scala 540:17] + node _T_4434 = or(take_pc_mem, UInt<1>("h01")) @[Rocket.scala 542:21] + node _T_4435 = mux(_T_4434, mem_npc, id_npc) @[Rocket.scala 542:8] + node _T_4436 = mux(replay_wb, wb_reg_pc, _T_4435) @[Rocket.scala 541:8] + node _T_4437 = mux(_T_4432, csr.io.evec, _T_4436) @[Rocket.scala 540:8] + io.imem.req.bits.pc <= _T_4437 @[Rocket.scala 539:23] + node _T_4438 = and(wb_reg_valid, wb_ctrl.fence_i) @[Rocket.scala 544:40] + node _T_4440 = eq(io.dmem.s2_nack, UInt<1>("h00")) @[Rocket.scala 544:62] + node _T_4441 = and(_T_4438, _T_4440) @[Rocket.scala 544:59] + io.imem.flush_icache <= _T_4441 @[Rocket.scala 544:24] + io.imem.flush_tlb <= csr.io.fatc @[Rocket.scala 545:21] + node _T_4443 = eq(ctrl_stalld, UInt<1>("h00")) @[Rocket.scala 547:28] + node _T_4444 = or(_T_4443, csr.io.interrupt) @[Rocket.scala 547:41] + ibuf.io.inst[0].ready <= _T_4444 @[Rocket.scala 547:25] + node _T_4445 = and(mem_reg_replay, mem_reg_btb_hit) @[Rocket.scala 549:47] + node _T_4447 = eq(take_pc_wb, UInt<1>("h00")) @[Rocket.scala 549:88] + node _T_4448 = and(mem_reg_valid, _T_4447) @[Rocket.scala 549:85] + node _T_4450 = eq(mem_cfi, UInt<1>("h00")) @[Rocket.scala 549:123] + node _T_4451 = or(mem_cfi_taken, _T_4450) @[Rocket.scala 549:120] + node _T_4452 = and(_T_4451, mem_misprediction) @[Rocket.scala 549:133] + node _T_4454 = and(UInt<1>("h00"), mem_ctrl.jal) @[Rocket.scala 549:169] + node _T_4456 = eq(mem_reg_btb_hit, UInt<1>("h00")) @[Rocket.scala 549:188] + node _T_4457 = and(_T_4454, _T_4456) @[Rocket.scala 549:185] + node _T_4458 = or(_T_4452, _T_4457) @[Rocket.scala 549:151] + node _T_4459 = and(_T_4448, _T_4458) @[Rocket.scala 549:100] + node _T_4460 = or(_T_4445, _T_4459) @[Rocket.scala 549:67] + io.imem.btb_update.valid <= _T_4460 @[Rocket.scala 549:28] + node _T_4462 = eq(mem_reg_replay, UInt<1>("h00")) @[Rocket.scala 550:38] + node _T_4463 = and(_T_4462, mem_cfi) @[Rocket.scala 550:54] + io.imem.btb_update.bits.isValid <= _T_4463 @[Rocket.scala 550:35] + node _T_4464 = or(mem_ctrl.jal, mem_ctrl.jalr) @[Rocket.scala 551:50] + io.imem.btb_update.bits.isJump <= _T_4464 @[Rocket.scala 551:34] + node _T_4465 = bits(mem_reg_inst, 19, 15) @[Rocket.scala 552:68] + node _T_4468 = and(_T_4465, UInt<5>("h01b")) @[Rocket.scala 552:76] + node _T_4469 = eq(UInt<1>("h01"), _T_4468) @[Rocket.scala 552:76] + node _T_4470 = and(mem_ctrl.jalr, _T_4469) @[Rocket.scala 552:53] + io.imem.btb_update.bits.isReturn <= _T_4470 @[Rocket.scala 552:36] + io.imem.btb_update.bits.target <= io.imem.req.bits.pc @[Rocket.scala 553:34] + node _T_4473 = mux(mem_reg_rvc, UInt<1>("h00"), UInt<2>("h02")) @[Rocket.scala 554:74] + node _T_4474 = add(mem_reg_pc, _T_4473) @[Rocket.scala 554:69] + node _T_4475 = tail(_T_4474, 1) @[Rocket.scala 554:69] + io.imem.btb_update.bits.br_pc <= _T_4475 @[Rocket.scala 554:33] + node _T_4476 = not(io.imem.btb_update.bits.br_pc) @[Rocket.scala 555:35] + node _T_4478 = or(_T_4476, UInt<2>("h03")) @[Rocket.scala 555:66] + node _T_4479 = not(_T_4478) @[Rocket.scala 555:33] + io.imem.btb_update.bits.pc <= _T_4479 @[Rocket.scala 555:30] + io.imem.btb_update.bits.prediction.valid <= mem_reg_btb_hit @[Rocket.scala 556:44] + io.imem.btb_update.bits.prediction.bits <- mem_reg_btb_resp @[Rocket.scala 557:43] + node _T_4481 = eq(take_pc_wb, UInt<1>("h00")) @[Rocket.scala 559:48] + node _T_4482 = and(mem_reg_valid, _T_4481) @[Rocket.scala 559:45] + node _T_4483 = and(_T_4482, mem_ctrl.branch) @[Rocket.scala 559:60] + io.imem.bht_update.valid <= _T_4483 @[Rocket.scala 559:28] + io.imem.bht_update.bits.pc <= io.imem.btb_update.bits.pc @[Rocket.scala 560:30] + io.imem.bht_update.bits.taken <= mem_br_taken @[Rocket.scala 561:33] + io.imem.bht_update.bits.mispredict <= mem_misprediction @[Rocket.scala 562:38] + io.imem.bht_update.bits.prediction <- io.imem.btb_update.bits.prediction @[Rocket.scala 563:38] + node _T_4485 = eq(take_pc_wb, UInt<1>("h00")) @[Rocket.scala 565:48] + node _T_4486 = and(mem_reg_valid, _T_4485) @[Rocket.scala 565:45] + io.imem.ras_update.valid <= _T_4486 @[Rocket.scala 565:28] + io.imem.ras_update.bits.returnAddr <= mem_int_wdata @[Rocket.scala 566:38] + node _T_4487 = bits(mem_waddr, 0, 0) @[Rocket.scala 567:80] + node _T_4488 = and(io.imem.btb_update.bits.isJump, _T_4487) @[Rocket.scala 567:68] + io.imem.ras_update.bits.isCall <= _T_4488 @[Rocket.scala 567:34] + io.imem.ras_update.bits.isReturn <= io.imem.btb_update.bits.isReturn @[Rocket.scala 568:36] + io.imem.ras_update.bits.prediction <- io.imem.btb_update.bits.prediction @[Rocket.scala 569:38] + node _T_4490 = eq(ctrl_killd, UInt<1>("h00")) @[Rocket.scala 571:19] + node _T_4491 = and(_T_4490, id_ctrl.fp) @[Rocket.scala 571:31] + io.fpu.valid <= _T_4491 @[Rocket.scala 571:16] + io.fpu.killx <= ctrl_killx @[Rocket.scala 572:16] + io.fpu.killm <= killm_common @[Rocket.scala 573:16] + io.fpu.inst <= ibuf.io.inst[0].bits.inst.bits @[Rocket.scala 574:15] + io.fpu.fromint_data <= ex_rs_0 @[Rocket.scala 575:23] + node _T_4492 = and(dmem_resp_valid, dmem_resp_fpu) @[Rocket.scala 576:43] + io.fpu.dmem_resp_val <= _T_4492 @[Rocket.scala 576:24] + io.fpu.dmem_resp_data <= io.dmem.resp.bits.data_word_bypass @[Rocket.scala 577:25] + io.fpu.dmem_resp_type <= io.dmem.resp.bits.typ @[Rocket.scala 578:25] + io.fpu.dmem_resp_tag <= dmem_resp_waddr @[Rocket.scala 579:24] + node _T_4493 = and(ex_reg_valid, ex_ctrl.mem) @[Rocket.scala 581:41] + io.dmem.req.valid <= _T_4493 @[Rocket.scala 581:25] + node ex_dcache_tag = cat(ex_waddr, ex_ctrl.fp) @[Cat.scala 30:58] + io.dmem.req.bits.tag <= ex_dcache_tag @[Rocket.scala 584:25] + io.dmem.req.bits.cmd <= ex_ctrl.mem_cmd @[Rocket.scala 585:25] + io.dmem.req.bits.typ <= ex_ctrl.mem_type @[Rocket.scala 586:25] + io.dmem.req.bits.phys <= UInt<1>("h00") @[Rocket.scala 587:25] + node _T_4495 = shr(ex_rs_0, 38) @[Rocket.scala 653:16] + node _T_4496 = bits(alu.io.adder_out, 39, 38) @[Rocket.scala 654:15] + node _T_4497 = asSInt(_T_4496) @[Rocket.scala 654:39] + node _T_4499 = eq(_T_4495, UInt<1>("h00")) @[Rocket.scala 656:13] + node _T_4501 = eq(_T_4495, UInt<1>("h01")) @[Rocket.scala 656:30] + node _T_4502 = or(_T_4499, _T_4501) @[Rocket.scala 656:25] + node _T_4504 = neq(_T_4497, asSInt(UInt<1>("h00"))) @[Rocket.scala 656:45] + node _T_4505 = asSInt(_T_4495) @[Rocket.scala 657:13] + node _T_4507 = eq(_T_4505, asSInt(UInt<1>("h01"))) @[Rocket.scala 657:20] + node _T_4508 = asSInt(_T_4495) @[Rocket.scala 657:38] + node _T_4510 = eq(_T_4508, asSInt(UInt<2>("h02"))) @[Rocket.scala 657:45] + node _T_4511 = or(_T_4507, _T_4510) @[Rocket.scala 657:33] + node _T_4513 = eq(_T_4497, asSInt(UInt<1>("h01"))) @[Rocket.scala 657:61] + node _T_4514 = bits(_T_4497, 0, 0) @[Rocket.scala 657:76] + node _T_4515 = mux(_T_4511, _T_4513, _T_4514) @[Rocket.scala 657:10] + node _T_4516 = mux(_T_4502, _T_4504, _T_4515) @[Rocket.scala 656:10] + node _T_4517 = bits(alu.io.adder_out, 38, 0) @[Rocket.scala 658:16] + node _T_4518 = cat(_T_4516, _T_4517) @[Cat.scala 30:58] + io.dmem.req.bits.addr <= _T_4518 @[Rocket.scala 588:25] + io.dmem.invalidate_lr <= wb_reg_xcpt @[Rocket.scala 589:25] + node _T_4519 = mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2) @[Rocket.scala 590:25] + io.dmem.s1_data <= _T_4519 @[Rocket.scala 590:19] + node _T_4520 = or(killm_common, mem_breakpoint) @[Rocket.scala 591:35] + io.dmem.s1_kill <= _T_4520 @[Rocket.scala 591:19] + node _T_4521 = and(mem_ctrl.mem, mem_xcpt) @[Rocket.scala 592:22] + node _T_4523 = eq(io.dmem.s1_kill, UInt<1>("h00")) @[Rocket.scala 592:37] + node _T_4524 = and(_T_4521, _T_4523) @[Rocket.scala 592:34] + when _T_4524 : @[Rocket.scala 592:55] + node _T_4525 = cat(io.dmem.xcpt.pf.ld, io.dmem.xcpt.pf.st) @[Rocket.scala 593:25] + node _T_4526 = cat(io.dmem.xcpt.ma.ld, io.dmem.xcpt.ma.st) @[Rocket.scala 593:25] + node _T_4527 = cat(_T_4526, _T_4525) @[Rocket.scala 593:25] + node _T_4529 = neq(_T_4527, UInt<1>("h00")) @[Rocket.scala 593:32] + node _T_4530 = or(_T_4529, reset) @[Rocket.scala 593:11] + node _T_4532 = eq(_T_4530, UInt<1>("h00")) @[Rocket.scala 593:11] + when _T_4532 : @[Rocket.scala 593:11] + printf(clock, UInt<1>(1), "Assertion failed\n at Rocket.scala:593 assert(io.dmem.xcpt.asUInt.orR) // make sure s1_kill is exhaustive\n") @[Rocket.scala 593:11] + stop(clock, UInt<1>(1), 1) @[Rocket.scala 593:11] + skip @[Rocket.scala 593:11] + skip @[Rocket.scala 592:55] + node _T_4533 = and(wb_reg_valid, wb_ctrl.rocc) @[Rocket.scala 596:37] + node _T_4535 = eq(replay_wb_common, UInt<1>("h00")) @[Rocket.scala 596:56] + node _T_4536 = and(_T_4533, _T_4535) @[Rocket.scala 596:53] + io.rocc.cmd.valid <= _T_4536 @[Rocket.scala 596:21] + node _T_4538 = neq(csr.io.status.xs, UInt<1>("h00")) @[Rocket.scala 597:52] + node _T_4539 = and(wb_reg_xcpt, _T_4538) @[Rocket.scala 597:32] + io.rocc.exception <= _T_4539 @[Rocket.scala 597:21] + io.rocc.cmd.bits.status <- csr.io.status @[Rocket.scala 598:27] + wire _T_4558 : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} @[Rocket.scala 599:58] + _T_4558 is invalid @[Rocket.scala 599:58] + wire _T_4568 : UInt<32> + _T_4568 is invalid + _T_4568 <= wb_reg_inst + node _T_4569 = bits(_T_4568, 6, 0) @[Rocket.scala 599:58] + _T_4558.opcode <= _T_4569 @[Rocket.scala 599:58] + node _T_4570 = bits(_T_4568, 11, 7) @[Rocket.scala 599:58] + _T_4558.rd <= _T_4570 @[Rocket.scala 599:58] + node _T_4571 = bits(_T_4568, 12, 12) @[Rocket.scala 599:58] + _T_4558.xs2 <= _T_4571 @[Rocket.scala 599:58] + node _T_4572 = bits(_T_4568, 13, 13) @[Rocket.scala 599:58] + _T_4558.xs1 <= _T_4572 @[Rocket.scala 599:58] + node _T_4573 = bits(_T_4568, 14, 14) @[Rocket.scala 599:58] + _T_4558.xd <= _T_4573 @[Rocket.scala 599:58] + node _T_4574 = bits(_T_4568, 19, 15) @[Rocket.scala 599:58] + _T_4558.rs1 <= _T_4574 @[Rocket.scala 599:58] + node _T_4575 = bits(_T_4568, 24, 20) @[Rocket.scala 599:58] + _T_4558.rs2 <= _T_4575 @[Rocket.scala 599:58] + node _T_4576 = bits(_T_4568, 31, 25) @[Rocket.scala 599:58] + _T_4558.funct <= _T_4576 @[Rocket.scala 599:58] + io.rocc.cmd.bits.inst <- _T_4558 @[Rocket.scala 599:25] + io.rocc.cmd.bits.rs1 <= wb_reg_wdata @[Rocket.scala 600:24] + io.rocc.cmd.bits.rs2 <= wb_reg_rs2 @[Rocket.scala 601:24] + node _T_4577 = bits(csr.io.time, 31, 0) @[Rocket.scala 637:32] + node _T_4579 = mux(rf_wen, rf_waddr, UInt<1>("h00")) @[Rocket.scala 638:13] + node _T_4580 = bits(wb_reg_inst, 19, 15) @[Rocket.scala 639:21] + reg _T_4581 : UInt, clock @[Rocket.scala 639:42] + _T_4581 <= ex_rs_0 @[Rocket.scala 639:42] + reg _T_4582 : UInt, clock @[Rocket.scala 639:33] + _T_4582 <= _T_4581 @[Rocket.scala 639:33] + node _T_4583 = bits(wb_reg_inst, 24, 20) @[Rocket.scala 640:21] + reg _T_4584 : UInt, clock @[Rocket.scala 640:42] + _T_4584 <= ex_rs_1 @[Rocket.scala 640:42] + reg _T_4585 : UInt, clock @[Rocket.scala 640:33] + _T_4585 <= _T_4584 @[Rocket.scala 640:33] + node _T_4587 = eq(reset, UInt<1>("h00")) @[Rocket.scala 636:11] + when _T_4587 : @[Rocket.scala 636:11] + printf(clock, UInt<1>(1), "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.hartid, _T_4577, wb_valid, wb_reg_pc, _T_4579, rf_wdata, rf_wen, _T_4580, _T_4582, _T_4583, _T_4585, wb_reg_inst, wb_reg_inst) @[Rocket.scala 636:11] + skip @[Rocket.scala 636:11] + + module IBuf : + input clock : Clock + input reset : UInt<1> + output io : {flip imem : {flip ready : UInt<1>, valid : UInt<1>, bits : {btb : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt_if : UInt<1>, replay : UInt<1>}}, flip kill : UInt<1>, pc : UInt<40>, btb_resp : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, inst : {flip ready : UInt<1>, valid : UInt<1>, bits : {pf0 : UInt<1>, pf1 : UInt<1>, replay : UInt<1>, btb_hit : UInt<1>, rvc : UInt<1>, inst : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, raw : UInt<32>}}[1]} + + io is invalid + io is invalid + reg nBufValid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[IBuf.scala 35:47] + reg buf : {btb : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt_if : UInt<1>, replay : UInt<1>}, clock @[IBuf.scala 36:16] + reg ibufBTBHit : UInt<1>, clock @[IBuf.scala 37:23] + reg ibufBTBResp : {taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clock @[IBuf.scala 38:24] + node pcWordBits = bits(io.imem.bits.pc, 1, 1) @[Package.scala 44:13] + wire nReady : UInt<2> + nReady is invalid + nReady <= UInt<2>("h00") + node _T_375 = and(io.imem.bits.btb.valid, io.imem.bits.btb.bits.taken) @[IBuf.scala 43:40] + node _T_377 = add(io.imem.bits.btb.bits.bridx, UInt<1>("h01")) @[IBuf.scala 43:100] + node _T_379 = mux(_T_375, _T_377, UInt<2>("h02")) @[IBuf.scala 43:16] + node _T_380 = sub(_T_379, pcWordBits) @[IBuf.scala 43:124] + node _T_381 = asUInt(_T_380) @[IBuf.scala 43:124] + node nIC = tail(_T_381, 1) @[IBuf.scala 43:124] + node _T_382 = sub(nReady, nBufValid) @[IBuf.scala 44:25] + node _T_383 = asUInt(_T_382) @[IBuf.scala 44:25] + node nICReady = tail(_T_383, 1) @[IBuf.scala 44:25] + node _T_385 = mux(io.imem.valid, nIC, UInt<1>("h00")) @[IBuf.scala 45:19] + node _T_386 = add(_T_385, nBufValid) @[IBuf.scala 45:49] + node nValid = tail(_T_386, 1) @[IBuf.scala 45:49] + node _T_387 = geq(nReady, nBufValid) @[IBuf.scala 46:27] + node _T_388 = geq(nICReady, nIC) @[IBuf.scala 46:53] + node _T_390 = sub(nIC, nICReady) @[IBuf.scala 46:72] + node _T_391 = asUInt(_T_390) @[IBuf.scala 46:72] + node _T_392 = tail(_T_391, 1) @[IBuf.scala 46:72] + node _T_393 = geq(UInt<1>("h01"), _T_392) @[IBuf.scala 46:65] + node _T_394 = or(_T_388, _T_393) @[IBuf.scala 46:60] + node _T_395 = and(_T_387, _T_394) @[IBuf.scala 46:40] + io.imem.ready <= _T_395 @[IBuf.scala 46:17] + node _T_396 = geq(nReady, nBufValid) @[IBuf.scala 49:29] + node _T_398 = sub(nBufValid, nReady) @[IBuf.scala 49:62] + node _T_399 = asUInt(_T_398) @[IBuf.scala 49:62] + node _T_400 = tail(_T_399, 1) @[IBuf.scala 49:62] + node _T_401 = mux(_T_396, UInt<1>("h00"), _T_400) @[IBuf.scala 49:21] + nBufValid <= _T_401 @[IBuf.scala 49:15] + node _T_402 = geq(nReady, nBufValid) @[IBuf.scala 56:35] + node _T_403 = and(io.imem.valid, _T_402) @[IBuf.scala 56:25] + node _T_404 = lt(nICReady, nIC) @[IBuf.scala 56:60] + node _T_405 = and(_T_403, _T_404) @[IBuf.scala 56:48] + node _T_407 = sub(nIC, nICReady) @[IBuf.scala 56:78] + node _T_408 = asUInt(_T_407) @[IBuf.scala 56:78] + node _T_409 = tail(_T_408, 1) @[IBuf.scala 56:78] + node _T_410 = geq(UInt<1>("h01"), _T_409) @[IBuf.scala 56:71] + node _T_411 = and(_T_405, _T_410) @[IBuf.scala 56:66] + when _T_411 : @[IBuf.scala 56:90] + node _T_412 = add(pcWordBits, nICReady) @[IBuf.scala 57:30] + node _T_413 = tail(_T_412, 1) @[IBuf.scala 57:30] + node _T_414 = sub(nIC, nICReady) @[IBuf.scala 58:24] + node _T_415 = asUInt(_T_414) @[IBuf.scala 58:24] + node _T_416 = tail(_T_415, 1) @[IBuf.scala 58:24] + nBufValid <= _T_416 @[IBuf.scala 58:17] + buf <- io.imem.bits @[IBuf.scala 59:11] + node _T_417 = shr(io.imem.bits.data, 16) @[IBuf.scala 133:58] + node _T_418 = cat(_T_417, _T_417) @[Cat.scala 30:58] + node _T_419 = cat(_T_418, io.imem.bits.data) @[Cat.scala 30:58] + node _T_420 = shl(_T_413, 4) @[IBuf.scala 134:19] + node _T_421 = dshr(_T_419, _T_420) @[IBuf.scala 134:10] + node _T_422 = bits(_T_421, 15, 0) @[IBuf.scala 60:59] + buf.data <= _T_422 @[IBuf.scala 60:16] + node _T_423 = not(UInt<40>("h03")) @[IBuf.scala 61:35] + node _T_424 = and(io.imem.bits.pc, _T_423) @[IBuf.scala 61:33] + node _T_425 = shl(nICReady, 1) @[IBuf.scala 61:78] + node _T_426 = add(io.imem.bits.pc, _T_425) @[IBuf.scala 61:66] + node _T_427 = tail(_T_426, 1) @[IBuf.scala 61:66] + node _T_428 = and(_T_427, UInt<40>("h03")) @[IBuf.scala 61:107] + node _T_429 = or(_T_424, _T_428) @[IBuf.scala 61:47] + buf.pc <= _T_429 @[IBuf.scala 61:14] + ibufBTBHit <= io.imem.bits.btb.valid @[IBuf.scala 62:18] + when io.imem.bits.btb.valid : @[IBuf.scala 63:37] + ibufBTBResp <- io.imem.bits.btb.bits @[IBuf.scala 64:21] + node _T_430 = add(io.imem.bits.btb.bits.bridx, nICReady) @[IBuf.scala 65:58] + node _T_431 = tail(_T_430, 1) @[IBuf.scala 65:58] + ibufBTBResp.bridx <= _T_431 @[IBuf.scala 65:27] + skip @[IBuf.scala 63:37] + skip @[IBuf.scala 56:90] + when io.kill : @[IBuf.scala 68:20] + nBufValid <= UInt<1>("h00") @[IBuf.scala 69:17] + skip @[IBuf.scala 68:20] + node _T_434 = add(UInt<2>("h02"), nBufValid) @[IBuf.scala 73:32] + node _T_435 = tail(_T_434, 1) @[IBuf.scala 73:32] + node _T_436 = sub(_T_435, pcWordBits) @[IBuf.scala 73:44] + node _T_437 = asUInt(_T_436) @[IBuf.scala 73:44] + node _T_438 = tail(_T_437, 1) @[IBuf.scala 73:44] + node icShiftAmt = bits(_T_438, 1, 0) @[IBuf.scala 73:57] + node _T_439 = bits(io.imem.bits.data, 15, 0) @[IBuf.scala 74:87] + node _T_440 = cat(_T_439, _T_439) @[Cat.scala 30:58] + node _T_441 = cat(io.imem.bits.data, _T_440) @[Cat.scala 30:58] + node _T_442 = shr(_T_441, 48) @[IBuf.scala 126:58] + node _T_443 = cat(_T_442, _T_442) @[Cat.scala 30:58] + node _T_444 = cat(_T_443, _T_443) @[Cat.scala 30:58] + node _T_445 = cat(_T_444, _T_441) @[Cat.scala 30:58] + node _T_446 = shl(icShiftAmt, 4) @[IBuf.scala 127:19] + node _T_447 = dshl(_T_445, _T_446) @[IBuf.scala 127:10] + node icData = bits(_T_447, 95, 64) @[Package.scala 44:13] + node _T_449 = not(UInt<32>("h00")) @[IBuf.scala 76:17] + node _T_450 = shl(nBufValid, 4) @[IBuf.scala 76:65] + node _T_451 = dshl(_T_449, _T_450) @[IBuf.scala 76:51] + node icMask = bits(_T_451, 31, 0) @[IBuf.scala 76:92] + node _T_452 = and(icData, icMask) @[IBuf.scala 77:21] + node _T_453 = not(icMask) @[IBuf.scala 77:43] + node _T_454 = and(buf.data, _T_453) @[IBuf.scala 77:41] + node inst = or(_T_452, _T_454) @[IBuf.scala 77:30] + node _T_456 = dshl(UInt<1>("h01"), nValid) @[OneHot.scala 47:11] + node _T_458 = sub(_T_456, UInt<1>("h01")) @[IBuf.scala 79:33] + node _T_459 = asUInt(_T_458) @[IBuf.scala 79:33] + node _T_460 = tail(_T_459, 1) @[IBuf.scala 79:33] + node valid = bits(_T_460, 1, 0) @[IBuf.scala 79:37] + node _T_462 = dshl(UInt<1>("h01"), nBufValid) @[OneHot.scala 47:11] + node _T_464 = sub(_T_462, UInt<1>("h01")) @[IBuf.scala 80:37] + node _T_465 = asUInt(_T_464) @[IBuf.scala 80:37] + node bufMask = tail(_T_465, 1) @[IBuf.scala 80:37] + node _T_467 = mux(buf.xcpt_if, bufMask, UInt<1>("h00")) @[IBuf.scala 81:29] + node _T_468 = not(bufMask) @[IBuf.scala 81:89] + node _T_470 = mux(io.imem.bits.xcpt_if, _T_468, UInt<1>("h00")) @[IBuf.scala 81:66] + node _T_471 = or(_T_467, _T_470) @[IBuf.scala 81:61] + node xcpt_if = and(valid, _T_471) @[IBuf.scala 81:23] + node _T_473 = mux(buf.replay, bufMask, UInt<1>("h00")) @[IBuf.scala 82:31] + node _T_474 = not(bufMask) @[IBuf.scala 82:89] + node _T_476 = mux(io.imem.bits.replay, _T_474, UInt<1>("h00")) @[IBuf.scala 82:67] + node _T_477 = or(_T_473, _T_476) @[IBuf.scala 82:62] + node ic_replay = and(valid, _T_477) @[IBuf.scala 82:25] + node _T_479 = dshl(UInt<1>("h01"), ibufBTBResp.bridx) @[OneHot.scala 47:11] + node ibufBTBHitMask = mux(ibufBTBHit, _T_479, UInt<1>("h00")) @[IBuf.scala 83:27] + node _T_482 = eq(io.imem.bits.btb.valid, UInt<1>("h00")) @[IBuf.scala 84:10] + node _T_483 = geq(io.imem.bits.btb.bits.bridx, pcWordBits) @[IBuf.scala 84:65] + node _T_484 = or(_T_482, _T_483) @[IBuf.scala 84:34] + node _T_485 = or(_T_484, reset) @[IBuf.scala 84:9] + node _T_487 = eq(_T_485, UInt<1>("h00")) @[IBuf.scala 84:9] + when _T_487 : @[IBuf.scala 84:9] + printf(clock, UInt<1>(1), "Assertion failed\n at IBuf.scala:84 assert(!io.imem.bits.btb.valid || io.imem.bits.btb.bits.bridx >= pcWordBits)\n") @[IBuf.scala 84:9] + stop(clock, UInt<1>(1), 1) @[IBuf.scala 84:9] + skip @[IBuf.scala 84:9] + node _T_488 = add(io.imem.bits.btb.bits.bridx, nBufValid) @[IBuf.scala 85:87] + node _T_489 = sub(_T_488, pcWordBits) @[IBuf.scala 85:100] + node _T_490 = asUInt(_T_489) @[IBuf.scala 85:100] + node _T_491 = tail(_T_490, 1) @[IBuf.scala 85:100] + node _T_493 = dshl(UInt<1>("h01"), _T_491) @[OneHot.scala 47:11] + node icBTBHitMask = mux(io.imem.bits.btb.valid, _T_493, UInt<1>("h00")) @[IBuf.scala 85:25] + node _T_495 = and(ibufBTBHitMask, bufMask) @[IBuf.scala 86:35] + node _T_496 = not(bufMask) @[IBuf.scala 86:62] + node _T_497 = and(icBTBHitMask, _T_496) @[IBuf.scala 86:60] + node btbHitMask = or(_T_495, _T_497) @[IBuf.scala 86:45] + node _T_498 = and(ibufBTBHitMask, bufMask) @[IBuf.scala 88:38] + node _T_500 = neq(_T_498, UInt<1>("h00")) @[IBuf.scala 88:49] + node _T_501 = mux(_T_500, ibufBTBResp, io.imem.bits.btb.bits) @[IBuf.scala 88:21] + io.btb_resp <- _T_501 @[IBuf.scala 88:15] + node _T_511 = gt(nBufValid, UInt<1>("h00")) @[IBuf.scala 89:26] + node _T_512 = mux(_T_511, buf.pc, io.imem.bits.pc) @[IBuf.scala 89:15] + io.pc <= _T_512 @[IBuf.scala 89:9] + inst RVCExpander of RVCExpander @[IBuf.scala 93:21] + RVCExpander.io is invalid + RVCExpander.clock <= clock + RVCExpander.reset <= reset + RVCExpander.io.in <= inst @[IBuf.scala 94:15] + io.inst[0].bits.inst <- RVCExpander.io.out @[IBuf.scala 95:26] + io.inst[0].bits.raw <= inst @[IBuf.scala 96:25] + node _T_514 = dshr(ic_replay, UInt<1>("h00")) @[IBuf.scala 99:29] + node _T_515 = bits(_T_514, 0, 0) @[IBuf.scala 99:29] + node _T_517 = eq(RVCExpander.io.rvc, UInt<1>("h00")) @[IBuf.scala 99:37] + node _T_518 = dshr(btbHitMask, UInt<1>("h00")) @[IBuf.scala 99:63] + node _T_519 = bits(_T_518, 0, 0) @[IBuf.scala 99:63] + node _T_521 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 99:81] + node _T_522 = tail(_T_521, 1) @[IBuf.scala 99:81] + node _T_523 = dshr(ic_replay, _T_522) @[IBuf.scala 99:79] + node _T_524 = bits(_T_523, 0, 0) @[IBuf.scala 99:79] + node _T_525 = or(_T_519, _T_524) @[IBuf.scala 99:67] + node _T_526 = and(_T_517, _T_525) @[IBuf.scala 99:49] + node _T_527 = or(_T_515, _T_526) @[IBuf.scala 99:33] + node _T_528 = dshr(valid, UInt<1>("h00")) @[IBuf.scala 100:32] + node _T_529 = bits(_T_528, 0, 0) @[IBuf.scala 100:32] + node _T_531 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 100:61] + node _T_532 = tail(_T_531, 1) @[IBuf.scala 100:61] + node _T_533 = dshr(valid, _T_532) @[IBuf.scala 100:59] + node _T_534 = bits(_T_533, 0, 0) @[IBuf.scala 100:59] + node _T_535 = or(RVCExpander.io.rvc, _T_534) @[IBuf.scala 100:51] + node _T_537 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 100:77] + node _T_538 = tail(_T_537, 1) @[IBuf.scala 100:77] + node _T_539 = dshr(xcpt_if, _T_538) @[IBuf.scala 100:75] + node _T_540 = bits(_T_539, 0, 0) @[IBuf.scala 100:75] + node _T_541 = or(_T_535, _T_540) @[IBuf.scala 100:65] + node _T_542 = or(_T_541, _T_527) @[IBuf.scala 100:81] + node _T_543 = and(_T_529, _T_542) @[IBuf.scala 100:36] + io.inst[0].valid <= _T_543 @[IBuf.scala 100:24] + node _T_544 = dshr(xcpt_if, UInt<1>("h00")) @[IBuf.scala 101:37] + node _T_545 = bits(_T_544, 0, 0) @[IBuf.scala 101:37] + io.inst[0].bits.pf0 <= _T_545 @[IBuf.scala 101:27] + node _T_547 = eq(RVCExpander.io.rvc, UInt<1>("h00")) @[IBuf.scala 102:30] + node _T_549 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 102:54] + node _T_550 = tail(_T_549, 1) @[IBuf.scala 102:54] + node _T_551 = dshr(xcpt_if, _T_550) @[IBuf.scala 102:52] + node _T_552 = bits(_T_551, 0, 0) @[IBuf.scala 102:52] + node _T_553 = and(_T_547, _T_552) @[IBuf.scala 102:42] + io.inst[0].bits.pf1 <= _T_553 @[IBuf.scala 102:27] + io.inst[0].bits.replay <= _T_527 @[IBuf.scala 103:30] + node _T_554 = dshr(btbHitMask, UInt<1>("h00")) @[IBuf.scala 104:44] + node _T_555 = bits(_T_554, 0, 0) @[IBuf.scala 104:44] + node _T_557 = eq(RVCExpander.io.rvc, UInt<1>("h00")) @[IBuf.scala 104:52] + node _T_559 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 104:79] + node _T_560 = tail(_T_559, 1) @[IBuf.scala 104:79] + node _T_561 = dshr(btbHitMask, _T_560) @[IBuf.scala 104:77] + node _T_562 = bits(_T_561, 0, 0) @[IBuf.scala 104:77] + node _T_563 = and(_T_557, _T_562) @[IBuf.scala 104:64] + node _T_564 = or(_T_555, _T_563) @[IBuf.scala 104:48] + io.inst[0].bits.btb_hit <= _T_564 @[IBuf.scala 104:31] + io.inst[0].bits.rvc <= RVCExpander.io.rvc @[IBuf.scala 105:27] + node _T_565 = and(io.inst[0].ready, io.inst[0].valid) @[Decoupled.scala 30:37] + when _T_565 : @[IBuf.scala 107:32] + node _T_567 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 107:61] + node _T_568 = tail(_T_567, 1) @[IBuf.scala 107:61] + node _T_570 = add(UInt<1>("h00"), UInt<2>("h02")) @[IBuf.scala 107:66] + node _T_571 = tail(_T_570, 1) @[IBuf.scala 107:66] + node _T_572 = mux(RVCExpander.io.rvc, _T_568, _T_571) @[IBuf.scala 107:47] + nReady <= _T_572 @[IBuf.scala 107:41] + skip @[IBuf.scala 107:32] + node _T_574 = add(UInt<1>("h00"), UInt<1>("h01")) @[IBuf.scala 109:36] + node _T_575 = tail(_T_574, 1) @[IBuf.scala 109:36] + node _T_577 = add(UInt<1>("h00"), UInt<2>("h02")) @[IBuf.scala 109:41] + node _T_578 = tail(_T_577, 1) @[IBuf.scala 109:41] + node _T_579 = mux(RVCExpander.io.rvc, _T_575, _T_578) @[IBuf.scala 109:22] + node _T_580 = shr(inst, 16) @[IBuf.scala 109:70] + node _T_581 = shr(inst, 32) @[IBuf.scala 109:85] + node _T_582 = mux(RVCExpander.io.rvc, _T_580, _T_581) @[IBuf.scala 109:49] + + module CSRFile : + input clock : Clock + input reset : UInt<1> + output io : {flip interrupts : {debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, seip : UInt<1>}, flip hartid : UInt<64>, rw : {flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}, decode : {flip csr : UInt<12>, fp_illegal : UInt<1>, rocc_illegal : UInt<1>, read_illegal : UInt<1>, write_illegal : UInt<1>, write_flush : UInt<1>, system_illegal : UInt<1>}, csr_stall : UInt<1>, eret : UInt<1>, singleStep : UInt<1>, status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, ptbr : {mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, evec : UInt<40>, flip exception : UInt<1>, flip retire : UInt<1>, custom_mrw_csrs : UInt<64>[0], flip cause : UInt<64>, flip pc : UInt<40>, flip badaddr : UInt<40>, fatc : UInt<1>, time : UInt<64>, fcsr_rm : UInt<3>, flip fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, flip rocc_interrupt : UInt<1>, interrupt : UInt<1>, interrupt_cause : UInt<64>, bp : {control : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>}[1], counters : {eventSel : UInt<64>, flip inc : UInt<1>}[0]} + + io is invalid + io is invalid + wire _T_347 : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} @[CSR.scala 194:55] + _T_347 is invalid @[CSR.scala 194:55] + wire _T_377 : UInt<99> + _T_377 is invalid + _T_377 <= UInt<1>("h00") + node _T_378 = bits(_T_377, 0, 0) @[CSR.scala 194:55] + _T_347.uie <= _T_378 @[CSR.scala 194:55] + node _T_379 = bits(_T_377, 1, 1) @[CSR.scala 194:55] + _T_347.sie <= _T_379 @[CSR.scala 194:55] + node _T_380 = bits(_T_377, 2, 2) @[CSR.scala 194:55] + _T_347.hie <= _T_380 @[CSR.scala 194:55] + node _T_381 = bits(_T_377, 3, 3) @[CSR.scala 194:55] + _T_347.mie <= _T_381 @[CSR.scala 194:55] + node _T_382 = bits(_T_377, 4, 4) @[CSR.scala 194:55] + _T_347.upie <= _T_382 @[CSR.scala 194:55] + node _T_383 = bits(_T_377, 5, 5) @[CSR.scala 194:55] + _T_347.spie <= _T_383 @[CSR.scala 194:55] + node _T_384 = bits(_T_377, 6, 6) @[CSR.scala 194:55] + _T_347.hpie <= _T_384 @[CSR.scala 194:55] + node _T_385 = bits(_T_377, 7, 7) @[CSR.scala 194:55] + _T_347.mpie <= _T_385 @[CSR.scala 194:55] + node _T_386 = bits(_T_377, 8, 8) @[CSR.scala 194:55] + _T_347.spp <= _T_386 @[CSR.scala 194:55] + node _T_387 = bits(_T_377, 10, 9) @[CSR.scala 194:55] + _T_347.hpp <= _T_387 @[CSR.scala 194:55] + node _T_388 = bits(_T_377, 12, 11) @[CSR.scala 194:55] + _T_347.mpp <= _T_388 @[CSR.scala 194:55] + node _T_389 = bits(_T_377, 14, 13) @[CSR.scala 194:55] + _T_347.fs <= _T_389 @[CSR.scala 194:55] + node _T_390 = bits(_T_377, 16, 15) @[CSR.scala 194:55] + _T_347.xs <= _T_390 @[CSR.scala 194:55] + node _T_391 = bits(_T_377, 17, 17) @[CSR.scala 194:55] + _T_347.mprv <= _T_391 @[CSR.scala 194:55] + node _T_392 = bits(_T_377, 18, 18) @[CSR.scala 194:55] + _T_347.pum <= _T_392 @[CSR.scala 194:55] + node _T_393 = bits(_T_377, 19, 19) @[CSR.scala 194:55] + _T_347.mxr <= _T_393 @[CSR.scala 194:55] + node _T_394 = bits(_T_377, 20, 20) @[CSR.scala 194:55] + _T_347.tvm <= _T_394 @[CSR.scala 194:55] + node _T_395 = bits(_T_377, 21, 21) @[CSR.scala 194:55] + _T_347.tw <= _T_395 @[CSR.scala 194:55] + node _T_396 = bits(_T_377, 22, 22) @[CSR.scala 194:55] + _T_347.tsr <= _T_396 @[CSR.scala 194:55] + node _T_397 = bits(_T_377, 30, 23) @[CSR.scala 194:55] + _T_347.zero1 <= _T_397 @[CSR.scala 194:55] + node _T_398 = bits(_T_377, 31, 31) @[CSR.scala 194:55] + _T_347.sd_rv32 <= _T_398 @[CSR.scala 194:55] + node _T_399 = bits(_T_377, 33, 32) @[CSR.scala 194:55] + _T_347.uxl <= _T_399 @[CSR.scala 194:55] + node _T_400 = bits(_T_377, 35, 34) @[CSR.scala 194:55] + _T_347.sxl <= _T_400 @[CSR.scala 194:55] + node _T_401 = bits(_T_377, 62, 36) @[CSR.scala 194:55] + _T_347.zero2 <= _T_401 @[CSR.scala 194:55] + node _T_402 = bits(_T_377, 63, 63) @[CSR.scala 194:55] + _T_347.sd <= _T_402 @[CSR.scala 194:55] + node _T_403 = bits(_T_377, 65, 64) @[CSR.scala 194:55] + _T_347.prv <= _T_403 @[CSR.scala 194:55] + node _T_404 = bits(_T_377, 97, 66) @[CSR.scala 194:55] + _T_347.isa <= _T_404 @[CSR.scala 194:55] + node _T_405 = bits(_T_377, 98, 98) @[CSR.scala 194:55] + _T_347.debug <= _T_405 @[CSR.scala 194:55] + wire reset_mstatus : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} + reset_mstatus is invalid + reset_mstatus <- _T_347 + reset_mstatus.mpp <= UInt<2>("h03") @[CSR.scala 195:21] + reset_mstatus.prv <= UInt<2>("h03") @[CSR.scala 196:21] + reg reg_mstatus : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock with : (reset => (reset, reset_mstatus)) @[CSR.scala 197:24] + wire new_prv : UInt + new_prv is invalid + new_prv <= reg_mstatus.prv + node _T_465 = eq(new_prv, UInt<2>("h02")) @[CSR.scala 697:27] + node _T_467 = mux(_T_465, UInt<1>("h00"), new_prv) @[CSR.scala 697:21] + reg_mstatus.prv <= _T_467 @[CSR.scala 200:19] + wire _T_505 : {xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>} @[CSR.scala 202:49] + _T_505 is invalid @[CSR.scala 202:49] + wire _T_524 : UInt<32> + _T_524 is invalid + _T_524 <= UInt<1>("h00") + node _T_525 = bits(_T_524, 1, 0) @[CSR.scala 202:49] + _T_505.prv <= _T_525 @[CSR.scala 202:49] + node _T_526 = bits(_T_524, 2, 2) @[CSR.scala 202:49] + _T_505.step <= _T_526 @[CSR.scala 202:49] + node _T_527 = bits(_T_524, 3, 3) @[CSR.scala 202:49] + _T_505.halt <= _T_527 @[CSR.scala 202:49] + node _T_528 = bits(_T_524, 4, 4) @[CSR.scala 202:49] + _T_505.zero1 <= _T_528 @[CSR.scala 202:49] + node _T_529 = bits(_T_524, 5, 5) @[CSR.scala 202:49] + _T_505.debugint <= _T_529 @[CSR.scala 202:49] + node _T_530 = bits(_T_524, 8, 6) @[CSR.scala 202:49] + _T_505.cause <= _T_530 @[CSR.scala 202:49] + node _T_531 = bits(_T_524, 9, 9) @[CSR.scala 202:49] + _T_505.stoptime <= _T_531 @[CSR.scala 202:49] + node _T_532 = bits(_T_524, 10, 10) @[CSR.scala 202:49] + _T_505.stopcycle <= _T_532 @[CSR.scala 202:49] + node _T_533 = bits(_T_524, 11, 11) @[CSR.scala 202:49] + _T_505.zero2 <= _T_533 @[CSR.scala 202:49] + node _T_534 = bits(_T_524, 12, 12) @[CSR.scala 202:49] + _T_505.ebreaku <= _T_534 @[CSR.scala 202:49] + node _T_535 = bits(_T_524, 13, 13) @[CSR.scala 202:49] + _T_505.ebreaks <= _T_535 @[CSR.scala 202:49] + node _T_536 = bits(_T_524, 14, 14) @[CSR.scala 202:49] + _T_505.ebreakh <= _T_536 @[CSR.scala 202:49] + node _T_537 = bits(_T_524, 15, 15) @[CSR.scala 202:49] + _T_505.ebreakm <= _T_537 @[CSR.scala 202:49] + node _T_538 = bits(_T_524, 27, 16) @[CSR.scala 202:49] + _T_505.zero3 <= _T_538 @[CSR.scala 202:49] + node _T_539 = bits(_T_524, 28, 28) @[CSR.scala 202:49] + _T_505.fullreset <= _T_539 @[CSR.scala 202:49] + node _T_540 = bits(_T_524, 29, 29) @[CSR.scala 202:49] + _T_505.ndreset <= _T_540 @[CSR.scala 202:49] + node _T_541 = bits(_T_524, 31, 30) @[CSR.scala 202:49] + _T_505.xdebugver <= _T_541 @[CSR.scala 202:49] + wire reset_dcsr : {xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>} + reset_dcsr is invalid + reset_dcsr <- _T_505 + reset_dcsr.xdebugver <= UInt<1>("h01") @[CSR.scala 203:24] + reset_dcsr.prv <= UInt<2>("h03") @[CSR.scala 204:18] + reg reg_dcsr : {xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>}, clock with : (reset => (reset, reset_dcsr)) @[CSR.scala 205:21] + wire _T_607 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[CSR.scala 208:43] + _T_607 is invalid @[CSR.scala 208:43] + wire _T_622 : UInt<13> + _T_622 is invalid + _T_622 <= UInt<1>("h00") + node _T_623 = bits(_T_622, 0, 0) @[CSR.scala 208:43] + _T_607.usip <= _T_623 @[CSR.scala 208:43] + node _T_624 = bits(_T_622, 1, 1) @[CSR.scala 208:43] + _T_607.ssip <= _T_624 @[CSR.scala 208:43] + node _T_625 = bits(_T_622, 2, 2) @[CSR.scala 208:43] + _T_607.hsip <= _T_625 @[CSR.scala 208:43] + node _T_626 = bits(_T_622, 3, 3) @[CSR.scala 208:43] + _T_607.msip <= _T_626 @[CSR.scala 208:43] + node _T_627 = bits(_T_622, 4, 4) @[CSR.scala 208:43] + _T_607.utip <= _T_627 @[CSR.scala 208:43] + node _T_628 = bits(_T_622, 5, 5) @[CSR.scala 208:43] + _T_607.stip <= _T_628 @[CSR.scala 208:43] + node _T_629 = bits(_T_622, 6, 6) @[CSR.scala 208:43] + _T_607.htip <= _T_629 @[CSR.scala 208:43] + node _T_630 = bits(_T_622, 7, 7) @[CSR.scala 208:43] + _T_607.mtip <= _T_630 @[CSR.scala 208:43] + node _T_631 = bits(_T_622, 8, 8) @[CSR.scala 208:43] + _T_607.ueip <= _T_631 @[CSR.scala 208:43] + node _T_632 = bits(_T_622, 9, 9) @[CSR.scala 208:43] + _T_607.seip <= _T_632 @[CSR.scala 208:43] + node _T_633 = bits(_T_622, 10, 10) @[CSR.scala 208:43] + _T_607.heip <= _T_633 @[CSR.scala 208:43] + node _T_634 = bits(_T_622, 11, 11) @[CSR.scala 208:43] + _T_607.meip <= _T_634 @[CSR.scala 208:43] + node _T_635 = bits(_T_622, 12, 12) @[CSR.scala 208:43] + _T_607.rocc <= _T_635 @[CSR.scala 208:43] + wire _T_636 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + _T_636 is invalid + _T_636 <- _T_607 + _T_636.ssip <= UInt<1>("h01") @[CSR.scala 209:14] + _T_636.msip <= UInt<1>("h01") @[CSR.scala 210:14] + _T_636.stip <= UInt<1>("h01") @[CSR.scala 211:14] + _T_636.mtip <= UInt<1>("h01") @[CSR.scala 212:14] + _T_636.meip <= UInt<1>("h01") @[CSR.scala 213:14] + _T_636.seip <= UInt<1>("h01") @[CSR.scala 214:14] + _T_636.rocc <= UInt<1>("h00") @[CSR.scala 215:14] + wire _T_657 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + _T_657 is invalid + _T_657 <- _T_636 + _T_657.msip <= UInt<1>("h00") @[CSR.scala 218:14] + _T_657.mtip <= UInt<1>("h00") @[CSR.scala 219:14] + _T_657.meip <= UInt<1>("h00") @[CSR.scala 220:14] + node _T_674 = cat(_T_636.hsip, _T_636.ssip) @[CSR.scala 222:10] + node _T_675 = cat(_T_674, _T_636.usip) @[CSR.scala 222:10] + node _T_676 = cat(_T_636.stip, _T_636.utip) @[CSR.scala 222:10] + node _T_677 = cat(_T_676, _T_636.msip) @[CSR.scala 222:10] + node _T_678 = cat(_T_677, _T_675) @[CSR.scala 222:10] + node _T_679 = cat(_T_636.ueip, _T_636.mtip) @[CSR.scala 222:10] + node _T_680 = cat(_T_679, _T_636.htip) @[CSR.scala 222:10] + node _T_681 = cat(_T_636.heip, _T_636.seip) @[CSR.scala 222:10] + node _T_682 = cat(_T_636.rocc, _T_636.meip) @[CSR.scala 222:10] + node _T_683 = cat(_T_682, _T_681) @[CSR.scala 222:10] + node _T_684 = cat(_T_683, _T_680) @[CSR.scala 222:10] + node supported_interrupts = cat(_T_684, _T_678) @[CSR.scala 222:10] + node _T_685 = cat(_T_657.hsip, _T_657.ssip) @[CSR.scala 222:22] + node _T_686 = cat(_T_685, _T_657.usip) @[CSR.scala 222:22] + node _T_687 = cat(_T_657.stip, _T_657.utip) @[CSR.scala 222:22] + node _T_688 = cat(_T_687, _T_657.msip) @[CSR.scala 222:22] + node _T_689 = cat(_T_688, _T_686) @[CSR.scala 222:22] + node _T_690 = cat(_T_657.ueip, _T_657.mtip) @[CSR.scala 222:22] + node _T_691 = cat(_T_690, _T_657.htip) @[CSR.scala 222:22] + node _T_692 = cat(_T_657.heip, _T_657.seip) @[CSR.scala 222:22] + node _T_693 = cat(_T_657.rocc, _T_657.meip) @[CSR.scala 222:22] + node _T_694 = cat(_T_693, _T_692) @[CSR.scala 222:22] + node _T_695 = cat(_T_694, _T_691) @[CSR.scala 222:22] + node delegable_interrupts = cat(_T_695, _T_689) @[CSR.scala 222:22] + reg reg_debug : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[CSR.scala 232:22] + node effective_prv = cat(reg_debug, reg_mstatus.prv) @[Cat.scala 30:58] + reg reg_dpc : UInt<40>, clock @[CSR.scala 234:20] + reg reg_dscratch : UInt<64>, clock @[CSR.scala 235:25] + reg reg_singleStepped : UInt<1>, clock @[CSR.scala 236:30] + reg reg_tselect : UInt<1>, clock @[CSR.scala 238:24] + reg reg_bp : {control : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>}[2], clock @[CSR.scala 239:19] + reg reg_mie : UInt<64>, clock @[CSR.scala 241:20] + reg reg_mideleg : UInt<64>, clock @[CSR.scala 242:24] + reg reg_medeleg : UInt<64>, clock @[CSR.scala 243:24] + reg reg_mip : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clock @[CSR.scala 244:20] + reg reg_mepc : UInt<40>, clock @[CSR.scala 245:21] + reg reg_mcause : UInt<64>, clock @[CSR.scala 246:23] + reg reg_mbadaddr : UInt<40>, clock @[CSR.scala 247:25] + reg reg_mscratch : UInt<64>, clock @[CSR.scala 248:25] + reg reg_mtvec : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[CSR.scala 251:27] + reg reg_mcounteren : UInt<32>, clock @[CSR.scala 254:27] + reg reg_scounteren : UInt<32>, clock @[CSR.scala 255:27] + reg reg_sepc : UInt<40>, clock @[CSR.scala 258:21] + reg reg_scause : UInt<64>, clock @[CSR.scala 259:23] + reg reg_sbadaddr : UInt<40>, clock @[CSR.scala 260:25] + reg reg_sscratch : UInt<64>, clock @[CSR.scala 261:25] + reg reg_stvec : UInt<39>, clock @[CSR.scala 262:22] + reg reg_sptbr : {mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock @[CSR.scala 263:22] + reg reg_wfi : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[CSR.scala 264:20] + reg reg_fflags : UInt<5>, clock @[CSR.scala 266:23] + reg reg_frm : UInt<3>, clock @[CSR.scala 267:20] + reg _T_931 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Counters.scala 47:37] + node _T_932 = add(_T_931, io.retire) @[Counters.scala 48:33] + _T_931 <= _T_932 @[Counters.scala 49:9] + reg _T_934 : UInt<58>, clock with : (reset => (reset, UInt<58>("h00"))) @[Counters.scala 52:27] + node _T_935 = bits(_T_932, 6, 6) @[Counters.scala 53:20] + when _T_935 : @[Counters.scala 53:34] + node _T_937 = add(_T_934, UInt<1>("h01")) @[Counters.scala 53:43] + node _T_938 = tail(_T_937, 1) @[Counters.scala 53:43] + _T_934 <= _T_938 @[Counters.scala 53:38] + skip @[Counters.scala 53:34] + node _T_939 = cat(_T_934, _T_931) @[Cat.scala 30:58] + reg _T_942 : UInt<6>, clock with : (reset => (reset, UInt<6>("h00"))) @[Counters.scala 47:37] + node _T_943 = add(_T_942, UInt<1>("h01")) @[Counters.scala 48:33] + _T_942 <= _T_943 @[Counters.scala 49:9] + reg _T_945 : UInt<58>, clock with : (reset => (reset, UInt<58>("h00"))) @[Counters.scala 52:27] + node _T_946 = bits(_T_943, 6, 6) @[Counters.scala 53:20] + when _T_946 : @[Counters.scala 53:34] + node _T_948 = add(_T_945, UInt<1>("h01")) @[Counters.scala 53:43] + node _T_949 = tail(_T_948, 1) @[Counters.scala 53:43] + _T_945 <= _T_949 @[Counters.scala 53:38] + skip @[Counters.scala 53:34] + node _T_950 = cat(_T_945, _T_942) @[Cat.scala 30:58] + node _T_953 = eq(reg_mstatus.prv, UInt<1>("h01")) @[CSR.scala 274:71] + node _T_954 = or(UInt<1>("h00"), _T_953) @[CSR.scala 274:52] + node _T_956 = mux(_T_954, UInt<3>("h07"), reg_scounteren) @[CSR.scala 274:38] + node hpm_mask = and(reg_mcounteren, _T_956) @[CSR.scala 274:33] + wire mip : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + mip is invalid + mip <- reg_mip + mip.rocc <= io.rocc_interrupt @[CSR.scala 277:12] + node _T_970 = cat(mip.hsip, mip.ssip) @[CSR.scala 278:22] + node _T_971 = cat(_T_970, mip.usip) @[CSR.scala 278:22] + node _T_972 = cat(mip.stip, mip.utip) @[CSR.scala 278:22] + node _T_973 = cat(_T_972, mip.msip) @[CSR.scala 278:22] + node _T_974 = cat(_T_973, _T_971) @[CSR.scala 278:22] + node _T_975 = cat(mip.ueip, mip.mtip) @[CSR.scala 278:22] + node _T_976 = cat(_T_975, mip.htip) @[CSR.scala 278:22] + node _T_977 = cat(mip.heip, mip.seip) @[CSR.scala 278:22] + node _T_978 = cat(mip.rocc, mip.meip) @[CSR.scala 278:22] + node _T_979 = cat(_T_978, _T_977) @[CSR.scala 278:22] + node _T_980 = cat(_T_979, _T_976) @[CSR.scala 278:22] + node _T_981 = cat(_T_980, _T_974) @[CSR.scala 278:22] + node read_mip = and(_T_981, supported_interrupts) @[CSR.scala 278:29] + node pending_interrupts = and(read_mip, reg_mie) @[CSR.scala 280:37] + node _T_983 = leq(reg_mstatus.prv, UInt<1>("h01")) @[CSR.scala 281:42] + node _T_985 = eq(reg_mstatus.prv, UInt<2>("h03")) @[CSR.scala 281:71] + node _T_986 = and(_T_985, reg_mstatus.mie) @[CSR.scala 281:81] + node _T_987 = or(_T_983, _T_986) @[CSR.scala 281:51] + node _T_988 = not(reg_mideleg) @[CSR.scala 281:123] + node _T_989 = and(pending_interrupts, _T_988) @[CSR.scala 281:121] + node m_interrupts = mux(_T_987, _T_989, UInt<1>("h00")) @[CSR.scala 281:25] + node _T_992 = eq(m_interrupts, UInt<1>("h00")) @[CSR.scala 282:39] + node _T_994 = lt(reg_mstatus.prv, UInt<1>("h01")) @[CSR.scala 282:65] + node _T_996 = eq(reg_mstatus.prv, UInt<1>("h01")) @[CSR.scala 282:93] + node _T_997 = and(_T_996, reg_mstatus.sie) @[CSR.scala 282:103] + node _T_998 = or(_T_994, _T_997) @[CSR.scala 282:73] + node _T_999 = and(_T_992, _T_998) @[CSR.scala 282:45] + node _T_1000 = and(pending_interrupts, reg_mideleg) @[CSR.scala 282:144] + node s_interrupts = mux(_T_999, _T_1000, UInt<1>("h00")) @[CSR.scala 282:25] + node all_interrupts = or(m_interrupts, s_interrupts) @[CSR.scala 283:37] + node _T_1003 = bits(all_interrupts, 0, 0) @[OneHot.scala 39:40] + node _T_1004 = bits(all_interrupts, 1, 1) @[OneHot.scala 39:40] + node _T_1005 = bits(all_interrupts, 2, 2) @[OneHot.scala 39:40] + node _T_1006 = bits(all_interrupts, 3, 3) @[OneHot.scala 39:40] + node _T_1007 = bits(all_interrupts, 4, 4) @[OneHot.scala 39:40] + node _T_1008 = bits(all_interrupts, 5, 5) @[OneHot.scala 39:40] + node _T_1009 = bits(all_interrupts, 6, 6) @[OneHot.scala 39:40] + node _T_1010 = bits(all_interrupts, 7, 7) @[OneHot.scala 39:40] + node _T_1011 = bits(all_interrupts, 8, 8) @[OneHot.scala 39:40] + node _T_1012 = bits(all_interrupts, 9, 9) @[OneHot.scala 39:40] + node _T_1013 = bits(all_interrupts, 10, 10) @[OneHot.scala 39:40] + node _T_1014 = bits(all_interrupts, 11, 11) @[OneHot.scala 39:40] + node _T_1015 = bits(all_interrupts, 12, 12) @[OneHot.scala 39:40] + node _T_1016 = bits(all_interrupts, 13, 13) @[OneHot.scala 39:40] + node _T_1017 = bits(all_interrupts, 14, 14) @[OneHot.scala 39:40] + node _T_1018 = bits(all_interrupts, 15, 15) @[OneHot.scala 39:40] + node _T_1019 = bits(all_interrupts, 16, 16) @[OneHot.scala 39:40] + node _T_1020 = bits(all_interrupts, 17, 17) @[OneHot.scala 39:40] + node _T_1021 = bits(all_interrupts, 18, 18) @[OneHot.scala 39:40] + node _T_1022 = bits(all_interrupts, 19, 19) @[OneHot.scala 39:40] + node _T_1023 = bits(all_interrupts, 20, 20) @[OneHot.scala 39:40] + node _T_1024 = bits(all_interrupts, 21, 21) @[OneHot.scala 39:40] + node _T_1025 = bits(all_interrupts, 22, 22) @[OneHot.scala 39:40] + node _T_1026 = bits(all_interrupts, 23, 23) @[OneHot.scala 39:40] + node _T_1027 = bits(all_interrupts, 24, 24) @[OneHot.scala 39:40] + node _T_1028 = bits(all_interrupts, 25, 25) @[OneHot.scala 39:40] + node _T_1029 = bits(all_interrupts, 26, 26) @[OneHot.scala 39:40] + node _T_1030 = bits(all_interrupts, 27, 27) @[OneHot.scala 39:40] + node _T_1031 = bits(all_interrupts, 28, 28) @[OneHot.scala 39:40] + node _T_1032 = bits(all_interrupts, 29, 29) @[OneHot.scala 39:40] + node _T_1033 = bits(all_interrupts, 30, 30) @[OneHot.scala 39:40] + node _T_1034 = bits(all_interrupts, 31, 31) @[OneHot.scala 39:40] + node _T_1035 = bits(all_interrupts, 32, 32) @[OneHot.scala 39:40] + node _T_1036 = bits(all_interrupts, 33, 33) @[OneHot.scala 39:40] + node _T_1037 = bits(all_interrupts, 34, 34) @[OneHot.scala 39:40] + node _T_1038 = bits(all_interrupts, 35, 35) @[OneHot.scala 39:40] + node _T_1039 = bits(all_interrupts, 36, 36) @[OneHot.scala 39:40] + node _T_1040 = bits(all_interrupts, 37, 37) @[OneHot.scala 39:40] + node _T_1041 = bits(all_interrupts, 38, 38) @[OneHot.scala 39:40] + node _T_1042 = bits(all_interrupts, 39, 39) @[OneHot.scala 39:40] + node _T_1043 = bits(all_interrupts, 40, 40) @[OneHot.scala 39:40] + node _T_1044 = bits(all_interrupts, 41, 41) @[OneHot.scala 39:40] + node _T_1045 = bits(all_interrupts, 42, 42) @[OneHot.scala 39:40] + node _T_1046 = bits(all_interrupts, 43, 43) @[OneHot.scala 39:40] + node _T_1047 = bits(all_interrupts, 44, 44) @[OneHot.scala 39:40] + node _T_1048 = bits(all_interrupts, 45, 45) @[OneHot.scala 39:40] + node _T_1049 = bits(all_interrupts, 46, 46) @[OneHot.scala 39:40] + node _T_1050 = bits(all_interrupts, 47, 47) @[OneHot.scala 39:40] + node _T_1051 = bits(all_interrupts, 48, 48) @[OneHot.scala 39:40] + node _T_1052 = bits(all_interrupts, 49, 49) @[OneHot.scala 39:40] + node _T_1053 = bits(all_interrupts, 50, 50) @[OneHot.scala 39:40] + node _T_1054 = bits(all_interrupts, 51, 51) @[OneHot.scala 39:40] + node _T_1055 = bits(all_interrupts, 52, 52) @[OneHot.scala 39:40] + node _T_1056 = bits(all_interrupts, 53, 53) @[OneHot.scala 39:40] + node _T_1057 = bits(all_interrupts, 54, 54) @[OneHot.scala 39:40] + node _T_1058 = bits(all_interrupts, 55, 55) @[OneHot.scala 39:40] + node _T_1059 = bits(all_interrupts, 56, 56) @[OneHot.scala 39:40] + node _T_1060 = bits(all_interrupts, 57, 57) @[OneHot.scala 39:40] + node _T_1061 = bits(all_interrupts, 58, 58) @[OneHot.scala 39:40] + node _T_1062 = bits(all_interrupts, 59, 59) @[OneHot.scala 39:40] + node _T_1063 = bits(all_interrupts, 60, 60) @[OneHot.scala 39:40] + node _T_1064 = bits(all_interrupts, 61, 61) @[OneHot.scala 39:40] + node _T_1065 = bits(all_interrupts, 62, 62) @[OneHot.scala 39:40] + node _T_1066 = bits(all_interrupts, 63, 63) @[OneHot.scala 39:40] + node _T_1131 = mux(_T_1065, UInt<6>("h03e"), UInt<6>("h03f")) @[Mux.scala 31:69] + node _T_1132 = mux(_T_1064, UInt<6>("h03d"), _T_1131) @[Mux.scala 31:69] + node _T_1133 = mux(_T_1063, UInt<6>("h03c"), _T_1132) @[Mux.scala 31:69] + node _T_1134 = mux(_T_1062, UInt<6>("h03b"), _T_1133) @[Mux.scala 31:69] + node _T_1135 = mux(_T_1061, UInt<6>("h03a"), _T_1134) @[Mux.scala 31:69] + node _T_1136 = mux(_T_1060, UInt<6>("h039"), _T_1135) @[Mux.scala 31:69] + node _T_1137 = mux(_T_1059, UInt<6>("h038"), _T_1136) @[Mux.scala 31:69] + node _T_1138 = mux(_T_1058, UInt<6>("h037"), _T_1137) @[Mux.scala 31:69] + node _T_1139 = mux(_T_1057, UInt<6>("h036"), _T_1138) @[Mux.scala 31:69] + node _T_1140 = mux(_T_1056, UInt<6>("h035"), _T_1139) @[Mux.scala 31:69] + node _T_1141 = mux(_T_1055, UInt<6>("h034"), _T_1140) @[Mux.scala 31:69] + node _T_1142 = mux(_T_1054, UInt<6>("h033"), _T_1141) @[Mux.scala 31:69] + node _T_1143 = mux(_T_1053, UInt<6>("h032"), _T_1142) @[Mux.scala 31:69] + node _T_1144 = mux(_T_1052, UInt<6>("h031"), _T_1143) @[Mux.scala 31:69] + node _T_1145 = mux(_T_1051, UInt<6>("h030"), _T_1144) @[Mux.scala 31:69] + node _T_1146 = mux(_T_1050, UInt<6>("h02f"), _T_1145) @[Mux.scala 31:69] + node _T_1147 = mux(_T_1049, UInt<6>("h02e"), _T_1146) @[Mux.scala 31:69] + node _T_1148 = mux(_T_1048, UInt<6>("h02d"), _T_1147) @[Mux.scala 31:69] + node _T_1149 = mux(_T_1047, UInt<6>("h02c"), _T_1148) @[Mux.scala 31:69] + node _T_1150 = mux(_T_1046, UInt<6>("h02b"), _T_1149) @[Mux.scala 31:69] + node _T_1151 = mux(_T_1045, UInt<6>("h02a"), _T_1150) @[Mux.scala 31:69] + node _T_1152 = mux(_T_1044, UInt<6>("h029"), _T_1151) @[Mux.scala 31:69] + node _T_1153 = mux(_T_1043, UInt<6>("h028"), _T_1152) @[Mux.scala 31:69] + node _T_1154 = mux(_T_1042, UInt<6>("h027"), _T_1153) @[Mux.scala 31:69] + node _T_1155 = mux(_T_1041, UInt<6>("h026"), _T_1154) @[Mux.scala 31:69] + node _T_1156 = mux(_T_1040, UInt<6>("h025"), _T_1155) @[Mux.scala 31:69] + node _T_1157 = mux(_T_1039, UInt<6>("h024"), _T_1156) @[Mux.scala 31:69] + node _T_1158 = mux(_T_1038, UInt<6>("h023"), _T_1157) @[Mux.scala 31:69] + node _T_1159 = mux(_T_1037, UInt<6>("h022"), _T_1158) @[Mux.scala 31:69] + node _T_1160 = mux(_T_1036, UInt<6>("h021"), _T_1159) @[Mux.scala 31:69] + node _T_1161 = mux(_T_1035, UInt<6>("h020"), _T_1160) @[Mux.scala 31:69] + node _T_1162 = mux(_T_1034, UInt<5>("h01f"), _T_1161) @[Mux.scala 31:69] + node _T_1163 = mux(_T_1033, UInt<5>("h01e"), _T_1162) @[Mux.scala 31:69] + node _T_1164 = mux(_T_1032, UInt<5>("h01d"), _T_1163) @[Mux.scala 31:69] + node _T_1165 = mux(_T_1031, UInt<5>("h01c"), _T_1164) @[Mux.scala 31:69] + node _T_1166 = mux(_T_1030, UInt<5>("h01b"), _T_1165) @[Mux.scala 31:69] + node _T_1167 = mux(_T_1029, UInt<5>("h01a"), _T_1166) @[Mux.scala 31:69] + node _T_1168 = mux(_T_1028, UInt<5>("h019"), _T_1167) @[Mux.scala 31:69] + node _T_1169 = mux(_T_1027, UInt<5>("h018"), _T_1168) @[Mux.scala 31:69] + node _T_1170 = mux(_T_1026, UInt<5>("h017"), _T_1169) @[Mux.scala 31:69] + node _T_1171 = mux(_T_1025, UInt<5>("h016"), _T_1170) @[Mux.scala 31:69] + node _T_1172 = mux(_T_1024, UInt<5>("h015"), _T_1171) @[Mux.scala 31:69] + node _T_1173 = mux(_T_1023, UInt<5>("h014"), _T_1172) @[Mux.scala 31:69] + node _T_1174 = mux(_T_1022, UInt<5>("h013"), _T_1173) @[Mux.scala 31:69] + node _T_1175 = mux(_T_1021, UInt<5>("h012"), _T_1174) @[Mux.scala 31:69] + node _T_1176 = mux(_T_1020, UInt<5>("h011"), _T_1175) @[Mux.scala 31:69] + node _T_1177 = mux(_T_1019, UInt<5>("h010"), _T_1176) @[Mux.scala 31:69] + node _T_1178 = mux(_T_1018, UInt<4>("h0f"), _T_1177) @[Mux.scala 31:69] + node _T_1179 = mux(_T_1017, UInt<4>("h0e"), _T_1178) @[Mux.scala 31:69] + node _T_1180 = mux(_T_1016, UInt<4>("h0d"), _T_1179) @[Mux.scala 31:69] + node _T_1181 = mux(_T_1015, UInt<4>("h0c"), _T_1180) @[Mux.scala 31:69] + node _T_1182 = mux(_T_1014, UInt<4>("h0b"), _T_1181) @[Mux.scala 31:69] + node _T_1183 = mux(_T_1013, UInt<4>("h0a"), _T_1182) @[Mux.scala 31:69] + node _T_1184 = mux(_T_1012, UInt<4>("h09"), _T_1183) @[Mux.scala 31:69] + node _T_1185 = mux(_T_1011, UInt<4>("h08"), _T_1184) @[Mux.scala 31:69] + node _T_1186 = mux(_T_1010, UInt<3>("h07"), _T_1185) @[Mux.scala 31:69] + node _T_1187 = mux(_T_1009, UInt<3>("h06"), _T_1186) @[Mux.scala 31:69] + node _T_1188 = mux(_T_1008, UInt<3>("h05"), _T_1187) @[Mux.scala 31:69] + node _T_1189 = mux(_T_1007, UInt<3>("h04"), _T_1188) @[Mux.scala 31:69] + node _T_1190 = mux(_T_1006, UInt<2>("h03"), _T_1189) @[Mux.scala 31:69] + node _T_1191 = mux(_T_1005, UInt<2>("h02"), _T_1190) @[Mux.scala 31:69] + node _T_1192 = mux(_T_1004, UInt<1>("h01"), _T_1191) @[Mux.scala 31:69] + node _T_1193 = mux(_T_1003, UInt<1>("h00"), _T_1192) @[Mux.scala 31:69] + node _T_1194 = add(UInt<64>("h08000000000000000"), _T_1193) @[CSR.scala 285:43] + node interruptCause = tail(_T_1194, 1) @[CSR.scala 285:43] + node _T_1196 = neq(all_interrupts, UInt<1>("h00")) @[CSR.scala 286:34] + node _T_1198 = eq(reg_debug, UInt<1>("h00")) @[CSR.scala 286:41] + node _T_1199 = and(_T_1196, _T_1198) @[CSR.scala 286:38] + node _T_1201 = eq(io.singleStep, UInt<1>("h00")) @[CSR.scala 286:55] + node _T_1202 = and(_T_1199, _T_1201) @[CSR.scala 286:52] + node _T_1203 = or(_T_1202, reg_singleStepped) @[CSR.scala 286:70] + io.interrupt <= _T_1203 @[CSR.scala 286:16] + io.interrupt_cause <= interruptCause @[CSR.scala 287:22] + io.bp[0] <- reg_bp[0] @[CSR.scala 288:9] + node _T_1205 = and(UInt<1>("h01"), reg_dcsr.debugint) @[CSR.scala 291:26] + node _T_1207 = eq(reg_debug, UInt<1>("h00")) @[CSR.scala 291:50] + node _T_1208 = and(_T_1205, _T_1207) @[CSR.scala 291:47] + when _T_1208 : @[CSR.scala 291:62] + io.interrupt <= UInt<1>("h01") @[CSR.scala 292:18] + node _T_1226 = add(UInt<64>("h08000000000000000"), UInt<4>("h0d")) @[CSR.scala 293:46] + node _T_1227 = tail(_T_1226, 1) @[CSR.scala 293:46] + io.interrupt_cause <= _T_1227 @[CSR.scala 293:24] + skip @[CSR.scala 291:62] + reg reg_misa : UInt, clock with : (reset => (reset, UInt<64>("h0800000000014112d"))) @[CSR.scala 307:21] + node _T_1229 = cat(io.status.hie, io.status.sie) @[CSR.scala 308:38] + node _T_1230 = cat(_T_1229, io.status.uie) @[CSR.scala 308:38] + node _T_1231 = cat(io.status.upie, io.status.mie) @[CSR.scala 308:38] + node _T_1232 = cat(io.status.hpie, io.status.spie) @[CSR.scala 308:38] + node _T_1233 = cat(_T_1232, _T_1231) @[CSR.scala 308:38] + node _T_1234 = cat(_T_1233, _T_1230) @[CSR.scala 308:38] + node _T_1235 = cat(io.status.hpp, io.status.spp) @[CSR.scala 308:38] + node _T_1236 = cat(_T_1235, io.status.mpie) @[CSR.scala 308:38] + node _T_1237 = cat(io.status.fs, io.status.mpp) @[CSR.scala 308:38] + node _T_1238 = cat(io.status.mprv, io.status.xs) @[CSR.scala 308:38] + node _T_1239 = cat(_T_1238, _T_1237) @[CSR.scala 308:38] + node _T_1240 = cat(_T_1239, _T_1236) @[CSR.scala 308:38] + node _T_1241 = cat(_T_1240, _T_1234) @[CSR.scala 308:38] + node _T_1242 = cat(io.status.tvm, io.status.mxr) @[CSR.scala 308:38] + node _T_1243 = cat(_T_1242, io.status.pum) @[CSR.scala 308:38] + node _T_1244 = cat(io.status.tsr, io.status.tw) @[CSR.scala 308:38] + node _T_1245 = cat(io.status.sd_rv32, io.status.zero1) @[CSR.scala 308:38] + node _T_1246 = cat(_T_1245, _T_1244) @[CSR.scala 308:38] + node _T_1247 = cat(_T_1246, _T_1243) @[CSR.scala 308:38] + node _T_1248 = cat(io.status.zero2, io.status.sxl) @[CSR.scala 308:38] + node _T_1249 = cat(_T_1248, io.status.uxl) @[CSR.scala 308:38] + node _T_1250 = cat(io.status.prv, io.status.sd) @[CSR.scala 308:38] + node _T_1251 = cat(io.status.debug, io.status.isa) @[CSR.scala 308:38] + node _T_1252 = cat(_T_1251, _T_1250) @[CSR.scala 308:38] + node _T_1253 = cat(_T_1252, _T_1249) @[CSR.scala 308:38] + node _T_1254 = cat(_T_1253, _T_1247) @[CSR.scala 308:38] + node _T_1255 = cat(_T_1254, _T_1241) @[CSR.scala 308:38] + node read_mstatus = bits(_T_1255, 63, 0) @[CSR.scala 308:40] + node _T_1291 = cat(reg_bp[reg_tselect].control.x, reg_bp[reg_tselect].control.w) @[CSR.scala 312:48] + node _T_1292 = cat(_T_1291, reg_bp[reg_tselect].control.r) @[CSR.scala 312:48] + node _T_1293 = cat(reg_bp[reg_tselect].control.s, reg_bp[reg_tselect].control.u) @[CSR.scala 312:48] + node _T_1294 = cat(reg_bp[reg_tselect].control.m, reg_bp[reg_tselect].control.h) @[CSR.scala 312:48] + node _T_1295 = cat(_T_1294, _T_1293) @[CSR.scala 312:48] + node _T_1296 = cat(_T_1295, _T_1292) @[CSR.scala 312:48] + node _T_1297 = cat(reg_bp[reg_tselect].control.zero, reg_bp[reg_tselect].control.tmatch) @[CSR.scala 312:48] + node _T_1298 = cat(reg_bp[reg_tselect].control.action, reg_bp[reg_tselect].control.chain) @[CSR.scala 312:48] + node _T_1299 = cat(_T_1298, _T_1297) @[CSR.scala 312:48] + node _T_1300 = cat(reg_bp[reg_tselect].control.maskmax, reg_bp[reg_tselect].control.reserved) @[CSR.scala 312:48] + node _T_1301 = cat(reg_bp[reg_tselect].control.ttype, reg_bp[reg_tselect].control.dmode) @[CSR.scala 312:48] + node _T_1302 = cat(_T_1301, _T_1300) @[CSR.scala 312:48] + node _T_1303 = cat(_T_1302, _T_1299) @[CSR.scala 312:48] + node _T_1304 = cat(_T_1303, _T_1296) @[CSR.scala 312:48] + node _T_1340 = bits(reg_bp[reg_tselect].address, 38, 38) @[Package.scala 40:38] + node _T_1341 = bits(_T_1340, 0, 0) @[Bitwise.scala 71:15] + node _T_1344 = mux(_T_1341, UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 71:12] + node _T_1345 = cat(_T_1344, reg_bp[reg_tselect].address) @[Cat.scala 30:58] + node _T_1349 = bits(reg_mepc, 39, 39) @[Package.scala 40:38] + node _T_1350 = bits(_T_1349, 0, 0) @[Bitwise.scala 71:15] + node _T_1353 = mux(_T_1350, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 71:12] + node _T_1354 = cat(_T_1353, reg_mepc) @[Cat.scala 30:58] + node _T_1355 = bits(reg_mbadaddr, 39, 39) @[Package.scala 40:38] + node _T_1356 = bits(_T_1355, 0, 0) @[Bitwise.scala 71:15] + node _T_1359 = mux(_T_1356, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 71:12] + node _T_1360 = cat(_T_1359, reg_mbadaddr) @[Cat.scala 30:58] + node _T_1361 = cat(reg_dcsr.step, reg_dcsr.prv) @[CSR.scala 333:27] + node _T_1362 = cat(reg_dcsr.zero1, reg_dcsr.halt) @[CSR.scala 333:27] + node _T_1363 = cat(_T_1362, _T_1361) @[CSR.scala 333:27] + node _T_1364 = cat(reg_dcsr.cause, reg_dcsr.debugint) @[CSR.scala 333:27] + node _T_1365 = cat(reg_dcsr.stopcycle, reg_dcsr.stoptime) @[CSR.scala 333:27] + node _T_1366 = cat(_T_1365, _T_1364) @[CSR.scala 333:27] + node _T_1367 = cat(_T_1366, _T_1363) @[CSR.scala 333:27] + node _T_1368 = cat(reg_dcsr.ebreaku, reg_dcsr.zero2) @[CSR.scala 333:27] + node _T_1369 = cat(reg_dcsr.ebreakh, reg_dcsr.ebreaks) @[CSR.scala 333:27] + node _T_1370 = cat(_T_1369, _T_1368) @[CSR.scala 333:27] + node _T_1371 = cat(reg_dcsr.zero3, reg_dcsr.ebreakm) @[CSR.scala 333:27] + node _T_1372 = cat(reg_dcsr.xdebugver, reg_dcsr.ndreset) @[CSR.scala 333:27] + node _T_1373 = cat(_T_1372, reg_dcsr.fullreset) @[CSR.scala 333:27] + node _T_1374 = cat(_T_1373, _T_1371) @[CSR.scala 333:27] + node _T_1375 = cat(_T_1374, _T_1370) @[CSR.scala 333:27] + node _T_1376 = cat(_T_1375, _T_1367) @[CSR.scala 333:27] + node _T_1377 = cat(reg_frm, reg_fflags) @[Cat.scala 30:58] + node _T_1380 = and(reg_mie, reg_mideleg) @[CSR.scala 360:28] + node _T_1381 = and(read_mip, reg_mideleg) @[CSR.scala 361:29] + wire _T_1382 : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} + _T_1382 is invalid + _T_1382 <- io.status + _T_1382.mprv <= UInt<1>("h00") @[CSR.scala 363:23] + _T_1382.mpp <= UInt<1>("h00") @[CSR.scala 364:22] + _T_1382.hpp <= UInt<1>("h00") @[CSR.scala 365:22] + _T_1382.mpie <= UInt<1>("h00") @[CSR.scala 366:23] + _T_1382.hpie <= UInt<1>("h00") @[CSR.scala 367:23] + _T_1382.mie <= UInt<1>("h00") @[CSR.scala 368:22] + _T_1382.hie <= UInt<1>("h00") @[CSR.scala 369:22] + node _T_1418 = cat(_T_1382.hie, _T_1382.sie) @[CSR.scala 371:57] + node _T_1419 = cat(_T_1418, _T_1382.uie) @[CSR.scala 371:57] + node _T_1420 = cat(_T_1382.upie, _T_1382.mie) @[CSR.scala 371:57] + node _T_1421 = cat(_T_1382.hpie, _T_1382.spie) @[CSR.scala 371:57] + node _T_1422 = cat(_T_1421, _T_1420) @[CSR.scala 371:57] + node _T_1423 = cat(_T_1422, _T_1419) @[CSR.scala 371:57] + node _T_1424 = cat(_T_1382.hpp, _T_1382.spp) @[CSR.scala 371:57] + node _T_1425 = cat(_T_1424, _T_1382.mpie) @[CSR.scala 371:57] + node _T_1426 = cat(_T_1382.fs, _T_1382.mpp) @[CSR.scala 371:57] + node _T_1427 = cat(_T_1382.mprv, _T_1382.xs) @[CSR.scala 371:57] + node _T_1428 = cat(_T_1427, _T_1426) @[CSR.scala 371:57] + node _T_1429 = cat(_T_1428, _T_1425) @[CSR.scala 371:57] + node _T_1430 = cat(_T_1429, _T_1423) @[CSR.scala 371:57] + node _T_1431 = cat(_T_1382.tvm, _T_1382.mxr) @[CSR.scala 371:57] + node _T_1432 = cat(_T_1431, _T_1382.pum) @[CSR.scala 371:57] + node _T_1433 = cat(_T_1382.tsr, _T_1382.tw) @[CSR.scala 371:57] + node _T_1434 = cat(_T_1382.sd_rv32, _T_1382.zero1) @[CSR.scala 371:57] + node _T_1435 = cat(_T_1434, _T_1433) @[CSR.scala 371:57] + node _T_1436 = cat(_T_1435, _T_1432) @[CSR.scala 371:57] + node _T_1437 = cat(_T_1382.zero2, _T_1382.sxl) @[CSR.scala 371:57] + node _T_1438 = cat(_T_1437, _T_1382.uxl) @[CSR.scala 371:57] + node _T_1439 = cat(_T_1382.prv, _T_1382.sd) @[CSR.scala 371:57] + node _T_1440 = cat(_T_1382.debug, _T_1382.isa) @[CSR.scala 371:57] + node _T_1441 = cat(_T_1440, _T_1439) @[CSR.scala 371:57] + node _T_1442 = cat(_T_1441, _T_1438) @[CSR.scala 371:57] + node _T_1443 = cat(_T_1442, _T_1436) @[CSR.scala 371:57] + node _T_1444 = cat(_T_1443, _T_1430) @[CSR.scala 371:57] + node _T_1445 = bits(_T_1444, 63, 0) @[CSR.scala 371:60] + node _T_1446 = bits(reg_sbadaddr, 39, 39) @[Package.scala 40:38] + node _T_1447 = bits(_T_1446, 0, 0) @[Bitwise.scala 71:15] + node _T_1450 = mux(_T_1447, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 71:12] + node _T_1451 = cat(_T_1450, reg_sbadaddr) @[Cat.scala 30:58] + node _T_1452 = cat(reg_sptbr.mode, reg_sptbr.asid) @[CSR.scala 377:45] + node _T_1453 = cat(_T_1452, reg_sptbr.ppn) @[CSR.scala 377:45] + node _T_1454 = bits(reg_sepc, 39, 39) @[Package.scala 40:38] + node _T_1455 = bits(_T_1454, 0, 0) @[Bitwise.scala 71:15] + node _T_1458 = mux(_T_1455, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 71:12] + node _T_1459 = cat(_T_1458, reg_sepc) @[Cat.scala 30:58] + node _T_1460 = bits(reg_stvec, 38, 38) @[Package.scala 40:38] + node _T_1461 = bits(_T_1460, 0, 0) @[Bitwise.scala 71:15] + node _T_1464 = mux(_T_1461, UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 71:12] + node _T_1465 = cat(_T_1464, reg_stvec) @[Cat.scala 30:58] + node _T_1467 = eq(io.rw.addr, UInt<11>("h07a0")) @[CSR.scala 405:73] + node _T_1469 = eq(io.rw.addr, UInt<11>("h07a1")) @[CSR.scala 405:73] + node _T_1471 = eq(io.rw.addr, UInt<11>("h07a2")) @[CSR.scala 405:73] + node _T_1473 = eq(io.rw.addr, UInt<12>("h0f13")) @[CSR.scala 405:73] + node _T_1475 = eq(io.rw.addr, UInt<12>("h0f12")) @[CSR.scala 405:73] + node _T_1477 = eq(io.rw.addr, UInt<12>("h0f11")) @[CSR.scala 405:73] + node _T_1479 = eq(io.rw.addr, UInt<12>("h0b00")) @[CSR.scala 405:73] + node _T_1481 = eq(io.rw.addr, UInt<12>("h0b02")) @[CSR.scala 405:73] + node _T_1483 = eq(io.rw.addr, UInt<10>("h0301")) @[CSR.scala 405:73] + node _T_1485 = eq(io.rw.addr, UInt<10>("h0300")) @[CSR.scala 405:73] + node _T_1487 = eq(io.rw.addr, UInt<10>("h0305")) @[CSR.scala 405:73] + node _T_1489 = eq(io.rw.addr, UInt<10>("h0344")) @[CSR.scala 405:73] + node _T_1491 = eq(io.rw.addr, UInt<10>("h0304")) @[CSR.scala 405:73] + node _T_1493 = eq(io.rw.addr, UInt<10>("h0303")) @[CSR.scala 405:73] + node _T_1495 = eq(io.rw.addr, UInt<10>("h0302")) @[CSR.scala 405:73] + node _T_1497 = eq(io.rw.addr, UInt<10>("h0340")) @[CSR.scala 405:73] + node _T_1499 = eq(io.rw.addr, UInt<10>("h0341")) @[CSR.scala 405:73] + node _T_1501 = eq(io.rw.addr, UInt<10>("h0343")) @[CSR.scala 405:73] + node _T_1503 = eq(io.rw.addr, UInt<10>("h0342")) @[CSR.scala 405:73] + node _T_1505 = eq(io.rw.addr, UInt<12>("h0f14")) @[CSR.scala 405:73] + node _T_1507 = eq(io.rw.addr, UInt<11>("h07b0")) @[CSR.scala 405:73] + node _T_1509 = eq(io.rw.addr, UInt<11>("h07b1")) @[CSR.scala 405:73] + node _T_1511 = eq(io.rw.addr, UInt<11>("h07b2")) @[CSR.scala 405:73] + node _T_1513 = eq(io.rw.addr, UInt<1>("h01")) @[CSR.scala 405:73] + node _T_1515 = eq(io.rw.addr, UInt<2>("h02")) @[CSR.scala 405:73] + node _T_1517 = eq(io.rw.addr, UInt<2>("h03")) @[CSR.scala 405:73] + node _T_1519 = eq(io.rw.addr, UInt<10>("h0323")) @[CSR.scala 405:73] + node _T_1521 = eq(io.rw.addr, UInt<12>("h0b03")) @[CSR.scala 405:73] + node _T_1523 = eq(io.rw.addr, UInt<12>("h0c03")) @[CSR.scala 405:73] + node _T_1525 = eq(io.rw.addr, UInt<10>("h0324")) @[CSR.scala 405:73] + node _T_1527 = eq(io.rw.addr, UInt<12>("h0b04")) @[CSR.scala 405:73] + node _T_1529 = eq(io.rw.addr, UInt<12>("h0c04")) @[CSR.scala 405:73] + node _T_1531 = eq(io.rw.addr, UInt<10>("h0325")) @[CSR.scala 405:73] + node _T_1533 = eq(io.rw.addr, UInt<12>("h0b05")) @[CSR.scala 405:73] + node _T_1535 = eq(io.rw.addr, UInt<12>("h0c05")) @[CSR.scala 405:73] + node _T_1537 = eq(io.rw.addr, UInt<10>("h0326")) @[CSR.scala 405:73] + node _T_1539 = eq(io.rw.addr, UInt<12>("h0b06")) @[CSR.scala 405:73] + node _T_1541 = eq(io.rw.addr, UInt<12>("h0c06")) @[CSR.scala 405:73] + node _T_1543 = eq(io.rw.addr, UInt<10>("h0327")) @[CSR.scala 405:73] + node _T_1545 = eq(io.rw.addr, UInt<12>("h0b07")) @[CSR.scala 405:73] + node _T_1547 = eq(io.rw.addr, UInt<12>("h0c07")) @[CSR.scala 405:73] + node _T_1549 = eq(io.rw.addr, UInt<10>("h0328")) @[CSR.scala 405:73] + node _T_1551 = eq(io.rw.addr, UInt<12>("h0b08")) @[CSR.scala 405:73] + node _T_1553 = eq(io.rw.addr, UInt<12>("h0c08")) @[CSR.scala 405:73] + node _T_1555 = eq(io.rw.addr, UInt<10>("h0329")) @[CSR.scala 405:73] + node _T_1557 = eq(io.rw.addr, UInt<12>("h0b09")) @[CSR.scala 405:73] + node _T_1559 = eq(io.rw.addr, UInt<12>("h0c09")) @[CSR.scala 405:73] + node _T_1561 = eq(io.rw.addr, UInt<10>("h032a")) @[CSR.scala 405:73] + node _T_1563 = eq(io.rw.addr, UInt<12>("h0b0a")) @[CSR.scala 405:73] + node _T_1565 = eq(io.rw.addr, UInt<12>("h0c0a")) @[CSR.scala 405:73] + node _T_1567 = eq(io.rw.addr, UInt<10>("h032b")) @[CSR.scala 405:73] + node _T_1569 = eq(io.rw.addr, UInt<12>("h0b0b")) @[CSR.scala 405:73] + node _T_1571 = eq(io.rw.addr, UInt<12>("h0c0b")) @[CSR.scala 405:73] + node _T_1573 = eq(io.rw.addr, UInt<10>("h032c")) @[CSR.scala 405:73] + node _T_1575 = eq(io.rw.addr, UInt<12>("h0b0c")) @[CSR.scala 405:73] + node _T_1577 = eq(io.rw.addr, UInt<12>("h0c0c")) @[CSR.scala 405:73] + node _T_1579 = eq(io.rw.addr, UInt<10>("h032d")) @[CSR.scala 405:73] + node _T_1581 = eq(io.rw.addr, UInt<12>("h0b0d")) @[CSR.scala 405:73] + node _T_1583 = eq(io.rw.addr, UInt<12>("h0c0d")) @[CSR.scala 405:73] + node _T_1585 = eq(io.rw.addr, UInt<10>("h032e")) @[CSR.scala 405:73] + node _T_1587 = eq(io.rw.addr, UInt<12>("h0b0e")) @[CSR.scala 405:73] + node _T_1589 = eq(io.rw.addr, UInt<12>("h0c0e")) @[CSR.scala 405:73] + node _T_1591 = eq(io.rw.addr, UInt<10>("h032f")) @[CSR.scala 405:73] + node _T_1593 = eq(io.rw.addr, UInt<12>("h0b0f")) @[CSR.scala 405:73] + node _T_1595 = eq(io.rw.addr, UInt<12>("h0c0f")) @[CSR.scala 405:73] + node _T_1597 = eq(io.rw.addr, UInt<10>("h0330")) @[CSR.scala 405:73] + node _T_1599 = eq(io.rw.addr, UInt<12>("h0b10")) @[CSR.scala 405:73] + node _T_1601 = eq(io.rw.addr, UInt<12>("h0c10")) @[CSR.scala 405:73] + node _T_1603 = eq(io.rw.addr, UInt<10>("h0331")) @[CSR.scala 405:73] + node _T_1605 = eq(io.rw.addr, UInt<12>("h0b11")) @[CSR.scala 405:73] + node _T_1607 = eq(io.rw.addr, UInt<12>("h0c11")) @[CSR.scala 405:73] + node _T_1609 = eq(io.rw.addr, UInt<10>("h0332")) @[CSR.scala 405:73] + node _T_1611 = eq(io.rw.addr, UInt<12>("h0b12")) @[CSR.scala 405:73] + node _T_1613 = eq(io.rw.addr, UInt<12>("h0c12")) @[CSR.scala 405:73] + node _T_1615 = eq(io.rw.addr, UInt<10>("h0333")) @[CSR.scala 405:73] + node _T_1617 = eq(io.rw.addr, UInt<12>("h0b13")) @[CSR.scala 405:73] + node _T_1619 = eq(io.rw.addr, UInt<12>("h0c13")) @[CSR.scala 405:73] + node _T_1621 = eq(io.rw.addr, UInt<10>("h0334")) @[CSR.scala 405:73] + node _T_1623 = eq(io.rw.addr, UInt<12>("h0b14")) @[CSR.scala 405:73] + node _T_1625 = eq(io.rw.addr, UInt<12>("h0c14")) @[CSR.scala 405:73] + node _T_1627 = eq(io.rw.addr, UInt<10>("h0335")) @[CSR.scala 405:73] + node _T_1629 = eq(io.rw.addr, UInt<12>("h0b15")) @[CSR.scala 405:73] + node _T_1631 = eq(io.rw.addr, UInt<12>("h0c15")) @[CSR.scala 405:73] + node _T_1633 = eq(io.rw.addr, UInt<10>("h0336")) @[CSR.scala 405:73] + node _T_1635 = eq(io.rw.addr, UInt<12>("h0b16")) @[CSR.scala 405:73] + node _T_1637 = eq(io.rw.addr, UInt<12>("h0c16")) @[CSR.scala 405:73] + node _T_1639 = eq(io.rw.addr, UInt<10>("h0337")) @[CSR.scala 405:73] + node _T_1641 = eq(io.rw.addr, UInt<12>("h0b17")) @[CSR.scala 405:73] + node _T_1643 = eq(io.rw.addr, UInt<12>("h0c17")) @[CSR.scala 405:73] + node _T_1645 = eq(io.rw.addr, UInt<10>("h0338")) @[CSR.scala 405:73] + node _T_1647 = eq(io.rw.addr, UInt<12>("h0b18")) @[CSR.scala 405:73] + node _T_1649 = eq(io.rw.addr, UInt<12>("h0c18")) @[CSR.scala 405:73] + node _T_1651 = eq(io.rw.addr, UInt<10>("h0339")) @[CSR.scala 405:73] + node _T_1653 = eq(io.rw.addr, UInt<12>("h0b19")) @[CSR.scala 405:73] + node _T_1655 = eq(io.rw.addr, UInt<12>("h0c19")) @[CSR.scala 405:73] + node _T_1657 = eq(io.rw.addr, UInt<10>("h033a")) @[CSR.scala 405:73] + node _T_1659 = eq(io.rw.addr, UInt<12>("h0b1a")) @[CSR.scala 405:73] + node _T_1661 = eq(io.rw.addr, UInt<12>("h0c1a")) @[CSR.scala 405:73] + node _T_1663 = eq(io.rw.addr, UInt<10>("h033b")) @[CSR.scala 405:73] + node _T_1665 = eq(io.rw.addr, UInt<12>("h0b1b")) @[CSR.scala 405:73] + node _T_1667 = eq(io.rw.addr, UInt<12>("h0c1b")) @[CSR.scala 405:73] + node _T_1669 = eq(io.rw.addr, UInt<10>("h033c")) @[CSR.scala 405:73] + node _T_1671 = eq(io.rw.addr, UInt<12>("h0b1c")) @[CSR.scala 405:73] + node _T_1673 = eq(io.rw.addr, UInt<12>("h0c1c")) @[CSR.scala 405:73] + node _T_1675 = eq(io.rw.addr, UInt<10>("h033d")) @[CSR.scala 405:73] + node _T_1677 = eq(io.rw.addr, UInt<12>("h0b1d")) @[CSR.scala 405:73] + node _T_1679 = eq(io.rw.addr, UInt<12>("h0c1d")) @[CSR.scala 405:73] + node _T_1681 = eq(io.rw.addr, UInt<10>("h033e")) @[CSR.scala 405:73] + node _T_1683 = eq(io.rw.addr, UInt<12>("h0b1e")) @[CSR.scala 405:73] + node _T_1685 = eq(io.rw.addr, UInt<12>("h0c1e")) @[CSR.scala 405:73] + node _T_1687 = eq(io.rw.addr, UInt<10>("h033f")) @[CSR.scala 405:73] + node _T_1689 = eq(io.rw.addr, UInt<12>("h0b1f")) @[CSR.scala 405:73] + node _T_1691 = eq(io.rw.addr, UInt<12>("h0c1f")) @[CSR.scala 405:73] + node _T_1693 = eq(io.rw.addr, UInt<9>("h0100")) @[CSR.scala 405:73] + node _T_1695 = eq(io.rw.addr, UInt<9>("h0144")) @[CSR.scala 405:73] + node _T_1697 = eq(io.rw.addr, UInt<9>("h0104")) @[CSR.scala 405:73] + node _T_1699 = eq(io.rw.addr, UInt<9>("h0140")) @[CSR.scala 405:73] + node _T_1701 = eq(io.rw.addr, UInt<9>("h0142")) @[CSR.scala 405:73] + node _T_1703 = eq(io.rw.addr, UInt<9>("h0143")) @[CSR.scala 405:73] + node _T_1705 = eq(io.rw.addr, UInt<9>("h0180")) @[CSR.scala 405:73] + node _T_1707 = eq(io.rw.addr, UInt<9>("h0141")) @[CSR.scala 405:73] + node _T_1709 = eq(io.rw.addr, UInt<9>("h0105")) @[CSR.scala 405:73] + node _T_1711 = eq(io.rw.addr, UInt<9>("h0106")) @[CSR.scala 405:73] + node _T_1713 = eq(io.rw.addr, UInt<10>("h0306")) @[CSR.scala 405:73] + node _T_1715 = eq(io.rw.addr, UInt<12>("h0c00")) @[CSR.scala 405:73] + node _T_1717 = eq(io.rw.addr, UInt<12>("h0c02")) @[CSR.scala 405:73] + node _T_1720 = eq(io.rw.cmd, UInt<3>("h02")) @[Package.scala 7:47] + node _T_1721 = eq(io.rw.cmd, UInt<3>("h03")) @[Package.scala 7:47] + node _T_1722 = or(_T_1720, _T_1721) @[Package.scala 7:62] + node _T_1724 = mux(_T_1722, io.rw.rdata, UInt<1>("h00")) @[CSR.scala 406:19] + node _T_1725 = or(_T_1724, io.rw.wdata) @[CSR.scala 406:75] + node _T_1727 = eq(io.rw.cmd, UInt<3>("h03")) @[CSR.scala 407:30] + node _T_1729 = mux(_T_1727, io.rw.wdata, UInt<1>("h00")) @[CSR.scala 407:19] + node _T_1730 = not(_T_1729) @[CSR.scala 407:15] + node wdata = and(_T_1725, _T_1730) @[CSR.scala 406:90] + node system_insn = eq(io.rw.cmd, UInt<3>("h04")) @[CSR.scala 409:31] + node _T_1733 = bits(io.rw.addr, 2, 0) @[CSR.scala 410:37] + node opcode = dshl(UInt<1>("h01"), _T_1733) @[CSR.scala 410:24] + node insn_rs2 = bits(io.rw.addr, 5, 5) @[CSR.scala 411:28] + node _T_1735 = eq(insn_rs2, UInt<1>("h00")) @[CSR.scala 412:34] + node _T_1736 = and(system_insn, _T_1735) @[CSR.scala 412:31] + node _T_1737 = bits(opcode, 0, 0) @[CSR.scala 412:53] + node insn_call = and(_T_1736, _T_1737) @[CSR.scala 412:44] + node _T_1738 = bits(opcode, 1, 1) @[CSR.scala 413:41] + node insn_break = and(system_insn, _T_1738) @[CSR.scala 413:32] + node _T_1739 = bits(opcode, 2, 2) @[CSR.scala 414:39] + node insn_ret = and(system_insn, _T_1739) @[CSR.scala 414:30] + node _T_1740 = bits(opcode, 5, 5) @[CSR.scala 415:39] + node insn_wfi = and(system_insn, _T_1740) @[CSR.scala 415:30] + node insn_sfence_vma = and(system_insn, insn_rs2) @[CSR.scala 416:37] + node _T_1743 = gt(effective_prv, UInt<1>("h01")) @[CSR.scala 418:51] + node _T_1744 = or(UInt<1>("h00"), _T_1743) @[CSR.scala 418:34] + node _T_1746 = eq(reg_mstatus.tw, UInt<1>("h00")) @[CSR.scala 418:62] + node allow_wfi = or(_T_1744, _T_1746) @[CSR.scala 418:59] + node _T_1749 = gt(effective_prv, UInt<1>("h01")) @[CSR.scala 419:58] + node _T_1750 = or(UInt<1>("h00"), _T_1749) @[CSR.scala 419:41] + node _T_1752 = eq(reg_mstatus.tvm, UInt<1>("h00")) @[CSR.scala 419:69] + node allow_sfence_vma = or(_T_1750, _T_1752) @[CSR.scala 419:66] + node _T_1755 = gt(effective_prv, UInt<1>("h01")) @[CSR.scala 420:52] + node _T_1756 = or(UInt<1>("h00"), _T_1755) @[CSR.scala 420:35] + node _T_1758 = eq(reg_mstatus.tsr, UInt<1>("h00")) @[CSR.scala 420:63] + node allow_sret = or(_T_1756, _T_1758) @[CSR.scala 420:60] + node _T_1760 = eq(io.status.fs, UInt<1>("h00")) @[CSR.scala 421:40] + node _T_1761 = bits(reg_misa, 5, 5) @[CSR.scala 421:58] + node _T_1763 = eq(_T_1761, UInt<1>("h00")) @[CSR.scala 421:49] + node _T_1764 = or(_T_1760, _T_1763) @[CSR.scala 421:46] + io.decode.fp_illegal <= _T_1764 @[CSR.scala 421:24] + node _T_1766 = eq(io.status.xs, UInt<1>("h00")) @[CSR.scala 422:42] + node _T_1767 = bits(reg_misa, 23, 23) @[CSR.scala 422:60] + node _T_1769 = eq(_T_1767, UInt<1>("h00")) @[CSR.scala 422:51] + node _T_1770 = or(_T_1766, _T_1769) @[CSR.scala 422:48] + io.decode.rocc_illegal <= _T_1770 @[CSR.scala 422:26] + node _T_1771 = bits(io.decode.csr, 9, 8) @[CSR.scala 423:58] + node _T_1772 = lt(effective_prv, _T_1771) @[CSR.scala 423:43] + node _T_1774 = eq(io.decode.csr, UInt<11>("h07a0")) @[CSR.scala 424:42] + node _T_1776 = eq(io.decode.csr, UInt<11>("h07a1")) @[CSR.scala 424:42] + node _T_1778 = eq(io.decode.csr, UInt<11>("h07a2")) @[CSR.scala 424:42] + node _T_1780 = eq(io.decode.csr, UInt<12>("h0f13")) @[CSR.scala 424:42] + node _T_1782 = eq(io.decode.csr, UInt<12>("h0f12")) @[CSR.scala 424:42] + node _T_1784 = eq(io.decode.csr, UInt<12>("h0f11")) @[CSR.scala 424:42] + node _T_1786 = eq(io.decode.csr, UInt<12>("h0b00")) @[CSR.scala 424:42] + node _T_1788 = eq(io.decode.csr, UInt<12>("h0b02")) @[CSR.scala 424:42] + node _T_1790 = eq(io.decode.csr, UInt<10>("h0301")) @[CSR.scala 424:42] + node _T_1792 = eq(io.decode.csr, UInt<10>("h0300")) @[CSR.scala 424:42] + node _T_1794 = eq(io.decode.csr, UInt<10>("h0305")) @[CSR.scala 424:42] + node _T_1796 = eq(io.decode.csr, UInt<10>("h0344")) @[CSR.scala 424:42] + node _T_1798 = eq(io.decode.csr, UInt<10>("h0304")) @[CSR.scala 424:42] + node _T_1800 = eq(io.decode.csr, UInt<10>("h0303")) @[CSR.scala 424:42] + node _T_1802 = eq(io.decode.csr, UInt<10>("h0302")) @[CSR.scala 424:42] + node _T_1804 = eq(io.decode.csr, UInt<10>("h0340")) @[CSR.scala 424:42] + node _T_1806 = eq(io.decode.csr, UInt<10>("h0341")) @[CSR.scala 424:42] + node _T_1808 = eq(io.decode.csr, UInt<10>("h0343")) @[CSR.scala 424:42] + node _T_1810 = eq(io.decode.csr, UInt<10>("h0342")) @[CSR.scala 424:42] + node _T_1812 = eq(io.decode.csr, UInt<12>("h0f14")) @[CSR.scala 424:42] + node _T_1814 = eq(io.decode.csr, UInt<11>("h07b0")) @[CSR.scala 424:42] + node _T_1816 = eq(io.decode.csr, UInt<11>("h07b1")) @[CSR.scala 424:42] + node _T_1818 = eq(io.decode.csr, UInt<11>("h07b2")) @[CSR.scala 424:42] + node _T_1820 = eq(io.decode.csr, UInt<1>("h01")) @[CSR.scala 424:42] + node _T_1822 = eq(io.decode.csr, UInt<2>("h02")) @[CSR.scala 424:42] + node _T_1824 = eq(io.decode.csr, UInt<2>("h03")) @[CSR.scala 424:42] + node _T_1826 = eq(io.decode.csr, UInt<10>("h0323")) @[CSR.scala 424:42] + node _T_1828 = eq(io.decode.csr, UInt<12>("h0b03")) @[CSR.scala 424:42] + node _T_1830 = eq(io.decode.csr, UInt<12>("h0c03")) @[CSR.scala 424:42] + node _T_1832 = eq(io.decode.csr, UInt<10>("h0324")) @[CSR.scala 424:42] + node _T_1834 = eq(io.decode.csr, UInt<12>("h0b04")) @[CSR.scala 424:42] + node _T_1836 = eq(io.decode.csr, UInt<12>("h0c04")) @[CSR.scala 424:42] + node _T_1838 = eq(io.decode.csr, UInt<10>("h0325")) @[CSR.scala 424:42] + node _T_1840 = eq(io.decode.csr, UInt<12>("h0b05")) @[CSR.scala 424:42] + node _T_1842 = eq(io.decode.csr, UInt<12>("h0c05")) @[CSR.scala 424:42] + node _T_1844 = eq(io.decode.csr, UInt<10>("h0326")) @[CSR.scala 424:42] + node _T_1846 = eq(io.decode.csr, UInt<12>("h0b06")) @[CSR.scala 424:42] + node _T_1848 = eq(io.decode.csr, UInt<12>("h0c06")) @[CSR.scala 424:42] + node _T_1850 = eq(io.decode.csr, UInt<10>("h0327")) @[CSR.scala 424:42] + node _T_1852 = eq(io.decode.csr, UInt<12>("h0b07")) @[CSR.scala 424:42] + node _T_1854 = eq(io.decode.csr, UInt<12>("h0c07")) @[CSR.scala 424:42] + node _T_1856 = eq(io.decode.csr, UInt<10>("h0328")) @[CSR.scala 424:42] + node _T_1858 = eq(io.decode.csr, UInt<12>("h0b08")) @[CSR.scala 424:42] + node _T_1860 = eq(io.decode.csr, UInt<12>("h0c08")) @[CSR.scala 424:42] + node _T_1862 = eq(io.decode.csr, UInt<10>("h0329")) @[CSR.scala 424:42] + node _T_1864 = eq(io.decode.csr, UInt<12>("h0b09")) @[CSR.scala 424:42] + node _T_1866 = eq(io.decode.csr, UInt<12>("h0c09")) @[CSR.scala 424:42] + node _T_1868 = eq(io.decode.csr, UInt<10>("h032a")) @[CSR.scala 424:42] + node _T_1870 = eq(io.decode.csr, UInt<12>("h0b0a")) @[CSR.scala 424:42] + node _T_1872 = eq(io.decode.csr, UInt<12>("h0c0a")) @[CSR.scala 424:42] + node _T_1874 = eq(io.decode.csr, UInt<10>("h032b")) @[CSR.scala 424:42] + node _T_1876 = eq(io.decode.csr, UInt<12>("h0b0b")) @[CSR.scala 424:42] + node _T_1878 = eq(io.decode.csr, UInt<12>("h0c0b")) @[CSR.scala 424:42] + node _T_1880 = eq(io.decode.csr, UInt<10>("h032c")) @[CSR.scala 424:42] + node _T_1882 = eq(io.decode.csr, UInt<12>("h0b0c")) @[CSR.scala 424:42] + node _T_1884 = eq(io.decode.csr, UInt<12>("h0c0c")) @[CSR.scala 424:42] + node _T_1886 = eq(io.decode.csr, UInt<10>("h032d")) @[CSR.scala 424:42] + node _T_1888 = eq(io.decode.csr, UInt<12>("h0b0d")) @[CSR.scala 424:42] + node _T_1890 = eq(io.decode.csr, UInt<12>("h0c0d")) @[CSR.scala 424:42] + node _T_1892 = eq(io.decode.csr, UInt<10>("h032e")) @[CSR.scala 424:42] + node _T_1894 = eq(io.decode.csr, UInt<12>("h0b0e")) @[CSR.scala 424:42] + node _T_1896 = eq(io.decode.csr, UInt<12>("h0c0e")) @[CSR.scala 424:42] + node _T_1898 = eq(io.decode.csr, UInt<10>("h032f")) @[CSR.scala 424:42] + node _T_1900 = eq(io.decode.csr, UInt<12>("h0b0f")) @[CSR.scala 424:42] + node _T_1902 = eq(io.decode.csr, UInt<12>("h0c0f")) @[CSR.scala 424:42] + node _T_1904 = eq(io.decode.csr, UInt<10>("h0330")) @[CSR.scala 424:42] + node _T_1906 = eq(io.decode.csr, UInt<12>("h0b10")) @[CSR.scala 424:42] + node _T_1908 = eq(io.decode.csr, UInt<12>("h0c10")) @[CSR.scala 424:42] + node _T_1910 = eq(io.decode.csr, UInt<10>("h0331")) @[CSR.scala 424:42] + node _T_1912 = eq(io.decode.csr, UInt<12>("h0b11")) @[CSR.scala 424:42] + node _T_1914 = eq(io.decode.csr, UInt<12>("h0c11")) @[CSR.scala 424:42] + node _T_1916 = eq(io.decode.csr, UInt<10>("h0332")) @[CSR.scala 424:42] + node _T_1918 = eq(io.decode.csr, UInt<12>("h0b12")) @[CSR.scala 424:42] + node _T_1920 = eq(io.decode.csr, UInt<12>("h0c12")) @[CSR.scala 424:42] + node _T_1922 = eq(io.decode.csr, UInt<10>("h0333")) @[CSR.scala 424:42] + node _T_1924 = eq(io.decode.csr, UInt<12>("h0b13")) @[CSR.scala 424:42] + node _T_1926 = eq(io.decode.csr, UInt<12>("h0c13")) @[CSR.scala 424:42] + node _T_1928 = eq(io.decode.csr, UInt<10>("h0334")) @[CSR.scala 424:42] + node _T_1930 = eq(io.decode.csr, UInt<12>("h0b14")) @[CSR.scala 424:42] + node _T_1932 = eq(io.decode.csr, UInt<12>("h0c14")) @[CSR.scala 424:42] + node _T_1934 = eq(io.decode.csr, UInt<10>("h0335")) @[CSR.scala 424:42] + node _T_1936 = eq(io.decode.csr, UInt<12>("h0b15")) @[CSR.scala 424:42] + node _T_1938 = eq(io.decode.csr, UInt<12>("h0c15")) @[CSR.scala 424:42] + node _T_1940 = eq(io.decode.csr, UInt<10>("h0336")) @[CSR.scala 424:42] + node _T_1942 = eq(io.decode.csr, UInt<12>("h0b16")) @[CSR.scala 424:42] + node _T_1944 = eq(io.decode.csr, UInt<12>("h0c16")) @[CSR.scala 424:42] + node _T_1946 = eq(io.decode.csr, UInt<10>("h0337")) @[CSR.scala 424:42] + node _T_1948 = eq(io.decode.csr, UInt<12>("h0b17")) @[CSR.scala 424:42] + node _T_1950 = eq(io.decode.csr, UInt<12>("h0c17")) @[CSR.scala 424:42] + node _T_1952 = eq(io.decode.csr, UInt<10>("h0338")) @[CSR.scala 424:42] + node _T_1954 = eq(io.decode.csr, UInt<12>("h0b18")) @[CSR.scala 424:42] + node _T_1956 = eq(io.decode.csr, UInt<12>("h0c18")) @[CSR.scala 424:42] + node _T_1958 = eq(io.decode.csr, UInt<10>("h0339")) @[CSR.scala 424:42] + node _T_1960 = eq(io.decode.csr, UInt<12>("h0b19")) @[CSR.scala 424:42] + node _T_1962 = eq(io.decode.csr, UInt<12>("h0c19")) @[CSR.scala 424:42] + node _T_1964 = eq(io.decode.csr, UInt<10>("h033a")) @[CSR.scala 424:42] + node _T_1966 = eq(io.decode.csr, UInt<12>("h0b1a")) @[CSR.scala 424:42] + node _T_1968 = eq(io.decode.csr, UInt<12>("h0c1a")) @[CSR.scala 424:42] + node _T_1970 = eq(io.decode.csr, UInt<10>("h033b")) @[CSR.scala 424:42] + node _T_1972 = eq(io.decode.csr, UInt<12>("h0b1b")) @[CSR.scala 424:42] + node _T_1974 = eq(io.decode.csr, UInt<12>("h0c1b")) @[CSR.scala 424:42] + node _T_1976 = eq(io.decode.csr, UInt<10>("h033c")) @[CSR.scala 424:42] + node _T_1978 = eq(io.decode.csr, UInt<12>("h0b1c")) @[CSR.scala 424:42] + node _T_1980 = eq(io.decode.csr, UInt<12>("h0c1c")) @[CSR.scala 424:42] + node _T_1982 = eq(io.decode.csr, UInt<10>("h033d")) @[CSR.scala 424:42] + node _T_1984 = eq(io.decode.csr, UInt<12>("h0b1d")) @[CSR.scala 424:42] + node _T_1986 = eq(io.decode.csr, UInt<12>("h0c1d")) @[CSR.scala 424:42] + node _T_1988 = eq(io.decode.csr, UInt<10>("h033e")) @[CSR.scala 424:42] + node _T_1990 = eq(io.decode.csr, UInt<12>("h0b1e")) @[CSR.scala 424:42] + node _T_1992 = eq(io.decode.csr, UInt<12>("h0c1e")) @[CSR.scala 424:42] + node _T_1994 = eq(io.decode.csr, UInt<10>("h033f")) @[CSR.scala 424:42] + node _T_1996 = eq(io.decode.csr, UInt<12>("h0b1f")) @[CSR.scala 424:42] + node _T_1998 = eq(io.decode.csr, UInt<12>("h0c1f")) @[CSR.scala 424:42] + node _T_2000 = eq(io.decode.csr, UInt<9>("h0100")) @[CSR.scala 424:42] + node _T_2002 = eq(io.decode.csr, UInt<9>("h0144")) @[CSR.scala 424:42] + node _T_2004 = eq(io.decode.csr, UInt<9>("h0104")) @[CSR.scala 424:42] + node _T_2006 = eq(io.decode.csr, UInt<9>("h0140")) @[CSR.scala 424:42] + node _T_2008 = eq(io.decode.csr, UInt<9>("h0142")) @[CSR.scala 424:42] + node _T_2010 = eq(io.decode.csr, UInt<9>("h0143")) @[CSR.scala 424:42] + node _T_2012 = eq(io.decode.csr, UInt<9>("h0180")) @[CSR.scala 424:42] + node _T_2014 = eq(io.decode.csr, UInt<9>("h0141")) @[CSR.scala 424:42] + node _T_2016 = eq(io.decode.csr, UInt<9>("h0105")) @[CSR.scala 424:42] + node _T_2018 = eq(io.decode.csr, UInt<9>("h0106")) @[CSR.scala 424:42] + node _T_2020 = eq(io.decode.csr, UInt<10>("h0306")) @[CSR.scala 424:42] + node _T_2022 = eq(io.decode.csr, UInt<12>("h0c00")) @[CSR.scala 424:42] + node _T_2024 = eq(io.decode.csr, UInt<12>("h0c02")) @[CSR.scala 424:42] + node _T_2025 = or(_T_1952, _T_1820) @[CSR.scala 424:57] + node _T_2026 = or(_T_2025, _T_1864) @[CSR.scala 424:57] + node _T_2027 = or(_T_2026, _T_2006) @[CSR.scala 424:57] + node _T_2028 = or(_T_2027, _T_1978) @[CSR.scala 424:57] + node _T_2029 = or(_T_2028, _T_1946) @[CSR.scala 424:57] + node _T_2030 = or(_T_2029, _T_1832) @[CSR.scala 424:57] + node _T_2031 = or(_T_2030, _T_1800) @[CSR.scala 424:57] + node _T_2032 = or(_T_2031, _T_2020) @[CSR.scala 424:57] + node _T_2033 = or(_T_2032, _T_1914) @[CSR.scala 424:57] + node _T_2034 = or(_T_2033, _T_1876) @[CSR.scala 424:57] + node _T_2035 = or(_T_2034, _T_1920) @[CSR.scala 424:57] + node _T_2036 = or(_T_2035, _T_1788) @[CSR.scala 424:57] + node _T_2037 = or(_T_2036, _T_1844) @[CSR.scala 424:57] + node _T_2038 = or(_T_2037, _T_1888) @[CSR.scala 424:57] + node _T_2039 = or(_T_2038, _T_1872) @[CSR.scala 424:57] + node _T_2040 = or(_T_2039, _T_1988) @[CSR.scala 424:57] + node _T_2041 = or(_T_2040, _T_1910) @[CSR.scala 424:57] + node _T_2042 = or(_T_2041, _T_1924) @[CSR.scala 424:57] + node _T_2043 = or(_T_2042, _T_1776) @[CSR.scala 424:57] + node _T_2044 = or(_T_2043, _T_1808) @[CSR.scala 424:57] + node _T_2045 = or(_T_2044, _T_1892) @[CSR.scala 424:57] + node _T_2046 = or(_T_2045, _T_1840) @[CSR.scala 424:57] + node _T_2047 = or(_T_2046, _T_1956) @[CSR.scala 424:57] + node _T_2048 = or(_T_2047, _T_2010) @[CSR.scala 424:57] + node _T_2049 = or(_T_2048, _T_1868) @[CSR.scala 424:57] + node _T_2050 = or(_T_2049, _T_2000) @[CSR.scala 424:57] + node _T_2051 = or(_T_2050, _T_1878) @[CSR.scala 424:57] + node _T_2052 = or(_T_2051, _T_1942) @[CSR.scala 424:57] + node _T_2053 = or(_T_2052, _T_1812) @[CSR.scala 424:57] + node _T_2054 = or(_T_2053, _T_1974) @[CSR.scala 424:57] + node _T_2055 = or(_T_2054, _T_1968) @[CSR.scala 424:57] + node _T_2056 = or(_T_2055, _T_1780) @[CSR.scala 424:57] + node _T_2057 = or(_T_2056, _T_1836) @[CSR.scala 424:57] + node _T_2058 = or(_T_2057, _T_1996) @[CSR.scala 424:57] + node _T_2059 = or(_T_2058, _T_1814) @[CSR.scala 424:57] + node _T_2060 = or(_T_2059, _T_1900) @[CSR.scala 424:57] + node _T_2061 = or(_T_2060, _T_1846) @[CSR.scala 424:57] + node _T_2062 = or(_T_2061, _T_1932) @[CSR.scala 424:57] + node _T_2063 = or(_T_2062, _T_1964) @[CSR.scala 424:57] + node _T_2064 = or(_T_2063, _T_1782) @[CSR.scala 424:57] + node _T_2065 = or(_T_2064, _T_1904) @[CSR.scala 424:57] + node _T_2066 = or(_T_2065, _T_1992) @[CSR.scala 424:57] + node _T_2067 = or(_T_2066, _T_1860) @[CSR.scala 424:57] + node _T_2068 = or(_T_2067, _T_1804) @[CSR.scala 424:57] + node _T_2069 = or(_T_2068, _T_1936) @[CSR.scala 424:57] + node _T_2070 = or(_T_2069, _T_1960) @[CSR.scala 424:57] + node _T_2071 = or(_T_2070, _T_1828) @[CSR.scala 424:57] + node _T_2072 = or(_T_2071, _T_1908) @[CSR.scala 424:57] + node _T_2073 = or(_T_2072, _T_2024) @[CSR.scala 424:57] + node _T_2074 = or(_T_2073, _T_2004) @[CSR.scala 424:57] + node _T_2075 = or(_T_2074, _T_1856) @[CSR.scala 424:57] + node _T_2076 = or(_T_2075, _T_1940) @[CSR.scala 424:57] + node _T_2077 = or(_T_2076, _T_1792) @[CSR.scala 424:57] + node _T_2078 = or(_T_2077, _T_1972) @[CSR.scala 424:57] + node _T_2079 = or(_T_2078, _T_1824) @[CSR.scala 424:57] + node _T_2080 = or(_T_2079, _T_1896) @[CSR.scala 424:57] + node _T_2081 = or(_T_2080, _T_1928) @[CSR.scala 424:57] + node _T_2082 = or(_T_2081, _T_1796) @[CSR.scala 424:57] + node _T_2083 = or(_T_2082, _T_1918) @[CSR.scala 424:57] + node _T_2084 = or(_T_2083, _T_1786) @[CSR.scala 424:57] + node _T_2085 = or(_T_2084, _T_1980) @[CSR.scala 424:57] + node _T_2086 = or(_T_2085, _T_1774) @[CSR.scala 424:57] + node _T_2087 = or(_T_2086, _T_1830) @[CSR.scala 424:57] + node _T_2088 = or(_T_2087, _T_1890) @[CSR.scala 424:57] + node _T_2089 = or(_T_2088, _T_2018) @[CSR.scala 424:57] + node _T_2090 = or(_T_2089, _T_1916) @[CSR.scala 424:57] + node _T_2091 = or(_T_2090, _T_1884) @[CSR.scala 424:57] + node _T_2092 = or(_T_2091, _T_1862) @[CSR.scala 424:57] + node _T_2093 = or(_T_2092, _T_1948) @[CSR.scala 424:57] + node _T_2094 = or(_T_2093, _T_1798) @[CSR.scala 424:57] + node _T_2095 = or(_T_2094, _T_1976) @[CSR.scala 424:57] + node _T_2096 = or(_T_2095, _T_1886) @[CSR.scala 424:57] + node _T_2097 = or(_T_2096, _T_1950) @[CSR.scala 424:57] + node _T_2098 = or(_T_2097, _T_1818) @[CSR.scala 424:57] + node _T_2099 = or(_T_2098, _T_1982) @[CSR.scala 424:57] + node _T_2100 = or(_T_2099, _T_1850) @[CSR.scala 424:57] + node _T_2101 = or(_T_2100, _T_1810) @[CSR.scala 424:57] + node _T_2102 = or(_T_2101, _T_1944) @[CSR.scala 424:57] + node _T_2103 = or(_T_2102, _T_2014) @[CSR.scala 424:57] + node _T_2104 = or(_T_2103, _T_1838) @[CSR.scala 424:57] + node _T_2105 = or(_T_2104, _T_1954) @[CSR.scala 424:57] + node _T_2106 = or(_T_2105, _T_1870) @[CSR.scala 424:57] + node _T_2107 = or(_T_2106, _T_1986) @[CSR.scala 424:57] + node _T_2108 = or(_T_2107, _T_2008) @[CSR.scala 424:57] + node _T_2109 = or(_T_2108, _T_1922) @[CSR.scala 424:57] + node _T_2110 = or(_T_2109, _T_1778) @[CSR.scala 424:57] + node _T_2111 = or(_T_2110, _T_1806) @[CSR.scala 424:57] + node _T_2112 = or(_T_2111, _T_1842) @[CSR.scala 424:57] + node _T_2113 = or(_T_2112, _T_1874) @[CSR.scala 424:57] + node _T_2114 = or(_T_2113, _T_1880) @[CSR.scala 424:57] + node _T_2115 = or(_T_2114, _T_2012) @[CSR.scala 424:57] + node _T_2116 = or(_T_2115, _T_1912) @[CSR.scala 424:57] + node _T_2117 = or(_T_2116, _T_1802) @[CSR.scala 424:57] + node _T_2118 = or(_T_2117, _T_1934) @[CSR.scala 424:57] + node _T_2119 = or(_T_2118, _T_1848) @[CSR.scala 424:57] + node _T_2120 = or(_T_2119, _T_1962) @[CSR.scala 424:57] + node _T_2121 = or(_T_2120, _T_1784) @[CSR.scala 424:57] + node _T_2122 = or(_T_2121, _T_1902) @[CSR.scala 424:57] + node _T_2123 = or(_T_2122, _T_1994) @[CSR.scala 424:57] + node _T_2124 = or(_T_2123, _T_2016) @[CSR.scala 424:57] + node _T_2125 = or(_T_2124, _T_1930) @[CSR.scala 424:57] + node _T_2126 = or(_T_2125, _T_1816) @[CSR.scala 424:57] + node _T_2127 = or(_T_2126, _T_1834) @[CSR.scala 424:57] + node _T_2128 = or(_T_2127, _T_1966) @[CSR.scala 424:57] + node _T_2129 = or(_T_2128, _T_1898) @[CSR.scala 424:57] + node _T_2130 = or(_T_2129, _T_1866) @[CSR.scala 424:57] + node _T_2131 = or(_T_2130, _T_1998) @[CSR.scala 424:57] + node _T_2132 = or(_T_2131, _T_1926) @[CSR.scala 424:57] + node _T_2133 = or(_T_2132, _T_1794) @[CSR.scala 424:57] + node _T_2134 = or(_T_2133, _T_1882) @[CSR.scala 424:57] + node _T_2135 = or(_T_2134, _T_1970) @[CSR.scala 424:57] + node _T_2136 = or(_T_2135, _T_1822) @[CSR.scala 424:57] + node _T_2137 = or(_T_2136, _T_1894) @[CSR.scala 424:57] + node _T_2138 = or(_T_2137, _T_2002) @[CSR.scala 424:57] + node _T_2139 = or(_T_2138, _T_1854) @[CSR.scala 424:57] + node _T_2140 = or(_T_2139, _T_1938) @[CSR.scala 424:57] + node _T_2141 = or(_T_2140, _T_1984) @[CSR.scala 424:57] + node _T_2142 = or(_T_2141, _T_1790) @[CSR.scala 424:57] + node _T_2143 = or(_T_2142, _T_1852) @[CSR.scala 424:57] + node _T_2144 = or(_T_2143, _T_1958) @[CSR.scala 424:57] + node _T_2145 = or(_T_2144, _T_1826) @[CSR.scala 424:57] + node _T_2146 = or(_T_2145, _T_2022) @[CSR.scala 424:57] + node _T_2147 = or(_T_2146, _T_1906) @[CSR.scala 424:57] + node _T_2148 = or(_T_2147, _T_1990) @[CSR.scala 424:57] + node _T_2149 = or(_T_2148, _T_1858) @[CSR.scala 424:57] + node _T_2151 = eq(_T_2149, UInt<1>("h00")) @[CSR.scala 424:5] + node _T_2152 = or(_T_1772, _T_2151) @[CSR.scala 423:64] + node _T_2154 = eq(io.decode.csr, UInt<9>("h0180")) @[CSR.scala 425:19] + node _T_2156 = eq(allow_sfence_vma, UInt<1>("h00")) @[CSR.scala 425:37] + node _T_2157 = and(_T_2154, _T_2156) @[CSR.scala 425:34] + node _T_2158 = or(_T_2152, _T_2157) @[CSR.scala 424:62] + node _T_2161 = geq(io.decode.csr, UInt<12>("h0c00")) @[Package.scala 47:47] + node _T_2162 = lt(io.decode.csr, UInt<12>("h0c20")) @[Package.scala 47:60] + node _T_2163 = and(_T_2161, _T_2162) @[Package.scala 47:55] + node _T_2166 = geq(io.decode.csr, UInt<12>("h0c80")) @[Package.scala 47:47] + node _T_2167 = lt(io.decode.csr, UInt<12>("h0ca0")) @[Package.scala 47:60] + node _T_2168 = and(_T_2166, _T_2167) @[Package.scala 47:55] + node _T_2169 = or(_T_2163, _T_2168) @[CSR.scala 426:67] + node _T_2171 = leq(effective_prv, UInt<1>("h01")) @[CSR.scala 426:151] + node _T_2172 = and(_T_2169, _T_2171) @[CSR.scala 426:134] + node _T_2173 = bits(io.decode.csr, 11, 0) @[CSR.scala 426:185] + node _T_2174 = dshr(hpm_mask, _T_2173) @[CSR.scala 426:171] + node _T_2175 = bits(_T_2174, 0, 0) @[CSR.scala 426:171] + node _T_2176 = and(_T_2172, _T_2175) @[CSR.scala 426:160] + node _T_2177 = or(_T_2158, _T_2176) @[CSR.scala 425:55] + node _T_2180 = eq(reg_debug, UInt<1>("h00")) @[CSR.scala 427:25] + node _T_2181 = and(UInt<1>("h01"), _T_2180) @[CSR.scala 427:22] + node _T_2183 = eq(io.decode.csr, UInt<11>("h07b0")) @[CSR.scala 427:73] + node _T_2185 = eq(io.decode.csr, UInt<11>("h07b1")) @[CSR.scala 427:73] + node _T_2187 = eq(io.decode.csr, UInt<11>("h07b2")) @[CSR.scala 427:73] + node _T_2188 = or(_T_2183, _T_2185) @[CSR.scala 427:88] + node _T_2189 = or(_T_2188, _T_2187) @[CSR.scala 427:88] + node _T_2190 = and(_T_2181, _T_2189) @[CSR.scala 427:36] + node _T_2191 = or(_T_2177, _T_2190) @[CSR.scala 426:215] + node _T_2194 = eq(io.decode.csr, UInt<1>("h01")) @[CSR.scala 428:54] + node _T_2196 = eq(io.decode.csr, UInt<2>("h02")) @[CSR.scala 428:54] + node _T_2198 = eq(io.decode.csr, UInt<2>("h03")) @[CSR.scala 428:54] + node _T_2199 = or(_T_2194, _T_2196) @[CSR.scala 428:69] + node _T_2200 = or(_T_2199, _T_2198) @[CSR.scala 428:69] + node _T_2201 = and(UInt<1>("h01"), _T_2200) @[CSR.scala 428:20] + node _T_2202 = and(_T_2201, io.decode.fp_illegal) @[CSR.scala 428:74] + node _T_2203 = or(_T_2191, _T_2202) @[CSR.scala 427:93] + io.decode.read_illegal <= _T_2203 @[CSR.scala 423:26] + node _T_2204 = bits(io.decode.csr, 11, 10) @[CSR.scala 429:43] + node _T_2205 = not(_T_2204) @[CSR.scala 429:51] + node _T_2207 = eq(_T_2205, UInt<1>("h00")) @[CSR.scala 429:51] + io.decode.write_illegal <= _T_2207 @[CSR.scala 429:27] + node _T_2209 = geq(io.decode.csr, UInt<10>("h0340")) @[CSR.scala 430:44] + node _T_2211 = leq(io.decode.csr, UInt<10>("h0343")) @[CSR.scala 430:78] + node _T_2212 = and(_T_2209, _T_2211) @[CSR.scala 430:61] + node _T_2214 = geq(io.decode.csr, UInt<9>("h0140")) @[CSR.scala 430:112] + node _T_2216 = leq(io.decode.csr, UInt<9>("h0143")) @[CSR.scala 430:146] + node _T_2217 = and(_T_2214, _T_2216) @[CSR.scala 430:129] + node _T_2218 = or(_T_2212, _T_2217) @[CSR.scala 430:95] + node _T_2220 = eq(_T_2218, UInt<1>("h00")) @[CSR.scala 430:28] + io.decode.write_flush <= _T_2220 @[CSR.scala 430:25] + node _T_2221 = bits(io.decode.csr, 9, 8) @[CSR.scala 431:60] + node _T_2222 = lt(effective_prv, _T_2221) @[CSR.scala 431:45] + node _T_2223 = bits(io.decode.csr, 5, 5) @[CSR.scala 432:19] + node _T_2225 = eq(_T_2223, UInt<1>("h00")) @[CSR.scala 432:5] + node _T_2226 = bits(io.decode.csr, 2, 2) @[CSR.scala 432:39] + node _T_2227 = and(_T_2225, _T_2226) @[CSR.scala 432:23] + node _T_2229 = eq(allow_wfi, UInt<1>("h00")) @[CSR.scala 432:46] + node _T_2230 = and(_T_2227, _T_2229) @[CSR.scala 432:43] + node _T_2231 = or(_T_2222, _T_2230) @[CSR.scala 431:66] + node _T_2232 = bits(io.decode.csr, 5, 5) @[CSR.scala 433:19] + node _T_2234 = eq(_T_2232, UInt<1>("h00")) @[CSR.scala 433:5] + node _T_2235 = bits(io.decode.csr, 1, 1) @[CSR.scala 433:39] + node _T_2236 = and(_T_2234, _T_2235) @[CSR.scala 433:23] + node _T_2238 = eq(allow_sret, UInt<1>("h00")) @[CSR.scala 433:46] + node _T_2239 = and(_T_2236, _T_2238) @[CSR.scala 433:43] + node _T_2240 = or(_T_2231, _T_2239) @[CSR.scala 432:57] + node _T_2241 = bits(io.decode.csr, 5, 5) @[CSR.scala 434:18] + node _T_2243 = eq(allow_sfence_vma, UInt<1>("h00")) @[CSR.scala 434:25] + node _T_2244 = and(_T_2241, _T_2243) @[CSR.scala 434:22] + node _T_2245 = or(_T_2240, _T_2244) @[CSR.scala 433:58] + io.decode.system_illegal <= _T_2245 @[CSR.scala 431:28] + node _T_2247 = add(reg_mstatus.prv, UInt<4>("h08")) @[CSR.scala 437:36] + node _T_2248 = tail(_T_2247, 1) @[CSR.scala 437:36] + node _T_2250 = mux(insn_break, UInt<2>("h03"), io.cause) @[CSR.scala 438:14] + node cause = mux(insn_call, _T_2248, _T_2250) @[CSR.scala 437:8] + node cause_lsbs = bits(cause, 5, 0) @[CSR.scala 439:25] + node _T_2251 = bits(cause, 63, 63) @[CSR.scala 440:30] + node _T_2267 = eq(cause_lsbs, UInt<4>("h0d")) @[CSR.scala 440:53] + node causeIsDebugInt = and(_T_2251, _T_2267) @[CSR.scala 440:39] + node _T_2268 = bits(cause, 63, 63) @[CSR.scala 441:35] + node _T_2270 = eq(_T_2268, UInt<1>("h00")) @[CSR.scala 441:29] + node _T_2300 = eq(cause_lsbs, UInt<4>("h0d")) @[CSR.scala 441:58] + node causeIsDebugTrigger = and(_T_2270, _T_2300) @[CSR.scala 441:44] + node _T_2301 = bits(cause, 63, 63) @[CSR.scala 442:33] + node _T_2303 = eq(_T_2301, UInt<1>("h00")) @[CSR.scala 442:27] + node _T_2304 = and(_T_2303, insn_break) @[CSR.scala 442:42] + node _T_2305 = cat(reg_dcsr.ebreaks, reg_dcsr.ebreaku) @[Cat.scala 30:58] + node _T_2306 = cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh) @[Cat.scala 30:58] + node _T_2307 = cat(_T_2306, _T_2305) @[Cat.scala 30:58] + node _T_2308 = dshr(_T_2307, reg_mstatus.prv) @[CSR.scala 442:134] + node _T_2309 = bits(_T_2308, 0, 0) @[CSR.scala 442:134] + node causeIsDebugBreak = and(_T_2304, _T_2309) @[CSR.scala 442:56] + node _T_2311 = or(reg_singleStepped, causeIsDebugInt) @[CSR.scala 443:60] + node _T_2312 = or(_T_2311, causeIsDebugTrigger) @[CSR.scala 443:79] + node _T_2313 = or(_T_2312, causeIsDebugBreak) @[CSR.scala 443:102] + node _T_2314 = or(_T_2313, reg_debug) @[CSR.scala 443:123] + node trapToDebug = and(UInt<1>("h01"), _T_2314) @[CSR.scala 443:38] + node _T_2317 = leq(reg_mstatus.prv, UInt<1>("h01")) @[CSR.scala 444:51] + node _T_2318 = and(UInt<1>("h01"), _T_2317) @[CSR.scala 444:32] + node _T_2319 = bits(cause, 63, 63) @[CSR.scala 444:72] + node _T_2320 = dshr(reg_mideleg, cause_lsbs) @[CSR.scala 444:93] + node _T_2321 = bits(_T_2320, 0, 0) @[CSR.scala 444:93] + node _T_2322 = dshr(reg_medeleg, cause_lsbs) @[CSR.scala 444:118] + node _T_2323 = bits(_T_2322, 0, 0) @[CSR.scala 444:118] + node _T_2324 = mux(_T_2319, _T_2321, _T_2323) @[CSR.scala 444:66] + node delegate = and(_T_2318, _T_2324) @[CSR.scala 444:60] + node debugTVec = mux(reg_debug, UInt<12>("h0808"), UInt<12>("h0800")) @[CSR.scala 445:22] + node _T_2327 = bits(reg_stvec, 38, 38) @[Package.scala 40:38] + node _T_2328 = cat(_T_2327, reg_stvec) @[Cat.scala 30:58] + node _T_2329 = mux(delegate, _T_2328, reg_mtvec) @[CSR.scala 446:45] + node tvec = mux(trapToDebug, debugTVec, _T_2329) @[CSR.scala 446:17] + io.fatc <= insn_sfence_vma @[CSR.scala 447:11] + io.evec <= tvec @[CSR.scala 448:11] + io.ptbr <- reg_sptbr @[CSR.scala 449:11] + node _T_2330 = or(insn_call, insn_break) @[CSR.scala 450:24] + node _T_2331 = or(_T_2330, insn_ret) @[CSR.scala 450:38] + io.eret <= _T_2331 @[CSR.scala 450:11] + node _T_2333 = eq(reg_debug, UInt<1>("h00")) @[CSR.scala 451:37] + node _T_2334 = and(reg_dcsr.step, _T_2333) @[CSR.scala 451:34] + io.singleStep <= _T_2334 @[CSR.scala 451:17] + io.status <- reg_mstatus @[CSR.scala 452:13] + node _T_2335 = not(io.status.fs) @[CSR.scala 453:32] + node _T_2337 = eq(_T_2335, UInt<1>("h00")) @[CSR.scala 453:32] + node _T_2338 = not(io.status.xs) @[CSR.scala 453:53] + node _T_2340 = eq(_T_2338, UInt<1>("h00")) @[CSR.scala 453:53] + node _T_2341 = or(_T_2337, _T_2340) @[CSR.scala 453:37] + io.status.sd <= _T_2341 @[CSR.scala 453:16] + io.status.debug <= reg_debug @[CSR.scala 454:19] + io.status.isa <= reg_misa @[CSR.scala 455:17] + io.status.uxl <= UInt<2>("h02") @[CSR.scala 456:17] + io.status.sxl <= UInt<2>("h02") @[CSR.scala 457:17] + node _T_2344 = or(insn_call, insn_break) @[CSR.scala 461:29] + node exception = or(_T_2344, io.exception) @[CSR.scala 461:43] + node _T_2345 = add(insn_ret, insn_call) @[Bitwise.scala 48:55] + node _T_2346 = add(insn_break, io.exception) @[Bitwise.scala 48:55] + node _T_2347 = add(_T_2345, _T_2346) @[Bitwise.scala 48:55] + node _T_2349 = leq(_T_2347, UInt<1>("h01")) @[CSR.scala 462:79] + node _T_2350 = or(_T_2349, reset) @[CSR.scala 462:9] + node _T_2352 = eq(_T_2350, UInt<1>("h00")) @[CSR.scala 462:9] + when _T_2352 : @[CSR.scala 462:9] + printf(clock, UInt<1>(1), "Assertion failed: these conditions must be mutually exclusive\n at CSR.scala:462 assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1, \"these conditions must be mutually exclusive\")\n") @[CSR.scala 462:9] + stop(clock, UInt<1>(1), 1) @[CSR.scala 462:9] + skip @[CSR.scala 462:9] + when insn_wfi : @[CSR.scala 464:19] + reg_wfi <= UInt<1>("h01") @[CSR.scala 464:29] + skip @[CSR.scala 464:19] + node _T_2355 = neq(pending_interrupts, UInt<1>("h00")) @[CSR.scala 465:28] + node _T_2356 = or(_T_2355, exception) @[CSR.scala 465:32] + when _T_2356 : @[CSR.scala 465:46] + reg_wfi <= UInt<1>("h00") @[CSR.scala 465:56] + skip @[CSR.scala 465:46] + node _T_2359 = eq(reg_wfi, UInt<1>("h00")) @[CSR.scala 466:10] + node _T_2361 = eq(io.retire, UInt<1>("h00")) @[CSR.scala 466:32] + node _T_2362 = or(_T_2359, _T_2361) @[CSR.scala 466:19] + node _T_2363 = or(_T_2362, reset) @[CSR.scala 466:9] + node _T_2365 = eq(_T_2363, UInt<1>("h00")) @[CSR.scala 466:9] + when _T_2365 : @[CSR.scala 466:9] + printf(clock, UInt<1>(1), "Assertion failed\n at CSR.scala:466 assert(!reg_wfi || io.retire === UInt(0))\n") @[CSR.scala 466:9] + stop(clock, UInt<1>(1), 1) @[CSR.scala 466:9] + skip @[CSR.scala 466:9] + node _T_2366 = bits(io.retire, 0, 0) @[CSR.scala 468:18] + when _T_2366 : @[CSR.scala 468:23] + reg_singleStepped <= UInt<1>("h01") @[CSR.scala 468:43] + skip @[CSR.scala 468:23] + node _T_2369 = eq(io.singleStep, UInt<1>("h00")) @[CSR.scala 469:9] + when _T_2369 : @[CSR.scala 469:25] + reg_singleStepped <= UInt<1>("h00") @[CSR.scala 469:45] + skip @[CSR.scala 469:25] + node _T_2372 = eq(io.singleStep, UInt<1>("h00")) @[CSR.scala 470:10] + node _T_2374 = leq(io.retire, UInt<1>("h01")) @[CSR.scala 470:38] + node _T_2375 = or(_T_2372, _T_2374) @[CSR.scala 470:25] + node _T_2376 = or(_T_2375, reset) @[CSR.scala 470:9] + node _T_2378 = eq(_T_2376, UInt<1>("h00")) @[CSR.scala 470:9] + when _T_2378 : @[CSR.scala 470:9] + printf(clock, UInt<1>(1), "Assertion failed\n at CSR.scala:470 assert(!io.singleStep || io.retire <= UInt(1))\n") @[CSR.scala 470:9] + stop(clock, UInt<1>(1), 1) @[CSR.scala 470:9] + skip @[CSR.scala 470:9] + node _T_2380 = eq(reg_singleStepped, UInt<1>("h00")) @[CSR.scala 471:10] + node _T_2382 = eq(io.retire, UInt<1>("h00")) @[CSR.scala 471:42] + node _T_2383 = or(_T_2380, _T_2382) @[CSR.scala 471:29] + node _T_2384 = or(_T_2383, reset) @[CSR.scala 471:9] + node _T_2386 = eq(_T_2384, UInt<1>("h00")) @[CSR.scala 471:9] + when _T_2386 : @[CSR.scala 471:9] + printf(clock, UInt<1>(1), "Assertion failed\n at CSR.scala:471 assert(!reg_singleStepped || io.retire === UInt(0))\n") @[CSR.scala 471:9] + stop(clock, UInt<1>(1), 1) @[CSR.scala 471:9] + skip @[CSR.scala 471:9] + when exception : @[CSR.scala 473:20] + node _T_2387 = not(io.pc) @[CSR.scala 474:17] + node _T_2389 = or(_T_2387, UInt<1>("h01")) @[CSR.scala 474:24] + node _T_2390 = not(_T_2389) @[CSR.scala 474:15] + node _T_2391 = dshr(read_mstatus, reg_mstatus.prv) @[CSR.scala 475:27] + node _T_2392 = bits(_T_2391, 0, 0) @[CSR.scala 475:27] + node _T_2400 = eq(cause, UInt<2>("h03")) @[Package.scala 7:47] + node _T_2401 = eq(cause, UInt<3>("h04")) @[Package.scala 7:47] + node _T_2402 = eq(cause, UInt<3>("h06")) @[Package.scala 7:47] + node _T_2403 = eq(cause, UInt<1>("h00")) @[Package.scala 7:47] + node _T_2404 = eq(cause, UInt<3>("h05")) @[Package.scala 7:47] + node _T_2405 = eq(cause, UInt<3>("h07")) @[Package.scala 7:47] + node _T_2406 = eq(cause, UInt<1>("h01")) @[Package.scala 7:47] + node _T_2407 = or(_T_2400, _T_2401) @[Package.scala 7:62] + node _T_2408 = or(_T_2407, _T_2402) @[Package.scala 7:62] + node _T_2409 = or(_T_2408, _T_2403) @[Package.scala 7:62] + node _T_2410 = or(_T_2409, _T_2404) @[Package.scala 7:62] + node _T_2411 = or(_T_2410, _T_2405) @[Package.scala 7:62] + node _T_2412 = or(_T_2411, _T_2406) @[Package.scala 7:62] + when trapToDebug : @[CSR.scala 481:24] + reg_debug <= UInt<1>("h01") @[CSR.scala 482:17] + reg_dpc <= _T_2390 @[CSR.scala 483:15] + node _T_2418 = mux(causeIsDebugTrigger, UInt<2>("h02"), UInt<1>("h01")) @[CSR.scala 484:84] + node _T_2419 = mux(causeIsDebugInt, UInt<2>("h03"), _T_2418) @[CSR.scala 484:54] + node _T_2420 = mux(reg_singleStepped, UInt<3>("h04"), _T_2419) @[CSR.scala 484:28] + reg_dcsr.cause <= _T_2420 @[CSR.scala 484:22] + reg_dcsr.prv <= reg_mstatus.prv @[CSR.scala 485:20] + skip @[CSR.scala 481:24] + node _T_2422 = eq(trapToDebug, UInt<1>("h00")) @[CSR.scala 481:24] + node _T_2423 = and(_T_2422, delegate) @[CSR.scala 486:27] + when _T_2423 : @[CSR.scala 486:27] + node _T_2424 = not(_T_2390) @[CSR.scala 714:28] + node _T_2425 = bits(reg_misa, 2, 2) @[CSR.scala 714:46] + node _T_2427 = eq(_T_2425, UInt<1>("h00")) @[CSR.scala 714:37] + node _T_2429 = cat(_T_2427, UInt<1>("h01")) @[Cat.scala 30:58] + node _T_2430 = or(_T_2424, _T_2429) @[CSR.scala 714:31] + node _T_2431 = not(_T_2430) @[CSR.scala 714:26] + reg_sepc <= _T_2431 @[CSR.scala 487:16] + reg_scause <= cause @[CSR.scala 488:18] + when _T_2412 : @[CSR.scala 489:28] + reg_sbadaddr <= io.badaddr @[CSR.scala 489:43] + skip @[CSR.scala 489:28] + reg_mstatus.spie <= _T_2392 @[CSR.scala 490:24] + reg_mstatus.spp <= reg_mstatus.prv @[CSR.scala 491:23] + reg_mstatus.sie <= UInt<1>("h00") @[CSR.scala 492:23] + new_prv <= UInt<1>("h01") @[CSR.scala 493:15] + skip @[CSR.scala 486:27] + node _T_2435 = eq(trapToDebug, UInt<1>("h00")) @[CSR.scala 481:24] + node _T_2437 = eq(delegate, UInt<1>("h00")) @[CSR.scala 486:27] + node _T_2438 = and(_T_2435, _T_2437) @[CSR.scala 486:27] + when _T_2438 : @[CSR.scala 494:17] + node _T_2439 = not(_T_2390) @[CSR.scala 714:28] + node _T_2440 = bits(reg_misa, 2, 2) @[CSR.scala 714:46] + node _T_2442 = eq(_T_2440, UInt<1>("h00")) @[CSR.scala 714:37] + node _T_2444 = cat(_T_2442, UInt<1>("h01")) @[Cat.scala 30:58] + node _T_2445 = or(_T_2439, _T_2444) @[CSR.scala 714:31] + node _T_2446 = not(_T_2445) @[CSR.scala 714:26] + reg_mepc <= _T_2446 @[CSR.scala 495:16] + reg_mcause <= cause @[CSR.scala 496:18] + when _T_2412 : @[CSR.scala 497:28] + reg_mbadaddr <= io.badaddr @[CSR.scala 497:43] + skip @[CSR.scala 497:28] + reg_mstatus.mpie <= _T_2392 @[CSR.scala 498:24] + reg_mstatus.mpp <= reg_mstatus.prv @[CSR.scala 499:23] + reg_mstatus.mie <= UInt<1>("h00") @[CSR.scala 500:23] + new_prv <= UInt<2>("h03") @[CSR.scala 501:15] + skip @[CSR.scala 494:17] + skip @[CSR.scala 473:20] + when insn_ret : @[CSR.scala 505:19] + node _T_2450 = bits(io.rw.addr, 9, 9) @[CSR.scala 506:39] + node _T_2452 = eq(_T_2450, UInt<1>("h00")) @[CSR.scala 506:28] + node _T_2453 = and(UInt<1>("h01"), _T_2452) @[CSR.scala 506:25] + when _T_2453 : @[CSR.scala 506:44] + node _T_2454 = bits(reg_mstatus.spp, 0, 0) @[CSR.scala 507:29] + when _T_2454 : @[CSR.scala 507:37] + reg_mstatus.sie <= reg_mstatus.spie @[CSR.scala 507:55] + skip @[CSR.scala 507:37] + reg_mstatus.spie <= UInt<1>("h01") @[CSR.scala 508:24] + reg_mstatus.spp <= UInt<1>("h00") @[CSR.scala 509:23] + new_prv <= reg_mstatus.spp @[CSR.scala 510:15] + io.evec <= reg_sepc @[CSR.scala 511:15] + skip @[CSR.scala 506:44] + node _T_2458 = bits(io.rw.addr, 10, 10) @[CSR.scala 512:47] + node _T_2459 = and(UInt<1>("h01"), _T_2458) @[CSR.scala 512:34] + node _T_2461 = eq(_T_2453, UInt<1>("h00")) @[CSR.scala 506:44] + node _T_2462 = and(_T_2461, _T_2459) @[CSR.scala 512:53] + when _T_2462 : @[CSR.scala 512:53] + new_prv <= reg_dcsr.prv @[CSR.scala 513:15] + reg_debug <= UInt<1>("h00") @[CSR.scala 514:17] + io.evec <= reg_dpc @[CSR.scala 515:15] + skip @[CSR.scala 512:53] + node _T_2465 = eq(_T_2453, UInt<1>("h00")) @[CSR.scala 506:44] + node _T_2467 = eq(_T_2459, UInt<1>("h00")) @[CSR.scala 512:53] + node _T_2468 = and(_T_2465, _T_2467) @[CSR.scala 512:53] + when _T_2468 : @[CSR.scala 516:17] + node _T_2469 = bits(reg_mstatus.mpp, 1, 1) @[CSR.scala 517:28] + when _T_2469 : @[CSR.scala 517:33] + reg_mstatus.mie <= reg_mstatus.mpie @[CSR.scala 517:51] + skip @[CSR.scala 517:33] + node _T_2471 = bits(reg_mstatus.mpp, 0, 0) @[CSR.scala 518:50] + node _T_2472 = and(UInt<1>("h01"), _T_2471) @[CSR.scala 518:32] + node _T_2474 = eq(_T_2469, UInt<1>("h00")) @[CSR.scala 517:33] + node _T_2475 = and(_T_2474, _T_2472) @[CSR.scala 518:55] + when _T_2475 : @[CSR.scala 518:55] + reg_mstatus.sie <= reg_mstatus.mpie @[CSR.scala 518:73] + skip @[CSR.scala 518:55] + reg_mstatus.mpie <= UInt<1>("h01") @[CSR.scala 519:24] + node _T_2479 = eq(UInt<1>("h00"), UInt<2>("h02")) @[CSR.scala 697:27] + node _T_2481 = mux(_T_2479, UInt<1>("h00"), UInt<1>("h00")) @[CSR.scala 697:21] + reg_mstatus.mpp <= _T_2481 @[CSR.scala 520:23] + new_prv <= reg_mstatus.mpp @[CSR.scala 521:15] + io.evec <= reg_mepc @[CSR.scala 522:15] + skip @[CSR.scala 516:17] + skip @[CSR.scala 505:19] + io.time <= _T_950 @[CSR.scala 526:11] + io.csr_stall <= reg_wfi @[CSR.scala 527:16] + node _T_2483 = mux(_T_1467, reg_tselect, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2485 = mux(_T_1469, _T_1304, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2487 = mux(_T_1471, _T_1345, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2489 = mux(_T_1473, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2491 = mux(_T_1475, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2493 = mux(_T_1477, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2495 = mux(_T_1479, _T_950, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2497 = mux(_T_1481, _T_939, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2499 = mux(_T_1483, reg_misa, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2501 = mux(_T_1485, read_mstatus, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2503 = mux(_T_1487, reg_mtvec, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2505 = mux(_T_1489, read_mip, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2507 = mux(_T_1491, reg_mie, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2509 = mux(_T_1493, reg_mideleg, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2511 = mux(_T_1495, reg_medeleg, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2513 = mux(_T_1497, reg_mscratch, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2515 = mux(_T_1499, _T_1354, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2517 = mux(_T_1501, _T_1360, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2519 = mux(_T_1503, reg_mcause, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2521 = mux(_T_1505, io.hartid, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2523 = mux(_T_1507, _T_1376, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2525 = mux(_T_1509, reg_dpc, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2527 = mux(_T_1511, reg_dscratch, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2529 = mux(_T_1513, reg_fflags, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2531 = mux(_T_1515, reg_frm, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2533 = mux(_T_1517, _T_1377, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2535 = mux(_T_1519, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2537 = mux(_T_1521, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2539 = mux(_T_1523, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2541 = mux(_T_1525, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2543 = mux(_T_1527, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2545 = mux(_T_1529, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2547 = mux(_T_1531, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2549 = mux(_T_1533, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2551 = mux(_T_1535, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2553 = mux(_T_1537, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2555 = mux(_T_1539, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2557 = mux(_T_1541, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2559 = mux(_T_1543, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2561 = mux(_T_1545, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2563 = mux(_T_1547, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2565 = mux(_T_1549, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2567 = mux(_T_1551, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2569 = mux(_T_1553, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2571 = mux(_T_1555, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2573 = mux(_T_1557, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2575 = mux(_T_1559, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2577 = mux(_T_1561, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2579 = mux(_T_1563, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2581 = mux(_T_1565, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2583 = mux(_T_1567, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2585 = mux(_T_1569, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2587 = mux(_T_1571, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2589 = mux(_T_1573, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2591 = mux(_T_1575, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2593 = mux(_T_1577, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2595 = mux(_T_1579, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2597 = mux(_T_1581, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2599 = mux(_T_1583, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2601 = mux(_T_1585, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2603 = mux(_T_1587, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2605 = mux(_T_1589, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2607 = mux(_T_1591, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2609 = mux(_T_1593, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2611 = mux(_T_1595, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2613 = mux(_T_1597, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2615 = mux(_T_1599, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2617 = mux(_T_1601, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2619 = mux(_T_1603, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2621 = mux(_T_1605, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2623 = mux(_T_1607, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2625 = mux(_T_1609, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2627 = mux(_T_1611, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2629 = mux(_T_1613, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2631 = mux(_T_1615, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2633 = mux(_T_1617, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2635 = mux(_T_1619, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2637 = mux(_T_1621, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2639 = mux(_T_1623, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2641 = mux(_T_1625, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2643 = mux(_T_1627, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2645 = mux(_T_1629, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2647 = mux(_T_1631, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2649 = mux(_T_1633, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2651 = mux(_T_1635, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2653 = mux(_T_1637, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2655 = mux(_T_1639, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2657 = mux(_T_1641, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2659 = mux(_T_1643, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2661 = mux(_T_1645, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2663 = mux(_T_1647, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2665 = mux(_T_1649, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2667 = mux(_T_1651, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2669 = mux(_T_1653, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2671 = mux(_T_1655, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2673 = mux(_T_1657, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2675 = mux(_T_1659, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2677 = mux(_T_1661, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2679 = mux(_T_1663, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2681 = mux(_T_1665, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2683 = mux(_T_1667, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2685 = mux(_T_1669, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2687 = mux(_T_1671, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2689 = mux(_T_1673, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2691 = mux(_T_1675, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2693 = mux(_T_1677, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2695 = mux(_T_1679, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2697 = mux(_T_1681, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2699 = mux(_T_1683, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2701 = mux(_T_1685, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2703 = mux(_T_1687, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2705 = mux(_T_1689, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2707 = mux(_T_1691, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2709 = mux(_T_1693, _T_1445, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2711 = mux(_T_1695, _T_1381, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2713 = mux(_T_1697, _T_1380, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2715 = mux(_T_1699, reg_sscratch, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2717 = mux(_T_1701, reg_scause, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2719 = mux(_T_1703, _T_1451, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2721 = mux(_T_1705, _T_1453, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2723 = mux(_T_1707, _T_1459, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2725 = mux(_T_1709, _T_1465, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2727 = mux(_T_1711, reg_scounteren, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2729 = mux(_T_1713, reg_mcounteren, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2731 = mux(_T_1715, _T_950, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2733 = mux(_T_1717, _T_939, UInt<1>("h00")) @[Mux.scala 19:72] + node _T_2735 = or(_T_2483, _T_2485) @[Mux.scala 19:72] + node _T_2736 = or(_T_2735, _T_2487) @[Mux.scala 19:72] + node _T_2737 = or(_T_2736, _T_2489) @[Mux.scala 19:72] + node _T_2738 = or(_T_2737, _T_2491) @[Mux.scala 19:72] + node _T_2739 = or(_T_2738, _T_2493) @[Mux.scala 19:72] + node _T_2740 = or(_T_2739, _T_2495) @[Mux.scala 19:72] + node _T_2741 = or(_T_2740, _T_2497) @[Mux.scala 19:72] + node _T_2742 = or(_T_2741, _T_2499) @[Mux.scala 19:72] + node _T_2743 = or(_T_2742, _T_2501) @[Mux.scala 19:72] + node _T_2744 = or(_T_2743, _T_2503) @[Mux.scala 19:72] + node _T_2745 = or(_T_2744, _T_2505) @[Mux.scala 19:72] + node _T_2746 = or(_T_2745, _T_2507) @[Mux.scala 19:72] + node _T_2747 = or(_T_2746, _T_2509) @[Mux.scala 19:72] + node _T_2748 = or(_T_2747, _T_2511) @[Mux.scala 19:72] + node _T_2749 = or(_T_2748, _T_2513) @[Mux.scala 19:72] + node _T_2750 = or(_T_2749, _T_2515) @[Mux.scala 19:72] + node _T_2751 = or(_T_2750, _T_2517) @[Mux.scala 19:72] + node _T_2752 = or(_T_2751, _T_2519) @[Mux.scala 19:72] + node _T_2753 = or(_T_2752, _T_2521) @[Mux.scala 19:72] + node _T_2754 = or(_T_2753, _T_2523) @[Mux.scala 19:72] + node _T_2755 = or(_T_2754, _T_2525) @[Mux.scala 19:72] + node _T_2756 = or(_T_2755, _T_2527) @[Mux.scala 19:72] + node _T_2757 = or(_T_2756, _T_2529) @[Mux.scala 19:72] + node _T_2758 = or(_T_2757, _T_2531) @[Mux.scala 19:72] + node _T_2759 = or(_T_2758, _T_2533) @[Mux.scala 19:72] + node _T_2760 = or(_T_2759, _T_2535) @[Mux.scala 19:72] + node _T_2761 = or(_T_2760, _T_2537) @[Mux.scala 19:72] + node _T_2762 = or(_T_2761, _T_2539) @[Mux.scala 19:72] + node _T_2763 = or(_T_2762, _T_2541) @[Mux.scala 19:72] + node _T_2764 = or(_T_2763, _T_2543) @[Mux.scala 19:72] + node _T_2765 = or(_T_2764, _T_2545) @[Mux.scala 19:72] + node _T_2766 = or(_T_2765, _T_2547) @[Mux.scala 19:72] + node _T_2767 = or(_T_2766, _T_2549) @[Mux.scala 19:72] + node _T_2768 = or(_T_2767, _T_2551) @[Mux.scala 19:72] + node _T_2769 = or(_T_2768, _T_2553) @[Mux.scala 19:72] + node _T_2770 = or(_T_2769, _T_2555) @[Mux.scala 19:72] + node _T_2771 = or(_T_2770, _T_2557) @[Mux.scala 19:72] + node _T_2772 = or(_T_2771, _T_2559) @[Mux.scala 19:72] + node _T_2773 = or(_T_2772, _T_2561) @[Mux.scala 19:72] + node _T_2774 = or(_T_2773, _T_2563) @[Mux.scala 19:72] + node _T_2775 = or(_T_2774, _T_2565) @[Mux.scala 19:72] + node _T_2776 = or(_T_2775, _T_2567) @[Mux.scala 19:72] + node _T_2777 = or(_T_2776, _T_2569) @[Mux.scala 19:72] + node _T_2778 = or(_T_2777, _T_2571) @[Mux.scala 19:72] + node _T_2779 = or(_T_2778, _T_2573) @[Mux.scala 19:72] + node _T_2780 = or(_T_2779, _T_2575) @[Mux.scala 19:72] + node _T_2781 = or(_T_2780, _T_2577) @[Mux.scala 19:72] + node _T_2782 = or(_T_2781, _T_2579) @[Mux.scala 19:72] + node _T_2783 = or(_T_2782, _T_2581) @[Mux.scala 19:72] + node _T_2784 = or(_T_2783, _T_2583) @[Mux.scala 19:72] + node _T_2785 = or(_T_2784, _T_2585) @[Mux.scala 19:72] + node _T_2786 = or(_T_2785, _T_2587) @[Mux.scala 19:72] + node _T_2787 = or(_T_2786, _T_2589) @[Mux.scala 19:72] + node _T_2788 = or(_T_2787, _T_2591) @[Mux.scala 19:72] + node _T_2789 = or(_T_2788, _T_2593) @[Mux.scala 19:72] + node _T_2790 = or(_T_2789, _T_2595) @[Mux.scala 19:72] + node _T_2791 = or(_T_2790, _T_2597) @[Mux.scala 19:72] + node _T_2792 = or(_T_2791, _T_2599) @[Mux.scala 19:72] + node _T_2793 = or(_T_2792, _T_2601) @[Mux.scala 19:72] + node _T_2794 = or(_T_2793, _T_2603) @[Mux.scala 19:72] + node _T_2795 = or(_T_2794, _T_2605) @[Mux.scala 19:72] + node _T_2796 = or(_T_2795, _T_2607) @[Mux.scala 19:72] + node _T_2797 = or(_T_2796, _T_2609) @[Mux.scala 19:72] + node _T_2798 = or(_T_2797, _T_2611) @[Mux.scala 19:72] + node _T_2799 = or(_T_2798, _T_2613) @[Mux.scala 19:72] + node _T_2800 = or(_T_2799, _T_2615) @[Mux.scala 19:72] + node _T_2801 = or(_T_2800, _T_2617) @[Mux.scala 19:72] + node _T_2802 = or(_T_2801, _T_2619) @[Mux.scala 19:72] + node _T_2803 = or(_T_2802, _T_2621) @[Mux.scala 19:72] + node _T_2804 = or(_T_2803, _T_2623) @[Mux.scala 19:72] + node _T_2805 = or(_T_2804, _T_2625) @[Mux.scala 19:72] + node _T_2806 = or(_T_2805, _T_2627) @[Mux.scala 19:72] + node _T_2807 = or(_T_2806, _T_2629) @[Mux.scala 19:72] + node _T_2808 = or(_T_2807, _T_2631) @[Mux.scala 19:72] + node _T_2809 = or(_T_2808, _T_2633) @[Mux.scala 19:72] + node _T_2810 = or(_T_2809, _T_2635) @[Mux.scala 19:72] + node _T_2811 = or(_T_2810, _T_2637) @[Mux.scala 19:72] + node _T_2812 = or(_T_2811, _T_2639) @[Mux.scala 19:72] + node _T_2813 = or(_T_2812, _T_2641) @[Mux.scala 19:72] + node _T_2814 = or(_T_2813, _T_2643) @[Mux.scala 19:72] + node _T_2815 = or(_T_2814, _T_2645) @[Mux.scala 19:72] + node _T_2816 = or(_T_2815, _T_2647) @[Mux.scala 19:72] + node _T_2817 = or(_T_2816, _T_2649) @[Mux.scala 19:72] + node _T_2818 = or(_T_2817, _T_2651) @[Mux.scala 19:72] + node _T_2819 = or(_T_2818, _T_2653) @[Mux.scala 19:72] + node _T_2820 = or(_T_2819, _T_2655) @[Mux.scala 19:72] + node _T_2821 = or(_T_2820, _T_2657) @[Mux.scala 19:72] + node _T_2822 = or(_T_2821, _T_2659) @[Mux.scala 19:72] + node _T_2823 = or(_T_2822, _T_2661) @[Mux.scala 19:72] + node _T_2824 = or(_T_2823, _T_2663) @[Mux.scala 19:72] + node _T_2825 = or(_T_2824, _T_2665) @[Mux.scala 19:72] + node _T_2826 = or(_T_2825, _T_2667) @[Mux.scala 19:72] + node _T_2827 = or(_T_2826, _T_2669) @[Mux.scala 19:72] + node _T_2828 = or(_T_2827, _T_2671) @[Mux.scala 19:72] + node _T_2829 = or(_T_2828, _T_2673) @[Mux.scala 19:72] + node _T_2830 = or(_T_2829, _T_2675) @[Mux.scala 19:72] + node _T_2831 = or(_T_2830, _T_2677) @[Mux.scala 19:72] + node _T_2832 = or(_T_2831, _T_2679) @[Mux.scala 19:72] + node _T_2833 = or(_T_2832, _T_2681) @[Mux.scala 19:72] + node _T_2834 = or(_T_2833, _T_2683) @[Mux.scala 19:72] + node _T_2835 = or(_T_2834, _T_2685) @[Mux.scala 19:72] + node _T_2836 = or(_T_2835, _T_2687) @[Mux.scala 19:72] + node _T_2837 = or(_T_2836, _T_2689) @[Mux.scala 19:72] + node _T_2838 = or(_T_2837, _T_2691) @[Mux.scala 19:72] + node _T_2839 = or(_T_2838, _T_2693) @[Mux.scala 19:72] + node _T_2840 = or(_T_2839, _T_2695) @[Mux.scala 19:72] + node _T_2841 = or(_T_2840, _T_2697) @[Mux.scala 19:72] + node _T_2842 = or(_T_2841, _T_2699) @[Mux.scala 19:72] + node _T_2843 = or(_T_2842, _T_2701) @[Mux.scala 19:72] + node _T_2844 = or(_T_2843, _T_2703) @[Mux.scala 19:72] + node _T_2845 = or(_T_2844, _T_2705) @[Mux.scala 19:72] + node _T_2846 = or(_T_2845, _T_2707) @[Mux.scala 19:72] + node _T_2847 = or(_T_2846, _T_2709) @[Mux.scala 19:72] + node _T_2848 = or(_T_2847, _T_2711) @[Mux.scala 19:72] + node _T_2849 = or(_T_2848, _T_2713) @[Mux.scala 19:72] + node _T_2850 = or(_T_2849, _T_2715) @[Mux.scala 19:72] + node _T_2851 = or(_T_2850, _T_2717) @[Mux.scala 19:72] + node _T_2852 = or(_T_2851, _T_2719) @[Mux.scala 19:72] + node _T_2853 = or(_T_2852, _T_2721) @[Mux.scala 19:72] + node _T_2854 = or(_T_2853, _T_2723) @[Mux.scala 19:72] + node _T_2855 = or(_T_2854, _T_2725) @[Mux.scala 19:72] + node _T_2856 = or(_T_2855, _T_2727) @[Mux.scala 19:72] + node _T_2857 = or(_T_2856, _T_2729) @[Mux.scala 19:72] + node _T_2858 = or(_T_2857, _T_2731) @[Mux.scala 19:72] + node _T_2859 = or(_T_2858, _T_2733) @[Mux.scala 19:72] + wire _T_2861 : UInt @[Mux.scala 19:72] + _T_2861 is invalid @[Mux.scala 19:72] + _T_2861 <= _T_2859 @[Mux.scala 19:72] + io.rw.rdata <= _T_2861 @[CSR.scala 529:15] + io.fcsr_rm <= reg_frm @[CSR.scala 531:14] + when io.fcsr_flags.valid : @[CSR.scala 532:30] + node _T_2862 = or(reg_fflags, io.fcsr_flags.bits) @[CSR.scala 533:30] + reg_fflags <= _T_2862 @[CSR.scala 533:16] + skip @[CSR.scala 532:30] + node _T_2866 = eq(io.rw.cmd, UInt<3>("h02")) @[Package.scala 7:47] + node _T_2867 = eq(io.rw.cmd, UInt<3>("h03")) @[Package.scala 7:47] + node _T_2868 = eq(io.rw.cmd, UInt<3>("h01")) @[Package.scala 7:47] + node _T_2869 = or(_T_2866, _T_2867) @[Package.scala 7:62] + node _T_2870 = or(_T_2869, _T_2868) @[Package.scala 7:62] + when _T_2870 : @[CSR.scala 536:49] + when _T_1485 : @[CSR.scala 537:39] + wire _T_2929 : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} @[CSR.scala 538:47] + _T_2929 is invalid @[CSR.scala 538:47] + wire _T_2959 : UInt<99> + _T_2959 is invalid + _T_2959 <= wdata + node _T_2960 = bits(_T_2959, 0, 0) @[CSR.scala 538:47] + _T_2929.uie <= _T_2960 @[CSR.scala 538:47] + node _T_2961 = bits(_T_2959, 1, 1) @[CSR.scala 538:47] + _T_2929.sie <= _T_2961 @[CSR.scala 538:47] + node _T_2962 = bits(_T_2959, 2, 2) @[CSR.scala 538:47] + _T_2929.hie <= _T_2962 @[CSR.scala 538:47] + node _T_2963 = bits(_T_2959, 3, 3) @[CSR.scala 538:47] + _T_2929.mie <= _T_2963 @[CSR.scala 538:47] + node _T_2964 = bits(_T_2959, 4, 4) @[CSR.scala 538:47] + _T_2929.upie <= _T_2964 @[CSR.scala 538:47] + node _T_2965 = bits(_T_2959, 5, 5) @[CSR.scala 538:47] + _T_2929.spie <= _T_2965 @[CSR.scala 538:47] + node _T_2966 = bits(_T_2959, 6, 6) @[CSR.scala 538:47] + _T_2929.hpie <= _T_2966 @[CSR.scala 538:47] + node _T_2967 = bits(_T_2959, 7, 7) @[CSR.scala 538:47] + _T_2929.mpie <= _T_2967 @[CSR.scala 538:47] + node _T_2968 = bits(_T_2959, 8, 8) @[CSR.scala 538:47] + _T_2929.spp <= _T_2968 @[CSR.scala 538:47] + node _T_2969 = bits(_T_2959, 10, 9) @[CSR.scala 538:47] + _T_2929.hpp <= _T_2969 @[CSR.scala 538:47] + node _T_2970 = bits(_T_2959, 12, 11) @[CSR.scala 538:47] + _T_2929.mpp <= _T_2970 @[CSR.scala 538:47] + node _T_2971 = bits(_T_2959, 14, 13) @[CSR.scala 538:47] + _T_2929.fs <= _T_2971 @[CSR.scala 538:47] + node _T_2972 = bits(_T_2959, 16, 15) @[CSR.scala 538:47] + _T_2929.xs <= _T_2972 @[CSR.scala 538:47] + node _T_2973 = bits(_T_2959, 17, 17) @[CSR.scala 538:47] + _T_2929.mprv <= _T_2973 @[CSR.scala 538:47] + node _T_2974 = bits(_T_2959, 18, 18) @[CSR.scala 538:47] + _T_2929.pum <= _T_2974 @[CSR.scala 538:47] + node _T_2975 = bits(_T_2959, 19, 19) @[CSR.scala 538:47] + _T_2929.mxr <= _T_2975 @[CSR.scala 538:47] + node _T_2976 = bits(_T_2959, 20, 20) @[CSR.scala 538:47] + _T_2929.tvm <= _T_2976 @[CSR.scala 538:47] + node _T_2977 = bits(_T_2959, 21, 21) @[CSR.scala 538:47] + _T_2929.tw <= _T_2977 @[CSR.scala 538:47] + node _T_2978 = bits(_T_2959, 22, 22) @[CSR.scala 538:47] + _T_2929.tsr <= _T_2978 @[CSR.scala 538:47] + node _T_2979 = bits(_T_2959, 30, 23) @[CSR.scala 538:47] + _T_2929.zero1 <= _T_2979 @[CSR.scala 538:47] + node _T_2980 = bits(_T_2959, 31, 31) @[CSR.scala 538:47] + _T_2929.sd_rv32 <= _T_2980 @[CSR.scala 538:47] + node _T_2981 = bits(_T_2959, 33, 32) @[CSR.scala 538:47] + _T_2929.uxl <= _T_2981 @[CSR.scala 538:47] + node _T_2982 = bits(_T_2959, 35, 34) @[CSR.scala 538:47] + _T_2929.sxl <= _T_2982 @[CSR.scala 538:47] + node _T_2983 = bits(_T_2959, 62, 36) @[CSR.scala 538:47] + _T_2929.zero2 <= _T_2983 @[CSR.scala 538:47] + node _T_2984 = bits(_T_2959, 63, 63) @[CSR.scala 538:47] + _T_2929.sd <= _T_2984 @[CSR.scala 538:47] + node _T_2985 = bits(_T_2959, 65, 64) @[CSR.scala 538:47] + _T_2929.prv <= _T_2985 @[CSR.scala 538:47] + node _T_2986 = bits(_T_2959, 97, 66) @[CSR.scala 538:47] + _T_2929.isa <= _T_2986 @[CSR.scala 538:47] + node _T_2987 = bits(_T_2959, 98, 98) @[CSR.scala 538:47] + _T_2929.debug <= _T_2987 @[CSR.scala 538:47] + reg_mstatus.mie <= _T_2929.mie @[CSR.scala 539:23] + reg_mstatus.mpie <= _T_2929.mpie @[CSR.scala 540:24] + reg_mstatus.mprv <= _T_2929.mprv @[CSR.scala 543:26] + reg_mstatus.mpp <= _T_2929.mpp @[CSR.scala 544:25] + reg_mstatus.mxr <= _T_2929.mxr @[CSR.scala 545:25] + reg_mstatus.pum <= _T_2929.pum @[CSR.scala 547:27] + reg_mstatus.spp <= _T_2929.spp @[CSR.scala 548:27] + reg_mstatus.spie <= _T_2929.spie @[CSR.scala 549:28] + reg_mstatus.sie <= _T_2929.sie @[CSR.scala 550:27] + reg_mstatus.tw <= _T_2929.tw @[CSR.scala 551:26] + reg_mstatus.tvm <= _T_2929.tvm @[CSR.scala 552:27] + reg_mstatus.tsr <= _T_2929.tsr @[CSR.scala 553:27] + node _T_2989 = neq(_T_2929.fs, UInt<1>("h00")) @[CSR.scala 557:73] + node _T_2990 = bits(_T_2989, 0, 0) @[Bitwise.scala 71:15] + node _T_2993 = mux(_T_2990, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 71:12] + reg_mstatus.fs <= _T_2993 @[CSR.scala 557:47] + skip @[CSR.scala 537:39] + when _T_1483 : @[CSR.scala 560:36] + node _T_2995 = bits(wdata, 5, 5) @[CSR.scala 562:20] + node _T_2996 = not(wdata) @[CSR.scala 563:21] + node _T_2998 = eq(_T_2995, UInt<1>("h00")) @[CSR.scala 563:31] + node _T_2999 = shl(_T_2998, 3) @[CSR.scala 563:34] + node _T_3000 = or(_T_2996, _T_2999) @[CSR.scala 563:28] + node _T_3001 = not(_T_3000) @[CSR.scala 563:19] + node _T_3002 = and(_T_3001, UInt<13>("h0102d")) @[CSR.scala 563:51] + node _T_3003 = not(UInt<13>("h0102d")) @[CSR.scala 563:71] + node _T_3004 = and(reg_misa, _T_3003) @[CSR.scala 563:69] + node _T_3005 = or(_T_3002, _T_3004) @[CSR.scala 563:58] + reg_misa <= _T_3005 @[CSR.scala 563:16] + skip @[CSR.scala 560:36] + when _T_1489 : @[CSR.scala 565:35] + wire _T_3034 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[CSR.scala 566:39] + _T_3034 is invalid @[CSR.scala 566:39] + wire _T_3049 : UInt<13> + _T_3049 is invalid + _T_3049 <= wdata + node _T_3050 = bits(_T_3049, 0, 0) @[CSR.scala 566:39] + _T_3034.usip <= _T_3050 @[CSR.scala 566:39] + node _T_3051 = bits(_T_3049, 1, 1) @[CSR.scala 566:39] + _T_3034.ssip <= _T_3051 @[CSR.scala 566:39] + node _T_3052 = bits(_T_3049, 2, 2) @[CSR.scala 566:39] + _T_3034.hsip <= _T_3052 @[CSR.scala 566:39] + node _T_3053 = bits(_T_3049, 3, 3) @[CSR.scala 566:39] + _T_3034.msip <= _T_3053 @[CSR.scala 566:39] + node _T_3054 = bits(_T_3049, 4, 4) @[CSR.scala 566:39] + _T_3034.utip <= _T_3054 @[CSR.scala 566:39] + node _T_3055 = bits(_T_3049, 5, 5) @[CSR.scala 566:39] + _T_3034.stip <= _T_3055 @[CSR.scala 566:39] + node _T_3056 = bits(_T_3049, 6, 6) @[CSR.scala 566:39] + _T_3034.htip <= _T_3056 @[CSR.scala 566:39] + node _T_3057 = bits(_T_3049, 7, 7) @[CSR.scala 566:39] + _T_3034.mtip <= _T_3057 @[CSR.scala 566:39] + node _T_3058 = bits(_T_3049, 8, 8) @[CSR.scala 566:39] + _T_3034.ueip <= _T_3058 @[CSR.scala 566:39] + node _T_3059 = bits(_T_3049, 9, 9) @[CSR.scala 566:39] + _T_3034.seip <= _T_3059 @[CSR.scala 566:39] + node _T_3060 = bits(_T_3049, 10, 10) @[CSR.scala 566:39] + _T_3034.heip <= _T_3060 @[CSR.scala 566:39] + node _T_3061 = bits(_T_3049, 11, 11) @[CSR.scala 566:39] + _T_3034.meip <= _T_3061 @[CSR.scala 566:39] + node _T_3062 = bits(_T_3049, 12, 12) @[CSR.scala 566:39] + _T_3034.rocc <= _T_3062 @[CSR.scala 566:39] + reg_mip.ssip <= _T_3034.ssip @[CSR.scala 568:22] + reg_mip.stip <= _T_3034.stip @[CSR.scala 569:22] + skip @[CSR.scala 565:35] + when _T_1491 : @[CSR.scala 572:40] + node _T_3063 = and(wdata, supported_interrupts) @[CSR.scala 572:59] + reg_mie <= _T_3063 @[CSR.scala 572:50] + skip @[CSR.scala 572:40] + when _T_1499 : @[CSR.scala 573:40] + node _T_3064 = not(wdata) @[CSR.scala 714:28] + node _T_3065 = bits(reg_misa, 2, 2) @[CSR.scala 714:46] + node _T_3067 = eq(_T_3065, UInt<1>("h00")) @[CSR.scala 714:37] + node _T_3069 = cat(_T_3067, UInt<1>("h01")) @[Cat.scala 30:58] + node _T_3070 = or(_T_3064, _T_3069) @[CSR.scala 714:31] + node _T_3071 = not(_T_3070) @[CSR.scala 714:26] + reg_mepc <= _T_3071 @[CSR.scala 573:51] + skip @[CSR.scala 573:40] + when _T_1497 : @[CSR.scala 574:40] + reg_mscratch <= wdata @[CSR.scala 574:55] + skip @[CSR.scala 574:40] + when _T_1487 : @[CSR.scala 576:40] + node _T_3072 = shr(wdata, 2) @[CSR.scala 576:61] + node _T_3073 = shl(_T_3072, 2) @[CSR.scala 576:66] + reg_mtvec <= _T_3073 @[CSR.scala 576:52] + skip @[CSR.scala 576:40] + when _T_1503 : @[CSR.scala 577:40] + node _T_3075 = and(wdata, UInt<64>("h0800000000000001f")) @[CSR.scala 577:62] + reg_mcause <= _T_3075 @[CSR.scala 577:53] + skip @[CSR.scala 577:40] + when _T_1501 : @[CSR.scala 578:40] + node _T_3076 = bits(wdata, 39, 0) @[CSR.scala 578:63] + reg_mbadaddr <= _T_3076 @[CSR.scala 578:55] + skip @[CSR.scala 578:40] + when _T_1479 : @[CSR.scala 711:31] + node _T_3077 = bits(wdata, 63, 0) @[CSR.scala 711:45] + _T_942 <= _T_3077 @[Counters.scala 67:11] + node _T_3078 = shr(_T_3077, 6) @[Counters.scala 68:28] + _T_945 <= _T_3078 @[Counters.scala 68:23] + skip @[CSR.scala 711:31] + when _T_1481 : @[CSR.scala 711:31] + node _T_3079 = bits(wdata, 63, 0) @[CSR.scala 711:45] + _T_931 <= _T_3079 @[Counters.scala 67:11] + node _T_3080 = shr(_T_3079, 6) @[Counters.scala 68:28] + _T_934 <= _T_3080 @[Counters.scala 68:23] + skip @[CSR.scala 711:31] + when _T_1513 : @[CSR.scala 588:40] + reg_fflags <= wdata @[CSR.scala 588:53] + skip @[CSR.scala 588:40] + when _T_1515 : @[CSR.scala 589:40] + reg_frm <= wdata @[CSR.scala 589:50] + skip @[CSR.scala 589:40] + when _T_1517 : @[CSR.scala 590:40] + reg_fflags <= wdata @[CSR.scala 590:53] + node _T_3081 = shr(wdata, 5) @[CSR.scala 590:80] + reg_frm <= _T_3081 @[CSR.scala 590:71] + skip @[CSR.scala 590:40] + when _T_1507 : @[CSR.scala 593:38] + wire _T_3118 : {xdebugver : UInt<2>, ndreset : UInt<1>, fullreset : UInt<1>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, debugint : UInt<1>, zero1 : UInt<1>, halt : UInt<1>, step : UInt<1>, prv : UInt<2>} @[CSR.scala 594:43] + _T_3118 is invalid @[CSR.scala 594:43] + wire _T_3137 : UInt<32> + _T_3137 is invalid + _T_3137 <= wdata + node _T_3138 = bits(_T_3137, 1, 0) @[CSR.scala 594:43] + _T_3118.prv <= _T_3138 @[CSR.scala 594:43] + node _T_3139 = bits(_T_3137, 2, 2) @[CSR.scala 594:43] + _T_3118.step <= _T_3139 @[CSR.scala 594:43] + node _T_3140 = bits(_T_3137, 3, 3) @[CSR.scala 594:43] + _T_3118.halt <= _T_3140 @[CSR.scala 594:43] + node _T_3141 = bits(_T_3137, 4, 4) @[CSR.scala 594:43] + _T_3118.zero1 <= _T_3141 @[CSR.scala 594:43] + node _T_3142 = bits(_T_3137, 5, 5) @[CSR.scala 594:43] + _T_3118.debugint <= _T_3142 @[CSR.scala 594:43] + node _T_3143 = bits(_T_3137, 8, 6) @[CSR.scala 594:43] + _T_3118.cause <= _T_3143 @[CSR.scala 594:43] + node _T_3144 = bits(_T_3137, 9, 9) @[CSR.scala 594:43] + _T_3118.stoptime <= _T_3144 @[CSR.scala 594:43] + node _T_3145 = bits(_T_3137, 10, 10) @[CSR.scala 594:43] + _T_3118.stopcycle <= _T_3145 @[CSR.scala 594:43] + node _T_3146 = bits(_T_3137, 11, 11) @[CSR.scala 594:43] + _T_3118.zero2 <= _T_3146 @[CSR.scala 594:43] + node _T_3147 = bits(_T_3137, 12, 12) @[CSR.scala 594:43] + _T_3118.ebreaku <= _T_3147 @[CSR.scala 594:43] + node _T_3148 = bits(_T_3137, 13, 13) @[CSR.scala 594:43] + _T_3118.ebreaks <= _T_3148 @[CSR.scala 594:43] + node _T_3149 = bits(_T_3137, 14, 14) @[CSR.scala 594:43] + _T_3118.ebreakh <= _T_3149 @[CSR.scala 594:43] + node _T_3150 = bits(_T_3137, 15, 15) @[CSR.scala 594:43] + _T_3118.ebreakm <= _T_3150 @[CSR.scala 594:43] + node _T_3151 = bits(_T_3137, 27, 16) @[CSR.scala 594:43] + _T_3118.zero3 <= _T_3151 @[CSR.scala 594:43] + node _T_3152 = bits(_T_3137, 28, 28) @[CSR.scala 594:43] + _T_3118.fullreset <= _T_3152 @[CSR.scala 594:43] + node _T_3153 = bits(_T_3137, 29, 29) @[CSR.scala 594:43] + _T_3118.ndreset <= _T_3153 @[CSR.scala 594:43] + node _T_3154 = bits(_T_3137, 31, 30) @[CSR.scala 594:43] + _T_3118.xdebugver <= _T_3154 @[CSR.scala 594:43] + reg_dcsr.halt <= _T_3118.halt @[CSR.scala 595:23] + reg_dcsr.step <= _T_3118.step @[CSR.scala 596:23] + reg_dcsr.ebreakm <= _T_3118.ebreakm @[CSR.scala 597:26] + reg_dcsr.ebreaks <= _T_3118.ebreaks @[CSR.scala 598:39] + reg_dcsr.ebreaku <= _T_3118.ebreaku @[CSR.scala 599:41] + reg_dcsr.prv <= _T_3118.prv @[CSR.scala 600:37] + skip @[CSR.scala 593:38] + when _T_1509 : @[CSR.scala 602:42] + node _T_3155 = not(wdata) @[CSR.scala 602:57] + node _T_3157 = or(_T_3155, UInt<1>("h01")) @[CSR.scala 602:64] + node _T_3158 = not(_T_3157) @[CSR.scala 602:55] + reg_dpc <= _T_3158 @[CSR.scala 602:52] + skip @[CSR.scala 602:42] + when _T_1511 : @[CSR.scala 603:42] + reg_dscratch <= wdata @[CSR.scala 603:57] + skip @[CSR.scala 603:42] + when _T_1693 : @[CSR.scala 606:41] + wire _T_3217 : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} @[CSR.scala 607:49] + _T_3217 is invalid @[CSR.scala 607:49] + wire _T_3247 : UInt<99> + _T_3247 is invalid + _T_3247 <= wdata + node _T_3248 = bits(_T_3247, 0, 0) @[CSR.scala 607:49] + _T_3217.uie <= _T_3248 @[CSR.scala 607:49] + node _T_3249 = bits(_T_3247, 1, 1) @[CSR.scala 607:49] + _T_3217.sie <= _T_3249 @[CSR.scala 607:49] + node _T_3250 = bits(_T_3247, 2, 2) @[CSR.scala 607:49] + _T_3217.hie <= _T_3250 @[CSR.scala 607:49] + node _T_3251 = bits(_T_3247, 3, 3) @[CSR.scala 607:49] + _T_3217.mie <= _T_3251 @[CSR.scala 607:49] + node _T_3252 = bits(_T_3247, 4, 4) @[CSR.scala 607:49] + _T_3217.upie <= _T_3252 @[CSR.scala 607:49] + node _T_3253 = bits(_T_3247, 5, 5) @[CSR.scala 607:49] + _T_3217.spie <= _T_3253 @[CSR.scala 607:49] + node _T_3254 = bits(_T_3247, 6, 6) @[CSR.scala 607:49] + _T_3217.hpie <= _T_3254 @[CSR.scala 607:49] + node _T_3255 = bits(_T_3247, 7, 7) @[CSR.scala 607:49] + _T_3217.mpie <= _T_3255 @[CSR.scala 607:49] + node _T_3256 = bits(_T_3247, 8, 8) @[CSR.scala 607:49] + _T_3217.spp <= _T_3256 @[CSR.scala 607:49] + node _T_3257 = bits(_T_3247, 10, 9) @[CSR.scala 607:49] + _T_3217.hpp <= _T_3257 @[CSR.scala 607:49] + node _T_3258 = bits(_T_3247, 12, 11) @[CSR.scala 607:49] + _T_3217.mpp <= _T_3258 @[CSR.scala 607:49] + node _T_3259 = bits(_T_3247, 14, 13) @[CSR.scala 607:49] + _T_3217.fs <= _T_3259 @[CSR.scala 607:49] + node _T_3260 = bits(_T_3247, 16, 15) @[CSR.scala 607:49] + _T_3217.xs <= _T_3260 @[CSR.scala 607:49] + node _T_3261 = bits(_T_3247, 17, 17) @[CSR.scala 607:49] + _T_3217.mprv <= _T_3261 @[CSR.scala 607:49] + node _T_3262 = bits(_T_3247, 18, 18) @[CSR.scala 607:49] + _T_3217.pum <= _T_3262 @[CSR.scala 607:49] + node _T_3263 = bits(_T_3247, 19, 19) @[CSR.scala 607:49] + _T_3217.mxr <= _T_3263 @[CSR.scala 607:49] + node _T_3264 = bits(_T_3247, 20, 20) @[CSR.scala 607:49] + _T_3217.tvm <= _T_3264 @[CSR.scala 607:49] + node _T_3265 = bits(_T_3247, 21, 21) @[CSR.scala 607:49] + _T_3217.tw <= _T_3265 @[CSR.scala 607:49] + node _T_3266 = bits(_T_3247, 22, 22) @[CSR.scala 607:49] + _T_3217.tsr <= _T_3266 @[CSR.scala 607:49] + node _T_3267 = bits(_T_3247, 30, 23) @[CSR.scala 607:49] + _T_3217.zero1 <= _T_3267 @[CSR.scala 607:49] + node _T_3268 = bits(_T_3247, 31, 31) @[CSR.scala 607:49] + _T_3217.sd_rv32 <= _T_3268 @[CSR.scala 607:49] + node _T_3269 = bits(_T_3247, 33, 32) @[CSR.scala 607:49] + _T_3217.uxl <= _T_3269 @[CSR.scala 607:49] + node _T_3270 = bits(_T_3247, 35, 34) @[CSR.scala 607:49] + _T_3217.sxl <= _T_3270 @[CSR.scala 607:49] + node _T_3271 = bits(_T_3247, 62, 36) @[CSR.scala 607:49] + _T_3217.zero2 <= _T_3271 @[CSR.scala 607:49] + node _T_3272 = bits(_T_3247, 63, 63) @[CSR.scala 607:49] + _T_3217.sd <= _T_3272 @[CSR.scala 607:49] + node _T_3273 = bits(_T_3247, 65, 64) @[CSR.scala 607:49] + _T_3217.prv <= _T_3273 @[CSR.scala 607:49] + node _T_3274 = bits(_T_3247, 97, 66) @[CSR.scala 607:49] + _T_3217.isa <= _T_3274 @[CSR.scala 607:49] + node _T_3275 = bits(_T_3247, 98, 98) @[CSR.scala 607:49] + _T_3217.debug <= _T_3275 @[CSR.scala 607:49] + reg_mstatus.sie <= _T_3217.sie @[CSR.scala 608:25] + reg_mstatus.spie <= _T_3217.spie @[CSR.scala 609:26] + reg_mstatus.spp <= _T_3217.spp @[CSR.scala 610:25] + reg_mstatus.pum <= _T_3217.pum @[CSR.scala 611:25] + node _T_3277 = neq(_T_3217.fs, UInt<1>("h00")) @[CSR.scala 612:50] + node _T_3278 = bits(_T_3277, 0, 0) @[Bitwise.scala 71:15] + node _T_3281 = mux(_T_3278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 71:12] + reg_mstatus.fs <= _T_3281 @[CSR.scala 612:24] + skip @[CSR.scala 606:41] + when _T_1695 : @[CSR.scala 615:37] + wire _T_3310 : {rocc : UInt<1>, meip : UInt<1>, heip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} @[CSR.scala 616:41] + _T_3310 is invalid @[CSR.scala 616:41] + wire _T_3325 : UInt<13> + _T_3325 is invalid + _T_3325 <= wdata + node _T_3326 = bits(_T_3325, 0, 0) @[CSR.scala 616:41] + _T_3310.usip <= _T_3326 @[CSR.scala 616:41] + node _T_3327 = bits(_T_3325, 1, 1) @[CSR.scala 616:41] + _T_3310.ssip <= _T_3327 @[CSR.scala 616:41] + node _T_3328 = bits(_T_3325, 2, 2) @[CSR.scala 616:41] + _T_3310.hsip <= _T_3328 @[CSR.scala 616:41] + node _T_3329 = bits(_T_3325, 3, 3) @[CSR.scala 616:41] + _T_3310.msip <= _T_3329 @[CSR.scala 616:41] + node _T_3330 = bits(_T_3325, 4, 4) @[CSR.scala 616:41] + _T_3310.utip <= _T_3330 @[CSR.scala 616:41] + node _T_3331 = bits(_T_3325, 5, 5) @[CSR.scala 616:41] + _T_3310.stip <= _T_3331 @[CSR.scala 616:41] + node _T_3332 = bits(_T_3325, 6, 6) @[CSR.scala 616:41] + _T_3310.htip <= _T_3332 @[CSR.scala 616:41] + node _T_3333 = bits(_T_3325, 7, 7) @[CSR.scala 616:41] + _T_3310.mtip <= _T_3333 @[CSR.scala 616:41] + node _T_3334 = bits(_T_3325, 8, 8) @[CSR.scala 616:41] + _T_3310.ueip <= _T_3334 @[CSR.scala 616:41] + node _T_3335 = bits(_T_3325, 9, 9) @[CSR.scala 616:41] + _T_3310.seip <= _T_3335 @[CSR.scala 616:41] + node _T_3336 = bits(_T_3325, 10, 10) @[CSR.scala 616:41] + _T_3310.heip <= _T_3336 @[CSR.scala 616:41] + node _T_3337 = bits(_T_3325, 11, 11) @[CSR.scala 616:41] + _T_3310.meip <= _T_3337 @[CSR.scala 616:41] + node _T_3338 = bits(_T_3325, 12, 12) @[CSR.scala 616:41] + _T_3310.rocc <= _T_3338 @[CSR.scala 616:41] + reg_mip.ssip <= _T_3310.ssip @[CSR.scala 617:22] + skip @[CSR.scala 615:37] + when _T_1705 : @[CSR.scala 619:39] + wire _T_3347 : {mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>} @[CSR.scala 620:44] + _T_3347 is invalid @[CSR.scala 620:44] + wire _T_3352 : UInt<64> + _T_3352 is invalid + _T_3352 <= wdata + node _T_3353 = bits(_T_3352, 43, 0) @[CSR.scala 620:44] + _T_3347.ppn <= _T_3353 @[CSR.scala 620:44] + node _T_3354 = bits(_T_3352, 59, 44) @[CSR.scala 620:44] + _T_3347.asid <= _T_3354 @[CSR.scala 620:44] + node _T_3355 = bits(_T_3352, 63, 60) @[CSR.scala 620:44] + _T_3347.mode <= _T_3355 @[CSR.scala 620:44] + node _T_3357 = eq(_T_3347.mode, UInt<1>("h00")) @[CSR.scala 622:30] + when _T_3357 : @[CSR.scala 622:37] + reg_sptbr.mode <= UInt<1>("h00") @[CSR.scala 622:54] + skip @[CSR.scala 622:37] + node _T_3360 = eq(_T_3347.mode, UInt<4>("h08")) @[CSR.scala 623:30] + when _T_3360 : @[CSR.scala 623:46] + reg_sptbr.mode <= UInt<4>("h08") @[CSR.scala 623:63] + skip @[CSR.scala 623:46] + node _T_3363 = eq(_T_3347.mode, UInt<1>("h00")) @[CSR.scala 624:30] + node _T_3365 = eq(_T_3347.mode, UInt<4>("h08")) @[CSR.scala 624:54] + node _T_3366 = or(_T_3363, _T_3365) @[CSR.scala 624:36] + when _T_3366 : @[CSR.scala 624:70] + node _T_3367 = bits(_T_3347.ppn, 19, 0) @[CSR.scala 625:41] + reg_sptbr.ppn <= _T_3367 @[CSR.scala 625:25] + skip @[CSR.scala 624:70] + skip @[CSR.scala 619:39] + when _T_1697 : @[CSR.scala 629:42] + node _T_3368 = not(reg_mideleg) @[CSR.scala 629:66] + node _T_3369 = and(reg_mie, _T_3368) @[CSR.scala 629:64] + node _T_3370 = and(wdata, reg_mideleg) @[CSR.scala 629:89] + node _T_3371 = or(_T_3369, _T_3370) @[CSR.scala 629:80] + reg_mie <= _T_3371 @[CSR.scala 629:52] + skip @[CSR.scala 629:42] + when _T_1699 : @[CSR.scala 630:42] + reg_sscratch <= wdata @[CSR.scala 630:57] + skip @[CSR.scala 630:42] + when _T_1707 : @[CSR.scala 631:42] + node _T_3372 = not(wdata) @[CSR.scala 714:28] + node _T_3373 = bits(reg_misa, 2, 2) @[CSR.scala 714:46] + node _T_3375 = eq(_T_3373, UInt<1>("h00")) @[CSR.scala 714:37] + node _T_3377 = cat(_T_3375, UInt<1>("h01")) @[Cat.scala 30:58] + node _T_3378 = or(_T_3372, _T_3377) @[CSR.scala 714:31] + node _T_3379 = not(_T_3378) @[CSR.scala 714:26] + reg_sepc <= _T_3379 @[CSR.scala 631:53] + skip @[CSR.scala 631:42] + when _T_1709 : @[CSR.scala 632:42] + node _T_3380 = shr(wdata, 2) @[CSR.scala 632:63] + node _T_3381 = shl(_T_3380, 2) @[CSR.scala 632:68] + reg_stvec <= _T_3381 @[CSR.scala 632:54] + skip @[CSR.scala 632:42] + when _T_1701 : @[CSR.scala 633:42] + node _T_3383 = and(wdata, UInt<64>("h0800000000000001f")) @[CSR.scala 633:64] + reg_scause <= _T_3383 @[CSR.scala 633:55] + skip @[CSR.scala 633:42] + when _T_1703 : @[CSR.scala 634:42] + node _T_3384 = bits(wdata, 39, 0) @[CSR.scala 634:65] + reg_sbadaddr <= _T_3384 @[CSR.scala 634:57] + skip @[CSR.scala 634:42] + when _T_1493 : @[CSR.scala 635:42] + node _T_3385 = and(wdata, delegable_interrupts) @[CSR.scala 635:65] + reg_mideleg <= _T_3385 @[CSR.scala 635:56] + skip @[CSR.scala 635:42] + when _T_1495 : @[CSR.scala 636:42] + node _T_3386 = and(wdata, UInt<9>("h01ab")) @[CSR.scala 636:65] + reg_medeleg <= _T_3386 @[CSR.scala 636:56] + skip @[CSR.scala 636:42] + when _T_1711 : @[CSR.scala 637:44] + node _T_3388 = and(wdata, UInt<3>("h07")) @[CSR.scala 637:70] + reg_scounteren <= _T_3388 @[CSR.scala 637:61] + skip @[CSR.scala 637:44] + when _T_1713 : @[CSR.scala 640:44] + node _T_3390 = and(wdata, UInt<3>("h07")) @[CSR.scala 640:70] + reg_mcounteren <= _T_3390 @[CSR.scala 640:61] + skip @[CSR.scala 640:44] + when _T_1467 : @[CSR.scala 643:41] + reg_tselect <= wdata @[CSR.scala 643:55] + skip @[CSR.scala 643:41] + node _T_3427 = eq(reg_bp[reg_tselect].control.dmode, UInt<1>("h00")) @[CSR.scala 646:13] + node _T_3428 = or(_T_3427, reg_debug) @[CSR.scala 646:31] + when _T_3428 : @[CSR.scala 646:45] + when _T_1469 : @[CSR.scala 647:42] + wire _T_3461 : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} @[CSR.scala 648:48] + _T_3461 is invalid @[CSR.scala 648:48] + wire _T_3478 : UInt<64> + _T_3478 is invalid + _T_3478 <= wdata + node _T_3479 = bits(_T_3478, 0, 0) @[CSR.scala 648:48] + _T_3461.r <= _T_3479 @[CSR.scala 648:48] + node _T_3480 = bits(_T_3478, 1, 1) @[CSR.scala 648:48] + _T_3461.w <= _T_3480 @[CSR.scala 648:48] + node _T_3481 = bits(_T_3478, 2, 2) @[CSR.scala 648:48] + _T_3461.x <= _T_3481 @[CSR.scala 648:48] + node _T_3482 = bits(_T_3478, 3, 3) @[CSR.scala 648:48] + _T_3461.u <= _T_3482 @[CSR.scala 648:48] + node _T_3483 = bits(_T_3478, 4, 4) @[CSR.scala 648:48] + _T_3461.s <= _T_3483 @[CSR.scala 648:48] + node _T_3484 = bits(_T_3478, 5, 5) @[CSR.scala 648:48] + _T_3461.h <= _T_3484 @[CSR.scala 648:48] + node _T_3485 = bits(_T_3478, 6, 6) @[CSR.scala 648:48] + _T_3461.m <= _T_3485 @[CSR.scala 648:48] + node _T_3486 = bits(_T_3478, 8, 7) @[CSR.scala 648:48] + _T_3461.tmatch <= _T_3486 @[CSR.scala 648:48] + node _T_3487 = bits(_T_3478, 10, 9) @[CSR.scala 648:48] + _T_3461.zero <= _T_3487 @[CSR.scala 648:48] + node _T_3488 = bits(_T_3478, 11, 11) @[CSR.scala 648:48] + _T_3461.chain <= _T_3488 @[CSR.scala 648:48] + node _T_3489 = bits(_T_3478, 12, 12) @[CSR.scala 648:48] + _T_3461.action <= _T_3489 @[CSR.scala 648:48] + node _T_3490 = bits(_T_3478, 52, 13) @[CSR.scala 648:48] + _T_3461.reserved <= _T_3490 @[CSR.scala 648:48] + node _T_3491 = bits(_T_3478, 58, 53) @[CSR.scala 648:48] + _T_3461.maskmax <= _T_3491 @[CSR.scala 648:48] + node _T_3492 = bits(_T_3478, 59, 59) @[CSR.scala 648:48] + _T_3461.dmode <= _T_3492 @[CSR.scala 648:48] + node _T_3493 = bits(_T_3478, 63, 60) @[CSR.scala 648:48] + _T_3461.ttype <= _T_3493 @[CSR.scala 648:48] + node _T_3494 = and(_T_3461.dmode, reg_debug) @[CSR.scala 649:36] + reg_bp[reg_tselect].control <- _T_3461 @[CSR.scala 650:22] + reg_bp[reg_tselect].control.dmode <= _T_3494 @[CSR.scala 651:28] + node _T_3495 = and(_T_3494, _T_3461.action) @[CSR.scala 652:38] + reg_bp[reg_tselect].control.action <= _T_3495 @[CSR.scala 652:29] + skip @[CSR.scala 647:42] + when _T_1471 : @[CSR.scala 654:42] + reg_bp[reg_tselect].address <= wdata @[CSR.scala 654:55] + skip @[CSR.scala 654:42] + skip @[CSR.scala 646:45] + skip @[CSR.scala 536:49] + reg_mip <- io.interrupts @[CSR.scala 659:11] + reg_dcsr.debugint <= io.interrupts.debug @[CSR.scala 660:21] + reg_sptbr.asid <= UInt<1>("h00") @[CSR.scala 672:18] + reg_tselect <= UInt<1>("h00") @[CSR.scala 673:38] + reg_bp[0].control.chain <= UInt<1>("h00") @[CSR.scala 675:42] + reg_bp[0].control.ttype <= UInt<2>("h02") @[CSR.scala 677:15] + reg_bp[0].control.maskmax <= UInt<3>("h04") @[CSR.scala 678:17] + reg_bp[0].control.reserved <= UInt<1>("h00") @[CSR.scala 679:18] + reg_bp[0].control.zero <= UInt<1>("h00") @[CSR.scala 680:14] + reg_bp[0].control.h <= UInt<1>("h00") @[CSR.scala 681:11] + when reset : @[CSR.scala 685:18] + reg_bp[0].control.action <= UInt<1>("h00") @[CSR.scala 686:18] + reg_bp[0].control.dmode <= UInt<1>("h00") @[CSR.scala 687:17] + reg_bp[0].control.r <= UInt<1>("h00") @[CSR.scala 688:13] + reg_bp[0].control.w <= UInt<1>("h00") @[CSR.scala 689:13] + reg_bp[0].control.x <= UInt<1>("h00") @[CSR.scala 690:13] + skip @[CSR.scala 685:18] + reg_bp[1].control.ttype <= UInt<2>("h02") @[CSR.scala 677:15] + reg_bp[1].control.maskmax <= UInt<3>("h04") @[CSR.scala 678:17] + reg_bp[1].control.reserved <= UInt<1>("h00") @[CSR.scala 679:18] + reg_bp[1].control.zero <= UInt<1>("h00") @[CSR.scala 680:14] + reg_bp[1].control.h <= UInt<1>("h00") @[CSR.scala 681:11] + when reset : @[CSR.scala 685:18] + reg_bp[1].control.action <= UInt<1>("h00") @[CSR.scala 686:18] + reg_bp[1].control.dmode <= UInt<1>("h00") @[CSR.scala 687:17] + reg_bp[1].control.r <= UInt<1>("h00") @[CSR.scala 688:13] + reg_bp[1].control.w <= UInt<1>("h00") @[CSR.scala 689:13] + reg_bp[1].control.x <= UInt<1>("h00") @[CSR.scala 690:13] + skip @[CSR.scala 685:18] + wire _T_3556 : {control : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>} @[CSR.scala 694:28] + _T_3556 is invalid @[CSR.scala 694:28] + wire _T_3575 : UInt<103> + _T_3575 is invalid + _T_3575 <= UInt<1>("h00") + node _T_3576 = bits(_T_3575, 38, 0) @[CSR.scala 694:28] + _T_3556.address <= _T_3576 @[CSR.scala 694:28] + node _T_3577 = bits(_T_3575, 102, 39) @[CSR.scala 694:28] + wire _T_3579 : UInt<64> + _T_3579 is invalid + _T_3579 <= _T_3577 + node _T_3580 = bits(_T_3579, 0, 0) @[CSR.scala 694:28] + _T_3556.control.r <= _T_3580 @[CSR.scala 694:28] + node _T_3581 = bits(_T_3579, 1, 1) @[CSR.scala 694:28] + _T_3556.control.w <= _T_3581 @[CSR.scala 694:28] + node _T_3582 = bits(_T_3579, 2, 2) @[CSR.scala 694:28] + _T_3556.control.x <= _T_3582 @[CSR.scala 694:28] + node _T_3583 = bits(_T_3579, 3, 3) @[CSR.scala 694:28] + _T_3556.control.u <= _T_3583 @[CSR.scala 694:28] + node _T_3584 = bits(_T_3579, 4, 4) @[CSR.scala 694:28] + _T_3556.control.s <= _T_3584 @[CSR.scala 694:28] + node _T_3585 = bits(_T_3579, 5, 5) @[CSR.scala 694:28] + _T_3556.control.h <= _T_3585 @[CSR.scala 694:28] + node _T_3586 = bits(_T_3579, 6, 6) @[CSR.scala 694:28] + _T_3556.control.m <= _T_3586 @[CSR.scala 694:28] + node _T_3587 = bits(_T_3579, 8, 7) @[CSR.scala 694:28] + _T_3556.control.tmatch <= _T_3587 @[CSR.scala 694:28] + node _T_3588 = bits(_T_3579, 10, 9) @[CSR.scala 694:28] + _T_3556.control.zero <= _T_3588 @[CSR.scala 694:28] + node _T_3589 = bits(_T_3579, 11, 11) @[CSR.scala 694:28] + _T_3556.control.chain <= _T_3589 @[CSR.scala 694:28] + node _T_3590 = bits(_T_3579, 12, 12) @[CSR.scala 694:28] + _T_3556.control.action <= _T_3590 @[CSR.scala 694:28] + node _T_3591 = bits(_T_3579, 52, 13) @[CSR.scala 694:28] + _T_3556.control.reserved <= _T_3591 @[CSR.scala 694:28] + node _T_3592 = bits(_T_3579, 58, 53) @[CSR.scala 694:28] + _T_3556.control.maskmax <= _T_3592 @[CSR.scala 694:28] + node _T_3593 = bits(_T_3579, 59, 59) @[CSR.scala 694:28] + _T_3556.control.dmode <= _T_3593 @[CSR.scala 694:28] + node _T_3594 = bits(_T_3579, 63, 60) @[CSR.scala 694:28] + _T_3556.control.ttype <= _T_3594 @[CSR.scala 694:28] + reg_bp[1] <- _T_3556 @[CSR.scala 694:8] + + module BreakpointUnit : + input clock : Clock + input reset : UInt<1> + output io : {flip status : {debug : UInt<1>, isa : UInt<32>, prv : UInt<2>, sd : UInt<1>, zero2 : UInt<27>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, pum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, hpp : UInt<2>, spp : UInt<1>, mpie : UInt<1>, hpie : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : {control : {ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>}[1], flip pc : UInt<39>, flip ea : UInt<39>, xcpt_if : UInt<1>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, debug_if : UInt<1>, debug_ld : UInt<1>, debug_st : UInt<1>} + + io is invalid + io is invalid + io.xcpt_if <= UInt<1>("h00") @[Breakpoint.scala 64:14] + io.xcpt_ld <= UInt<1>("h00") @[Breakpoint.scala 65:14] + io.xcpt_st <= UInt<1>("h00") @[Breakpoint.scala 66:14] + io.debug_if <= UInt<1>("h00") @[Breakpoint.scala 67:15] + io.debug_ld <= UInt<1>("h00") @[Breakpoint.scala 68:15] + io.debug_st <= UInt<1>("h00") @[Breakpoint.scala 69:15] + node _T_212 = eq(io.status.debug, UInt<1>("h00")) @[Breakpoint.scala 30:35] + node _T_213 = cat(io.bp[0].control.s, io.bp[0].control.u) @[Cat.scala 30:58] + node _T_214 = cat(io.bp[0].control.m, io.bp[0].control.h) @[Cat.scala 30:58] + node _T_215 = cat(_T_214, _T_213) @[Cat.scala 30:58] + node _T_216 = dshr(_T_215, io.status.prv) @[Breakpoint.scala 30:68] + node _T_217 = bits(_T_216, 0, 0) @[Breakpoint.scala 30:68] + node _T_218 = and(_T_212, _T_217) @[Breakpoint.scala 30:50] + node _T_219 = and(_T_218, UInt<1>("h01")) @[Breakpoint.scala 73:16] + node _T_220 = and(_T_219, io.bp[0].control.r) @[Breakpoint.scala 73:22] + node _T_221 = bits(io.bp[0].control.tmatch, 1, 1) @[Breakpoint.scala 47:23] + node _T_222 = geq(io.ea, io.bp[0].address) @[Breakpoint.scala 44:8] + node _T_223 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 44:36] + node _T_224 = xor(_T_222, _T_223) @[Breakpoint.scala 44:20] + node _T_225 = not(io.ea) @[Breakpoint.scala 41:6] + node _T_226 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 38:56] + node _T_227 = bits(io.bp[0].address, 0, 0) @[Breakpoint.scala 38:83] + node _T_228 = and(_T_226, _T_227) @[Breakpoint.scala 38:73] + node _T_229 = bits(io.bp[0].address, 1, 1) @[Breakpoint.scala 38:83] + node _T_230 = and(_T_228, _T_229) @[Breakpoint.scala 38:73] + node _T_231 = bits(io.bp[0].address, 2, 2) @[Breakpoint.scala 38:83] + node _T_232 = and(_T_230, _T_231) @[Breakpoint.scala 38:73] + node _T_233 = cat(_T_228, _T_226) @[Cat.scala 30:58] + node _T_234 = cat(_T_232, _T_230) @[Cat.scala 30:58] + node _T_235 = cat(_T_234, _T_233) @[Cat.scala 30:58] + node _T_236 = or(_T_225, _T_235) @[Breakpoint.scala 41:9] + node _T_237 = not(io.bp[0].address) @[Breakpoint.scala 41:24] + node _T_238 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 38:56] + node _T_239 = bits(io.bp[0].address, 0, 0) @[Breakpoint.scala 38:83] + node _T_240 = and(_T_238, _T_239) @[Breakpoint.scala 38:73] + node _T_241 = bits(io.bp[0].address, 1, 1) @[Breakpoint.scala 38:83] + node _T_242 = and(_T_240, _T_241) @[Breakpoint.scala 38:73] + node _T_243 = bits(io.bp[0].address, 2, 2) @[Breakpoint.scala 38:83] + node _T_244 = and(_T_242, _T_243) @[Breakpoint.scala 38:73] + node _T_245 = cat(_T_240, _T_238) @[Cat.scala 30:58] + node _T_246 = cat(_T_244, _T_242) @[Cat.scala 30:58] + node _T_247 = cat(_T_246, _T_245) @[Cat.scala 30:58] + node _T_248 = or(_T_237, _T_247) @[Breakpoint.scala 41:33] + node _T_249 = eq(_T_236, _T_248) @[Breakpoint.scala 41:19] + node _T_250 = mux(_T_221, _T_224, _T_249) @[Breakpoint.scala 47:8] + node _T_251 = and(_T_220, _T_250) @[Breakpoint.scala 73:38] + node _T_252 = and(_T_218, UInt<1>("h01")) @[Breakpoint.scala 74:16] + node _T_253 = and(_T_252, io.bp[0].control.w) @[Breakpoint.scala 74:22] + node _T_254 = bits(io.bp[0].control.tmatch, 1, 1) @[Breakpoint.scala 47:23] + node _T_255 = geq(io.ea, io.bp[0].address) @[Breakpoint.scala 44:8] + node _T_256 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 44:36] + node _T_257 = xor(_T_255, _T_256) @[Breakpoint.scala 44:20] + node _T_258 = not(io.ea) @[Breakpoint.scala 41:6] + node _T_259 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 38:56] + node _T_260 = bits(io.bp[0].address, 0, 0) @[Breakpoint.scala 38:83] + node _T_261 = and(_T_259, _T_260) @[Breakpoint.scala 38:73] + node _T_262 = bits(io.bp[0].address, 1, 1) @[Breakpoint.scala 38:83] + node _T_263 = and(_T_261, _T_262) @[Breakpoint.scala 38:73] + node _T_264 = bits(io.bp[0].address, 2, 2) @[Breakpoint.scala 38:83] + node _T_265 = and(_T_263, _T_264) @[Breakpoint.scala 38:73] + node _T_266 = cat(_T_261, _T_259) @[Cat.scala 30:58] + node _T_267 = cat(_T_265, _T_263) @[Cat.scala 30:58] + node _T_268 = cat(_T_267, _T_266) @[Cat.scala 30:58] + node _T_269 = or(_T_258, _T_268) @[Breakpoint.scala 41:9] + node _T_270 = not(io.bp[0].address) @[Breakpoint.scala 41:24] + node _T_271 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 38:56] + node _T_272 = bits(io.bp[0].address, 0, 0) @[Breakpoint.scala 38:83] + node _T_273 = and(_T_271, _T_272) @[Breakpoint.scala 38:73] + node _T_274 = bits(io.bp[0].address, 1, 1) @[Breakpoint.scala 38:83] + node _T_275 = and(_T_273, _T_274) @[Breakpoint.scala 38:73] + node _T_276 = bits(io.bp[0].address, 2, 2) @[Breakpoint.scala 38:83] + node _T_277 = and(_T_275, _T_276) @[Breakpoint.scala 38:73] + node _T_278 = cat(_T_273, _T_271) @[Cat.scala 30:58] + node _T_279 = cat(_T_277, _T_275) @[Cat.scala 30:58] + node _T_280 = cat(_T_279, _T_278) @[Cat.scala 30:58] + node _T_281 = or(_T_270, _T_280) @[Breakpoint.scala 41:33] + node _T_282 = eq(_T_269, _T_281) @[Breakpoint.scala 41:19] + node _T_283 = mux(_T_254, _T_257, _T_282) @[Breakpoint.scala 47:8] + node _T_284 = and(_T_253, _T_283) @[Breakpoint.scala 74:38] + node _T_285 = and(_T_218, UInt<1>("h01")) @[Breakpoint.scala 75:16] + node _T_286 = and(_T_285, io.bp[0].control.x) @[Breakpoint.scala 75:22] + node _T_287 = bits(io.bp[0].control.tmatch, 1, 1) @[Breakpoint.scala 47:23] + node _T_288 = geq(io.pc, io.bp[0].address) @[Breakpoint.scala 44:8] + node _T_289 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 44:36] + node _T_290 = xor(_T_288, _T_289) @[Breakpoint.scala 44:20] + node _T_291 = not(io.pc) @[Breakpoint.scala 41:6] + node _T_292 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 38:56] + node _T_293 = bits(io.bp[0].address, 0, 0) @[Breakpoint.scala 38:83] + node _T_294 = and(_T_292, _T_293) @[Breakpoint.scala 38:73] + node _T_295 = bits(io.bp[0].address, 1, 1) @[Breakpoint.scala 38:83] + node _T_296 = and(_T_294, _T_295) @[Breakpoint.scala 38:73] + node _T_297 = bits(io.bp[0].address, 2, 2) @[Breakpoint.scala 38:83] + node _T_298 = and(_T_296, _T_297) @[Breakpoint.scala 38:73] + node _T_299 = cat(_T_294, _T_292) @[Cat.scala 30:58] + node _T_300 = cat(_T_298, _T_296) @[Cat.scala 30:58] + node _T_301 = cat(_T_300, _T_299) @[Cat.scala 30:58] + node _T_302 = or(_T_291, _T_301) @[Breakpoint.scala 41:9] + node _T_303 = not(io.bp[0].address) @[Breakpoint.scala 41:24] + node _T_304 = bits(io.bp[0].control.tmatch, 0, 0) @[Breakpoint.scala 38:56] + node _T_305 = bits(io.bp[0].address, 0, 0) @[Breakpoint.scala 38:83] + node _T_306 = and(_T_304, _T_305) @[Breakpoint.scala 38:73] + node _T_307 = bits(io.bp[0].address, 1, 1) @[Breakpoint.scala 38:83] + node _T_308 = and(_T_306, _T_307) @[Breakpoint.scala 38:73] + node _T_309 = bits(io.bp[0].address, 2, 2) @[Breakpoint.scala 38:83] + node _T_310 = and(_T_308, _T_309) @[Breakpoint.scala 38:73] + node _T_311 = cat(_T_306, _T_304) @[Cat.scala 30:58] + node _T_312 = cat(_T_310, _T_308) @[Cat.scala 30:58] + node _T_313 = cat(_T_312, _T_311) @[Cat.scala 30:58] + node _T_314 = or(_T_303, _T_313) @[Breakpoint.scala 41:33] + node _T_315 = eq(_T_302, _T_314) @[Breakpoint.scala 41:19] + node _T_316 = mux(_T_287, _T_290, _T_315) @[Breakpoint.scala 47:8] + node _T_317 = and(_T_286, _T_316) @[Breakpoint.scala 75:38] + node _T_319 = eq(io.bp[0].control.chain, UInt<1>("h00")) @[Breakpoint.scala 76:15] + node _T_320 = and(_T_319, _T_251) @[Breakpoint.scala 78:15] + when _T_320 : @[Breakpoint.scala 78:21] + node _T_322 = eq(io.bp[0].control.action, UInt<1>("h00")) @[Breakpoint.scala 78:37] + io.xcpt_ld <= _T_322 @[Breakpoint.scala 78:34] + io.debug_ld <= io.bp[0].control.action @[Breakpoint.scala 78:69] + skip @[Breakpoint.scala 78:21] + node _T_323 = and(_T_319, _T_284) @[Breakpoint.scala 79:15] + when _T_323 : @[Breakpoint.scala 79:21] + node _T_325 = eq(io.bp[0].control.action, UInt<1>("h00")) @[Breakpoint.scala 79:37] + io.xcpt_st <= _T_325 @[Breakpoint.scala 79:34] + io.debug_st <= io.bp[0].control.action @[Breakpoint.scala 79:69] + skip @[Breakpoint.scala 79:21] + node _T_326 = and(_T_319, _T_317) @[Breakpoint.scala 80:15] + when _T_326 : @[Breakpoint.scala 80:21] + node _T_328 = eq(io.bp[0].control.action, UInt<1>("h00")) @[Breakpoint.scala 80:37] + io.xcpt_if <= _T_328 @[Breakpoint.scala 80:34] + io.debug_if <= io.bp[0].control.action @[Breakpoint.scala 80:69] + skip @[Breakpoint.scala 80:21] + node _T_329 = or(_T_319, _T_251) @[Breakpoint.scala 82:10] + node _T_330 = or(_T_319, _T_284) @[Breakpoint.scala 82:20] + node _T_331 = or(_T_319, _T_317) @[Breakpoint.scala 82:30] + + module ALU : + input clock : Clock + input reset : UInt<1> + output io : {flip dw : UInt<1>, flip fn : UInt<4>, flip in2 : UInt<64>, flip in1 : UInt<64>, out : UInt<64>, adder_out : UInt<64>, cmp_out : UInt<1>} + + io is invalid + io is invalid + node _T_16 = bits(io.fn, 3, 3) @[ALU.scala 41:29] + node _T_17 = not(io.in2) @[ALU.scala 61:35] + node in2_inv = mux(_T_16, _T_17, io.in2) @[ALU.scala 61:20] + node in1_xor_in2 = xor(io.in1, in2_inv) @[ALU.scala 62:28] + node _T_18 = add(io.in1, in2_inv) @[ALU.scala 63:26] + node _T_19 = tail(_T_18, 1) @[ALU.scala 63:26] + node _T_20 = bits(io.fn, 3, 3) @[ALU.scala 41:29] + node _T_21 = add(_T_19, _T_20) @[ALU.scala 63:36] + node _T_22 = tail(_T_21, 1) @[ALU.scala 63:36] + io.adder_out <= _T_22 @[ALU.scala 63:16] + node _T_23 = bits(io.fn, 0, 0) @[ALU.scala 44:35] + node _T_24 = bits(io.fn, 3, 3) @[ALU.scala 45:30] + node _T_26 = eq(_T_24, UInt<1>("h00")) @[ALU.scala 45:26] + node _T_28 = eq(in1_xor_in2, UInt<1>("h00")) @[ALU.scala 67:35] + node _T_29 = bits(io.in1, 63, 63) @[ALU.scala 68:15] + node _T_30 = bits(io.in2, 63, 63) @[ALU.scala 68:34] + node _T_31 = eq(_T_29, _T_30) @[ALU.scala 68:24] + node _T_32 = bits(io.adder_out, 63, 63) @[ALU.scala 68:56] + node _T_33 = bits(io.fn, 1, 1) @[ALU.scala 43:35] + node _T_34 = bits(io.in2, 63, 63) @[ALU.scala 69:35] + node _T_35 = bits(io.in1, 63, 63) @[ALU.scala 69:51] + node _T_36 = mux(_T_33, _T_34, _T_35) @[ALU.scala 69:8] + node _T_37 = mux(_T_31, _T_32, _T_36) @[ALU.scala 68:8] + node _T_38 = mux(_T_26, _T_28, _T_37) @[ALU.scala 67:8] + node _T_39 = xor(_T_23, _T_38) @[ALU.scala 66:36] + io.cmp_out <= _T_39 @[ALU.scala 66:14] + node _T_40 = bits(io.fn, 3, 3) @[ALU.scala 41:29] + node _T_41 = bits(io.in1, 31, 31) @[ALU.scala 76:55] + node _T_42 = and(_T_40, _T_41) @[ALU.scala 76:46] + node _T_43 = bits(_T_42, 0, 0) @[Bitwise.scala 71:15] + node _T_46 = mux(_T_43, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12] + node _T_48 = eq(io.dw, UInt<1>("h01")) @[ALU.scala 77:31] + node _T_49 = bits(io.in1, 63, 32) @[ALU.scala 77:48] + node _T_50 = mux(_T_48, _T_49, _T_46) @[ALU.scala 77:24] + node _T_51 = bits(io.in2, 5, 5) @[ALU.scala 78:29] + node _T_53 = eq(io.dw, UInt<1>("h01")) @[ALU.scala 78:42] + node _T_54 = and(_T_51, _T_53) @[ALU.scala 78:33] + node _T_55 = bits(io.in2, 4, 0) @[ALU.scala 78:60] + node shamt = cat(_T_54, _T_55) @[Cat.scala 30:58] + node _T_56 = bits(io.in1, 31, 0) @[ALU.scala 79:34] + node shin_r = cat(_T_50, _T_56) @[Cat.scala 30:58] + node _T_58 = eq(io.fn, UInt<3>("h05")) @[ALU.scala 81:24] + node _T_60 = eq(io.fn, UInt<4>("h0b")) @[ALU.scala 81:44] + node _T_61 = or(_T_58, _T_60) @[ALU.scala 81:35] + node _T_64 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 101:47] + node _T_65 = xor(UInt<64>("h0ffffffffffffffff"), _T_64) @[Bitwise.scala 101:21] + node _T_66 = shr(shin_r, 32) @[Bitwise.scala 102:21] + node _T_67 = and(_T_66, _T_65) @[Bitwise.scala 102:31] + node _T_68 = bits(shin_r, 31, 0) @[Bitwise.scala 102:46] + node _T_69 = shl(_T_68, 32) @[Bitwise.scala 102:65] + node _T_70 = not(_T_65) @[Bitwise.scala 102:77] + node _T_71 = and(_T_69, _T_70) @[Bitwise.scala 102:75] + node _T_72 = or(_T_67, _T_71) @[Bitwise.scala 102:39] + node _T_73 = bits(_T_65, 47, 0) @[Bitwise.scala 101:28] + node _T_74 = shl(_T_73, 16) @[Bitwise.scala 101:47] + node _T_75 = xor(_T_65, _T_74) @[Bitwise.scala 101:21] + node _T_76 = shr(_T_72, 16) @[Bitwise.scala 102:21] + node _T_77 = and(_T_76, _T_75) @[Bitwise.scala 102:31] + node _T_78 = bits(_T_72, 47, 0) @[Bitwise.scala 102:46] + node _T_79 = shl(_T_78, 16) @[Bitwise.scala 102:65] + node _T_80 = not(_T_75) @[Bitwise.scala 102:77] + node _T_81 = and(_T_79, _T_80) @[Bitwise.scala 102:75] + node _T_82 = or(_T_77, _T_81) @[Bitwise.scala 102:39] + node _T_83 = bits(_T_75, 55, 0) @[Bitwise.scala 101:28] + node _T_84 = shl(_T_83, 8) @[Bitwise.scala 101:47] + node _T_85 = xor(_T_75, _T_84) @[Bitwise.scala 101:21] + node _T_86 = shr(_T_82, 8) @[Bitwise.scala 102:21] + node _T_87 = and(_T_86, _T_85) @[Bitwise.scala 102:31] + node _T_88 = bits(_T_82, 55, 0) @[Bitwise.scala 102:46] + node _T_89 = shl(_T_88, 8) @[Bitwise.scala 102:65] + node _T_90 = not(_T_85) @[Bitwise.scala 102:77] + node _T_91 = and(_T_89, _T_90) @[Bitwise.scala 102:75] + node _T_92 = or(_T_87, _T_91) @[Bitwise.scala 102:39] + node _T_93 = bits(_T_85, 59, 0) @[Bitwise.scala 101:28] + node _T_94 = shl(_T_93, 4) @[Bitwise.scala 101:47] + node _T_95 = xor(_T_85, _T_94) @[Bitwise.scala 101:21] + node _T_96 = shr(_T_92, 4) @[Bitwise.scala 102:21] + node _T_97 = and(_T_96, _T_95) @[Bitwise.scala 102:31] + node _T_98 = bits(_T_92, 59, 0) @[Bitwise.scala 102:46] + node _T_99 = shl(_T_98, 4) @[Bitwise.scala 102:65] + node _T_100 = not(_T_95) @[Bitwise.scala 102:77] + node _T_101 = and(_T_99, _T_100) @[Bitwise.scala 102:75] + node _T_102 = or(_T_97, _T_101) @[Bitwise.scala 102:39] + node _T_103 = bits(_T_95, 61, 0) @[Bitwise.scala 101:28] + node _T_104 = shl(_T_103, 2) @[Bitwise.scala 101:47] + node _T_105 = xor(_T_95, _T_104) @[Bitwise.scala 101:21] + node _T_106 = shr(_T_102, 2) @[Bitwise.scala 102:21] + node _T_107 = and(_T_106, _T_105) @[Bitwise.scala 102:31] + node _T_108 = bits(_T_102, 61, 0) @[Bitwise.scala 102:46] + node _T_109 = shl(_T_108, 2) @[Bitwise.scala 102:65] + node _T_110 = not(_T_105) @[Bitwise.scala 102:77] + node _T_111 = and(_T_109, _T_110) @[Bitwise.scala 102:75] + node _T_112 = or(_T_107, _T_111) @[Bitwise.scala 102:39] + node _T_113 = bits(_T_105, 62, 0) @[Bitwise.scala 101:28] + node _T_114 = shl(_T_113, 1) @[Bitwise.scala 101:47] + node _T_115 = xor(_T_105, _T_114) @[Bitwise.scala 101:21] + node _T_116 = shr(_T_112, 1) @[Bitwise.scala 102:21] + node _T_117 = and(_T_116, _T_115) @[Bitwise.scala 102:31] + node _T_118 = bits(_T_112, 62, 0) @[Bitwise.scala 102:46] + node _T_119 = shl(_T_118, 1) @[Bitwise.scala 102:65] + node _T_120 = not(_T_115) @[Bitwise.scala 102:77] + node _T_121 = and(_T_119, _T_120) @[Bitwise.scala 102:75] + node _T_122 = or(_T_117, _T_121) @[Bitwise.scala 102:39] + node shin = mux(_T_61, shin_r, _T_122) @[ALU.scala 81:17] + node _T_123 = bits(io.fn, 3, 3) @[ALU.scala 41:29] + node _T_124 = bits(shin, 63, 63) @[ALU.scala 82:41] + node _T_125 = and(_T_123, _T_124) @[ALU.scala 82:35] + node _T_126 = cat(_T_125, shin) @[Cat.scala 30:58] + node _T_127 = asSInt(_T_126) @[ALU.scala 82:57] + node _T_128 = dshr(_T_127, shamt) @[ALU.scala 82:64] + node shout_r = bits(_T_128, 63, 0) @[ALU.scala 82:73] + node _T_131 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 101:47] + node _T_132 = xor(UInt<64>("h0ffffffffffffffff"), _T_131) @[Bitwise.scala 101:21] + node _T_133 = shr(shout_r, 32) @[Bitwise.scala 102:21] + node _T_134 = and(_T_133, _T_132) @[Bitwise.scala 102:31] + node _T_135 = bits(shout_r, 31, 0) @[Bitwise.scala 102:46] + node _T_136 = shl(_T_135, 32) @[Bitwise.scala 102:65] + node _T_137 = not(_T_132) @[Bitwise.scala 102:77] + node _T_138 = and(_T_136, _T_137) @[Bitwise.scala 102:75] + node _T_139 = or(_T_134, _T_138) @[Bitwise.scala 102:39] + node _T_140 = bits(_T_132, 47, 0) @[Bitwise.scala 101:28] + node _T_141 = shl(_T_140, 16) @[Bitwise.scala 101:47] + node _T_142 = xor(_T_132, _T_141) @[Bitwise.scala 101:21] + node _T_143 = shr(_T_139, 16) @[Bitwise.scala 102:21] + node _T_144 = and(_T_143, _T_142) @[Bitwise.scala 102:31] + node _T_145 = bits(_T_139, 47, 0) @[Bitwise.scala 102:46] + node _T_146 = shl(_T_145, 16) @[Bitwise.scala 102:65] + node _T_147 = not(_T_142) @[Bitwise.scala 102:77] + node _T_148 = and(_T_146, _T_147) @[Bitwise.scala 102:75] + node _T_149 = or(_T_144, _T_148) @[Bitwise.scala 102:39] + node _T_150 = bits(_T_142, 55, 0) @[Bitwise.scala 101:28] + node _T_151 = shl(_T_150, 8) @[Bitwise.scala 101:47] + node _T_152 = xor(_T_142, _T_151) @[Bitwise.scala 101:21] + node _T_153 = shr(_T_149, 8) @[Bitwise.scala 102:21] + node _T_154 = and(_T_153, _T_152) @[Bitwise.scala 102:31] + node _T_155 = bits(_T_149, 55, 0) @[Bitwise.scala 102:46] + node _T_156 = shl(_T_155, 8) @[Bitwise.scala 102:65] + node _T_157 = not(_T_152) @[Bitwise.scala 102:77] + node _T_158 = and(_T_156, _T_157) @[Bitwise.scala 102:75] + node _T_159 = or(_T_154, _T_158) @[Bitwise.scala 102:39] + node _T_160 = bits(_T_152, 59, 0) @[Bitwise.scala 101:28] + node _T_161 = shl(_T_160, 4) @[Bitwise.scala 101:47] + node _T_162 = xor(_T_152, _T_161) @[Bitwise.scala 101:21] + node _T_163 = shr(_T_159, 4) @[Bitwise.scala 102:21] + node _T_164 = and(_T_163, _T_162) @[Bitwise.scala 102:31] + node _T_165 = bits(_T_159, 59, 0) @[Bitwise.scala 102:46] + node _T_166 = shl(_T_165, 4) @[Bitwise.scala 102:65] + node _T_167 = not(_T_162) @[Bitwise.scala 102:77] + node _T_168 = and(_T_166, _T_167) @[Bitwise.scala 102:75] + node _T_169 = or(_T_164, _T_168) @[Bitwise.scala 102:39] + node _T_170 = bits(_T_162, 61, 0) @[Bitwise.scala 101:28] + node _T_171 = shl(_T_170, 2) @[Bitwise.scala 101:47] + node _T_172 = xor(_T_162, _T_171) @[Bitwise.scala 101:21] + node _T_173 = shr(_T_169, 2) @[Bitwise.scala 102:21] + node _T_174 = and(_T_173, _T_172) @[Bitwise.scala 102:31] + node _T_175 = bits(_T_169, 61, 0) @[Bitwise.scala 102:46] + node _T_176 = shl(_T_175, 2) @[Bitwise.scala 102:65] + node _T_177 = not(_T_172) @[Bitwise.scala 102:77] + node _T_178 = and(_T_176, _T_177) @[Bitwise.scala 102:75] + node _T_179 = or(_T_174, _T_178) @[Bitwise.scala 102:39] + node _T_180 = bits(_T_172, 62, 0) @[Bitwise.scala 101:28] + node _T_181 = shl(_T_180, 1) @[Bitwise.scala 101:47] + node _T_182 = xor(_T_172, _T_181) @[Bitwise.scala 101:21] + node _T_183 = shr(_T_179, 1) @[Bitwise.scala 102:21] + node _T_184 = and(_T_183, _T_182) @[Bitwise.scala 102:31] + node _T_185 = bits(_T_179, 62, 0) @[Bitwise.scala 102:46] + node _T_186 = shl(_T_185, 1) @[Bitwise.scala 102:65] + node _T_187 = not(_T_182) @[Bitwise.scala 102:77] + node _T_188 = and(_T_186, _T_187) @[Bitwise.scala 102:75] + node shout_l = or(_T_184, _T_188) @[Bitwise.scala 102:39] + node _T_190 = eq(io.fn, UInt<3>("h05")) @[ALU.scala 84:25] + node _T_192 = eq(io.fn, UInt<4>("h0b")) @[ALU.scala 84:44] + node _T_193 = or(_T_190, _T_192) @[ALU.scala 84:35] + node _T_195 = mux(_T_193, shout_r, UInt<1>("h00")) @[ALU.scala 84:18] + node _T_197 = eq(io.fn, UInt<1>("h01")) @[ALU.scala 85:25] + node _T_199 = mux(_T_197, shout_l, UInt<1>("h00")) @[ALU.scala 85:18] + node shout = or(_T_195, _T_199) @[ALU.scala 84:74] + node _T_201 = eq(io.fn, UInt<3>("h04")) @[ALU.scala 88:25] + node _T_203 = eq(io.fn, UInt<3>("h06")) @[ALU.scala 88:45] + node _T_204 = or(_T_201, _T_203) @[ALU.scala 88:36] + node _T_206 = mux(_T_204, in1_xor_in2, UInt<1>("h00")) @[ALU.scala 88:18] + node _T_208 = eq(io.fn, UInt<3>("h06")) @[ALU.scala 89:25] + node _T_210 = eq(io.fn, UInt<3>("h07")) @[ALU.scala 89:44] + node _T_211 = or(_T_208, _T_210) @[ALU.scala 89:35] + node _T_212 = and(io.in1, io.in2) @[ALU.scala 89:63] + node _T_214 = mux(_T_211, _T_212, UInt<1>("h00")) @[ALU.scala 89:18] + node logic = or(_T_206, _T_214) @[ALU.scala 88:78] + node _T_216 = eq(io.fn, UInt<2>("h02")) @[ALU.scala 42:30] + node _T_218 = eq(io.fn, UInt<2>("h03")) @[ALU.scala 42:48] + node _T_219 = or(_T_216, _T_218) @[ALU.scala 42:41] + node _T_221 = geq(io.fn, UInt<4>("h0c")) @[ALU.scala 42:66] + node _T_222 = or(_T_219, _T_221) @[ALU.scala 42:59] + node _T_223 = and(_T_222, io.cmp_out) @[ALU.scala 90:35] + node _T_224 = or(_T_223, logic) @[ALU.scala 90:50] + node shift_logic = or(_T_224, shout) @[ALU.scala 90:58] + node _T_226 = eq(io.fn, UInt<1>("h00")) @[ALU.scala 91:23] + node _T_228 = eq(io.fn, UInt<4>("h0a")) @[ALU.scala 91:43] + node _T_229 = or(_T_226, _T_228) @[ALU.scala 91:34] + node out = mux(_T_229, io.adder_out, shift_logic) @[ALU.scala 91:16] + io.out <= out @[ALU.scala 93:10] + node _T_231 = eq(io.dw, UInt<1>("h00")) @[ALU.scala 96:17] + when _T_231 : @[ALU.scala 96:28] + node _T_232 = bits(out, 31, 31) @[ALU.scala 96:56] + node _T_233 = bits(_T_232, 0, 0) @[Bitwise.scala 71:15] + node _T_236 = mux(_T_233, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12] + node _T_237 = bits(out, 31, 0) @[ALU.scala 96:66] + node _T_238 = cat(_T_236, _T_237) @[Cat.scala 30:58] + io.out <= _T_238 @[ALU.scala 96:37] + skip @[ALU.scala 96:28] + + module MulDiv : + input clock : Clock + input reset : UInt<1> + output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}}, flip kill : UInt<1>, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}}} + + io is invalid + io is invalid + reg state : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[Multiplier.scala 45:18] + reg req : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clock @[Multiplier.scala 47:16] + reg count : UInt<7>, clock @[Multiplier.scala 48:18] + reg neg_out : UInt<1>, clock @[Multiplier.scala 49:20] + reg isMul : UInt<1>, clock @[Multiplier.scala 50:18] + reg isHi : UInt<1>, clock @[Multiplier.scala 51:17] + reg divisor : UInt<65>, clock @[Multiplier.scala 52:20] + reg remainder : UInt<130>, clock @[Multiplier.scala 53:22] + node _T_79 = and(io.req.bits.fn, UInt<4>("h04")) @[Decode.scala 13:65] + node _T_81 = eq(_T_79, UInt<4>("h00")) @[Decode.scala 13:121] + node _T_83 = and(io.req.bits.fn, UInt<4>("h08")) @[Decode.scala 13:65] + node _T_85 = eq(_T_83, UInt<4>("h08")) @[Decode.scala 13:121] + node _T_87 = or(UInt<1>("h00"), _T_81) @[Decode.scala 14:30] + node _T_88 = or(_T_87, _T_85) @[Decode.scala 14:30] + node _T_90 = and(io.req.bits.fn, UInt<4>("h05")) @[Decode.scala 13:65] + node _T_92 = eq(_T_90, UInt<4>("h01")) @[Decode.scala 13:121] + node _T_94 = and(io.req.bits.fn, UInt<4>("h02")) @[Decode.scala 13:65] + node _T_96 = eq(_T_94, UInt<4>("h02")) @[Decode.scala 13:121] + node _T_98 = or(UInt<1>("h00"), _T_92) @[Decode.scala 14:30] + node _T_99 = or(_T_98, _T_96) @[Decode.scala 14:30] + node _T_100 = or(_T_99, _T_85) @[Decode.scala 14:30] + node _T_102 = and(io.req.bits.fn, UInt<4>("h09")) @[Decode.scala 13:65] + node _T_104 = eq(_T_102, UInt<4>("h00")) @[Decode.scala 13:121] + node _T_106 = and(io.req.bits.fn, UInt<4>("h03")) @[Decode.scala 13:65] + node _T_108 = eq(_T_106, UInt<4>("h00")) @[Decode.scala 13:121] + node _T_110 = or(UInt<1>("h00"), _T_104) @[Decode.scala 14:30] + node _T_111 = or(_T_110, _T_81) @[Decode.scala 14:30] + node _T_112 = or(_T_111, _T_108) @[Decode.scala 14:30] + node _T_114 = or(UInt<1>("h00"), _T_104) @[Decode.scala 14:30] + node _T_115 = or(_T_114, _T_81) @[Decode.scala 14:30] + node cmdMul = bits(_T_88, 0, 0) @[Multiplier.scala 64:58] + node cmdHi = bits(_T_100, 0, 0) @[Multiplier.scala 64:58] + node lhsSigned = bits(_T_112, 0, 0) @[Multiplier.scala 64:58] + node rhsSigned = bits(_T_115, 0, 0) @[Multiplier.scala 64:58] + node _T_118 = eq(io.req.bits.dw, UInt<1>("h00")) @[Multiplier.scala 67:62] + node _T_119 = and(UInt<1>("h01"), _T_118) @[Multiplier.scala 67:52] + node _T_120 = bits(io.req.bits.in1, 31, 31) @[Multiplier.scala 70:38] + node _T_121 = bits(io.req.bits.in1, 63, 63) @[Multiplier.scala 70:48] + node _T_122 = mux(_T_119, _T_120, _T_121) @[Multiplier.scala 70:29] + node lhs_sign = and(lhsSigned, _T_122) @[Multiplier.scala 70:23] + node _T_123 = bits(lhs_sign, 0, 0) @[Bitwise.scala 71:15] + node _T_126 = mux(_T_123, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12] + node _T_127 = bits(io.req.bits.in1, 63, 32) @[Multiplier.scala 71:43] + node _T_128 = mux(_T_119, _T_126, _T_127) @[Multiplier.scala 71:17] + node _T_129 = bits(io.req.bits.in1, 31, 0) @[Multiplier.scala 72:15] + node lhs_in = cat(_T_128, _T_129) @[Cat.scala 30:58] + node _T_132 = eq(io.req.bits.dw, UInt<1>("h00")) @[Multiplier.scala 67:62] + node _T_133 = and(UInt<1>("h01"), _T_132) @[Multiplier.scala 67:52] + node _T_134 = bits(io.req.bits.in2, 31, 31) @[Multiplier.scala 70:38] + node _T_135 = bits(io.req.bits.in2, 63, 63) @[Multiplier.scala 70:48] + node _T_136 = mux(_T_133, _T_134, _T_135) @[Multiplier.scala 70:29] + node rhs_sign = and(rhsSigned, _T_136) @[Multiplier.scala 70:23] + node _T_137 = bits(rhs_sign, 0, 0) @[Bitwise.scala 71:15] + node _T_140 = mux(_T_137, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12] + node _T_141 = bits(io.req.bits.in2, 63, 32) @[Multiplier.scala 71:43] + node _T_142 = mux(_T_133, _T_140, _T_141) @[Multiplier.scala 71:17] + node _T_143 = bits(io.req.bits.in2, 31, 0) @[Multiplier.scala 72:15] + node rhs_in = cat(_T_142, _T_143) @[Cat.scala 30:58] + node _T_144 = bits(remainder, 128, 64) @[Multiplier.scala 77:29] + node _T_145 = sub(_T_144, divisor) @[Multiplier.scala 77:37] + node _T_146 = asUInt(_T_145) @[Multiplier.scala 77:37] + node subtractor = tail(_T_146, 1) @[Multiplier.scala 77:37] + node _T_147 = bits(remainder, 63, 0) @[Multiplier.scala 78:37] + node _T_149 = sub(UInt<1>("h00"), _T_147) @[Multiplier.scala 78:27] + node _T_150 = asUInt(_T_149) @[Multiplier.scala 78:27] + node negated_remainder = tail(_T_150, 1) @[Multiplier.scala 78:27] + node _T_151 = eq(state, UInt<3>("h01")) @[Multiplier.scala 80:15] + when _T_151 : @[Multiplier.scala 80:33] + node _T_152 = bits(remainder, 63, 63) @[Multiplier.scala 81:20] + node _T_153 = or(_T_152, isMul) @[Multiplier.scala 81:26] + when _T_153 : @[Multiplier.scala 81:36] + remainder <= negated_remainder @[Multiplier.scala 82:17] + skip @[Multiplier.scala 81:36] + node _T_154 = bits(divisor, 63, 63) @[Multiplier.scala 84:18] + node _T_155 = or(_T_154, isMul) @[Multiplier.scala 84:24] + when _T_155 : @[Multiplier.scala 84:34] + divisor <= subtractor @[Multiplier.scala 85:15] + skip @[Multiplier.scala 84:34] + state <= UInt<3>("h02") @[Multiplier.scala 87:11] + skip @[Multiplier.scala 80:33] + node _T_156 = eq(state, UInt<3>("h04")) @[Multiplier.scala 90:15] + when _T_156 : @[Multiplier.scala 90:33] + remainder <= negated_remainder @[Multiplier.scala 91:15] + state <= UInt<3>("h05") @[Multiplier.scala 92:11] + skip @[Multiplier.scala 90:33] + node _T_157 = eq(state, UInt<3>("h03")) @[Multiplier.scala 94:15] + when _T_157 : @[Multiplier.scala 94:31] + node _T_158 = bits(remainder, 128, 65) @[Multiplier.scala 95:27] + remainder <= _T_158 @[Multiplier.scala 95:15] + node _T_159 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) @[Multiplier.scala 96:17] + state <= _T_159 @[Multiplier.scala 96:11] + skip @[Multiplier.scala 94:31] + node _T_160 = eq(state, UInt<3>("h02")) @[Multiplier.scala 98:15] + node _T_161 = and(_T_160, isMul) @[Multiplier.scala 98:26] + when _T_161 : @[Multiplier.scala 98:36] + node _T_162 = bits(remainder, 129, 65) @[Multiplier.scala 99:31] + node _T_163 = bits(remainder, 63, 0) @[Multiplier.scala 99:55] + node _T_164 = cat(_T_162, _T_163) @[Cat.scala 30:58] + node _T_165 = bits(_T_164, 63, 0) @[Multiplier.scala 100:24] + node _T_166 = bits(_T_164, 128, 64) @[Multiplier.scala 101:23] + node _T_167 = asSInt(_T_166) @[Multiplier.scala 101:37] + node _T_168 = asSInt(divisor) @[Multiplier.scala 102:26] + node _T_169 = bits(_T_165, 7, 0) @[Multiplier.scala 103:22] + node _T_170 = mul(_T_168, _T_169) @[Multiplier.scala 103:43] + node _T_171 = add(_T_170, _T_167) @[Multiplier.scala 103:52] + node _T_172 = tail(_T_171, 1) @[Multiplier.scala 103:52] + node _T_173 = asSInt(_T_172) @[Multiplier.scala 103:52] + node _T_174 = bits(_T_165, 63, 8) @[Multiplier.scala 104:38] + node _T_175 = asUInt(_T_173) @[Cat.scala 30:58] + node _T_176 = cat(_T_175, _T_174) @[Cat.scala 30:58] + node _T_179 = mul(count, UInt<4>("h08")) @[Multiplier.scala 106:56] + node _T_180 = bits(_T_179, 5, 0) @[Multiplier.scala 106:72] + node _T_181 = dshr(asSInt(UInt<65>("h010000000000000000")), _T_180) @[Multiplier.scala 106:46] + node _T_182 = bits(_T_181, 63, 0) @[Multiplier.scala 106:91] + node _T_185 = neq(count, UInt<3>("h07")) @[Multiplier.scala 107:47] + node _T_186 = and(UInt<1>("h01"), _T_185) @[Multiplier.scala 107:38] + node _T_188 = neq(count, UInt<1>("h00")) @[Multiplier.scala 107:81] + node _T_189 = and(_T_186, _T_188) @[Multiplier.scala 107:72] + node _T_191 = eq(isHi, UInt<1>("h00")) @[Multiplier.scala 108:7] + node _T_192 = and(_T_189, _T_191) @[Multiplier.scala 107:87] + node _T_193 = not(_T_182) @[Multiplier.scala 108:26] + node _T_194 = and(_T_165, _T_193) @[Multiplier.scala 108:24] + node _T_196 = eq(_T_194, UInt<1>("h00")) @[Multiplier.scala 108:37] + node _T_197 = and(_T_192, _T_196) @[Multiplier.scala 108:13] + node _T_200 = mul(count, UInt<4>("h08")) @[Multiplier.scala 109:44] + node _T_201 = sub(UInt<7>("h040"), _T_200) @[Multiplier.scala 109:36] + node _T_202 = asUInt(_T_201) @[Multiplier.scala 109:36] + node _T_203 = tail(_T_202, 1) @[Multiplier.scala 109:36] + node _T_204 = bits(_T_203, 5, 0) @[Multiplier.scala 109:60] + node _T_205 = dshr(_T_164, _T_204) @[Multiplier.scala 109:27] + node _T_206 = bits(_T_176, 128, 64) @[Multiplier.scala 110:37] + node _T_207 = mux(_T_197, _T_205, _T_176) @[Multiplier.scala 110:55] + node _T_208 = bits(_T_207, 63, 0) @[Multiplier.scala 110:82] + node _T_209 = cat(_T_206, _T_208) @[Cat.scala 30:58] + node _T_210 = shr(_T_209, 64) @[Multiplier.scala 111:34] + node _T_212 = bits(_T_209, 63, 0) @[Multiplier.scala 111:64] + node _T_213 = cat(_T_210, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_214 = cat(_T_213, _T_212) @[Cat.scala 30:58] + remainder <= _T_214 @[Multiplier.scala 111:15] + node _T_216 = add(count, UInt<1>("h01")) @[Multiplier.scala 113:20] + node _T_217 = tail(_T_216, 1) @[Multiplier.scala 113:20] + count <= _T_217 @[Multiplier.scala 113:11] + node _T_219 = eq(count, UInt<3>("h07")) @[Multiplier.scala 114:25] + node _T_220 = or(_T_197, _T_219) @[Multiplier.scala 114:16] + when _T_220 : @[Multiplier.scala 114:51] + node _T_221 = mux(isHi, UInt<3>("h03"), UInt<3>("h05")) @[Multiplier.scala 115:19] + state <= _T_221 @[Multiplier.scala 115:13] + skip @[Multiplier.scala 114:51] + skip @[Multiplier.scala 98:36] + node _T_222 = eq(state, UInt<3>("h02")) @[Multiplier.scala 118:15] + node _T_224 = eq(isMul, UInt<1>("h00")) @[Multiplier.scala 118:29] + node _T_225 = and(_T_222, _T_224) @[Multiplier.scala 118:26] + when _T_225 : @[Multiplier.scala 118:37] + node _T_226 = bits(subtractor, 64, 64) @[Multiplier.scala 122:28] + node _T_227 = bits(remainder, 127, 64) @[Multiplier.scala 123:24] + node _T_228 = bits(subtractor, 63, 0) @[Multiplier.scala 123:45] + node _T_229 = mux(_T_226, _T_227, _T_228) @[Multiplier.scala 123:14] + node _T_230 = bits(remainder, 63, 0) @[Multiplier.scala 123:58] + node _T_232 = eq(_T_226, UInt<1>("h00")) @[Multiplier.scala 123:67] + node _T_233 = cat(_T_229, _T_230) @[Cat.scala 30:58] + node _T_234 = cat(_T_233, _T_232) @[Cat.scala 30:58] + remainder <= _T_234 @[Multiplier.scala 126:15] + node _T_236 = eq(count, UInt<7>("h040")) @[Multiplier.scala 127:17] + when _T_236 : @[Multiplier.scala 127:38] + node _T_237 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) @[Multiplier.scala 128:41] + node _T_238 = mux(isHi, UInt<3>("h03"), _T_237) @[Multiplier.scala 128:19] + state <= _T_238 @[Multiplier.scala 128:13] + skip @[Multiplier.scala 127:38] + node _T_240 = add(count, UInt<1>("h01")) @[Multiplier.scala 132:20] + node _T_241 = tail(_T_240, 1) @[Multiplier.scala 132:20] + count <= _T_241 @[Multiplier.scala 132:11] + node _T_243 = eq(count, UInt<1>("h00")) @[Multiplier.scala 134:24] + node _T_244 = bits(subtractor, 64, 64) @[Multiplier.scala 134:44] + node _T_246 = eq(_T_244, UInt<1>("h00")) @[Multiplier.scala 134:33] + node _T_247 = and(_T_243, _T_246) @[Multiplier.scala 134:30] + node _T_248 = bits(divisor, 63, 0) @[Multiplier.scala 136:36] + node _T_249 = bits(_T_248, 63, 32) @[CircuitMath.scala 35:17] + node _T_250 = bits(_T_248, 31, 0) @[CircuitMath.scala 36:17] + node _T_252 = neq(_T_249, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_253 = bits(_T_249, 31, 16) @[CircuitMath.scala 35:17] + node _T_254 = bits(_T_249, 15, 0) @[CircuitMath.scala 36:17] + node _T_256 = neq(_T_253, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_257 = bits(_T_253, 15, 8) @[CircuitMath.scala 35:17] + node _T_258 = bits(_T_253, 7, 0) @[CircuitMath.scala 36:17] + node _T_260 = neq(_T_257, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_261 = bits(_T_257, 7, 4) @[CircuitMath.scala 35:17] + node _T_262 = bits(_T_257, 3, 0) @[CircuitMath.scala 36:17] + node _T_264 = neq(_T_261, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_265 = bits(_T_261, 3, 3) @[CircuitMath.scala 32:12] + node _T_267 = bits(_T_261, 2, 2) @[CircuitMath.scala 32:12] + node _T_269 = bits(_T_261, 1, 1) @[CircuitMath.scala 30:8] + node _T_270 = mux(_T_267, UInt<2>("h02"), _T_269) @[CircuitMath.scala 32:10] + node _T_271 = mux(_T_265, UInt<2>("h03"), _T_270) @[CircuitMath.scala 32:10] + node _T_272 = bits(_T_262, 3, 3) @[CircuitMath.scala 32:12] + node _T_274 = bits(_T_262, 2, 2) @[CircuitMath.scala 32:12] + node _T_276 = bits(_T_262, 1, 1) @[CircuitMath.scala 30:8] + node _T_277 = mux(_T_274, UInt<2>("h02"), _T_276) @[CircuitMath.scala 32:10] + node _T_278 = mux(_T_272, UInt<2>("h03"), _T_277) @[CircuitMath.scala 32:10] + node _T_279 = mux(_T_264, _T_271, _T_278) @[CircuitMath.scala 38:21] + node _T_280 = cat(_T_264, _T_279) @[Cat.scala 30:58] + node _T_281 = bits(_T_258, 7, 4) @[CircuitMath.scala 35:17] + node _T_282 = bits(_T_258, 3, 0) @[CircuitMath.scala 36:17] + node _T_284 = neq(_T_281, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_285 = bits(_T_281, 3, 3) @[CircuitMath.scala 32:12] + node _T_287 = bits(_T_281, 2, 2) @[CircuitMath.scala 32:12] + node _T_289 = bits(_T_281, 1, 1) @[CircuitMath.scala 30:8] + node _T_290 = mux(_T_287, UInt<2>("h02"), _T_289) @[CircuitMath.scala 32:10] + node _T_291 = mux(_T_285, UInt<2>("h03"), _T_290) @[CircuitMath.scala 32:10] + node _T_292 = bits(_T_282, 3, 3) @[CircuitMath.scala 32:12] + node _T_294 = bits(_T_282, 2, 2) @[CircuitMath.scala 32:12] + node _T_296 = bits(_T_282, 1, 1) @[CircuitMath.scala 30:8] + node _T_297 = mux(_T_294, UInt<2>("h02"), _T_296) @[CircuitMath.scala 32:10] + node _T_298 = mux(_T_292, UInt<2>("h03"), _T_297) @[CircuitMath.scala 32:10] + node _T_299 = mux(_T_284, _T_291, _T_298) @[CircuitMath.scala 38:21] + node _T_300 = cat(_T_284, _T_299) @[Cat.scala 30:58] + node _T_301 = mux(_T_260, _T_280, _T_300) @[CircuitMath.scala 38:21] + node _T_302 = cat(_T_260, _T_301) @[Cat.scala 30:58] + node _T_303 = bits(_T_254, 15, 8) @[CircuitMath.scala 35:17] + node _T_304 = bits(_T_254, 7, 0) @[CircuitMath.scala 36:17] + node _T_306 = neq(_T_303, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_307 = bits(_T_303, 7, 4) @[CircuitMath.scala 35:17] + node _T_308 = bits(_T_303, 3, 0) @[CircuitMath.scala 36:17] + node _T_310 = neq(_T_307, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_311 = bits(_T_307, 3, 3) @[CircuitMath.scala 32:12] + node _T_313 = bits(_T_307, 2, 2) @[CircuitMath.scala 32:12] + node _T_315 = bits(_T_307, 1, 1) @[CircuitMath.scala 30:8] + node _T_316 = mux(_T_313, UInt<2>("h02"), _T_315) @[CircuitMath.scala 32:10] + node _T_317 = mux(_T_311, UInt<2>("h03"), _T_316) @[CircuitMath.scala 32:10] + node _T_318 = bits(_T_308, 3, 3) @[CircuitMath.scala 32:12] + node _T_320 = bits(_T_308, 2, 2) @[CircuitMath.scala 32:12] + node _T_322 = bits(_T_308, 1, 1) @[CircuitMath.scala 30:8] + node _T_323 = mux(_T_320, UInt<2>("h02"), _T_322) @[CircuitMath.scala 32:10] + node _T_324 = mux(_T_318, UInt<2>("h03"), _T_323) @[CircuitMath.scala 32:10] + node _T_325 = mux(_T_310, _T_317, _T_324) @[CircuitMath.scala 38:21] + node _T_326 = cat(_T_310, _T_325) @[Cat.scala 30:58] + node _T_327 = bits(_T_304, 7, 4) @[CircuitMath.scala 35:17] + node _T_328 = bits(_T_304, 3, 0) @[CircuitMath.scala 36:17] + node _T_330 = neq(_T_327, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_331 = bits(_T_327, 3, 3) @[CircuitMath.scala 32:12] + node _T_333 = bits(_T_327, 2, 2) @[CircuitMath.scala 32:12] + node _T_335 = bits(_T_327, 1, 1) @[CircuitMath.scala 30:8] + node _T_336 = mux(_T_333, UInt<2>("h02"), _T_335) @[CircuitMath.scala 32:10] + node _T_337 = mux(_T_331, UInt<2>("h03"), _T_336) @[CircuitMath.scala 32:10] + node _T_338 = bits(_T_328, 3, 3) @[CircuitMath.scala 32:12] + node _T_340 = bits(_T_328, 2, 2) @[CircuitMath.scala 32:12] + node _T_342 = bits(_T_328, 1, 1) @[CircuitMath.scala 30:8] + node _T_343 = mux(_T_340, UInt<2>("h02"), _T_342) @[CircuitMath.scala 32:10] + node _T_344 = mux(_T_338, UInt<2>("h03"), _T_343) @[CircuitMath.scala 32:10] + node _T_345 = mux(_T_330, _T_337, _T_344) @[CircuitMath.scala 38:21] + node _T_346 = cat(_T_330, _T_345) @[Cat.scala 30:58] + node _T_347 = mux(_T_306, _T_326, _T_346) @[CircuitMath.scala 38:21] + node _T_348 = cat(_T_306, _T_347) @[Cat.scala 30:58] + node _T_349 = mux(_T_256, _T_302, _T_348) @[CircuitMath.scala 38:21] + node _T_350 = cat(_T_256, _T_349) @[Cat.scala 30:58] + node _T_351 = bits(_T_250, 31, 16) @[CircuitMath.scala 35:17] + node _T_352 = bits(_T_250, 15, 0) @[CircuitMath.scala 36:17] + node _T_354 = neq(_T_351, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_355 = bits(_T_351, 15, 8) @[CircuitMath.scala 35:17] + node _T_356 = bits(_T_351, 7, 0) @[CircuitMath.scala 36:17] + node _T_358 = neq(_T_355, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_359 = bits(_T_355, 7, 4) @[CircuitMath.scala 35:17] + node _T_360 = bits(_T_355, 3, 0) @[CircuitMath.scala 36:17] + node _T_362 = neq(_T_359, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_363 = bits(_T_359, 3, 3) @[CircuitMath.scala 32:12] + node _T_365 = bits(_T_359, 2, 2) @[CircuitMath.scala 32:12] + node _T_367 = bits(_T_359, 1, 1) @[CircuitMath.scala 30:8] + node _T_368 = mux(_T_365, UInt<2>("h02"), _T_367) @[CircuitMath.scala 32:10] + node _T_369 = mux(_T_363, UInt<2>("h03"), _T_368) @[CircuitMath.scala 32:10] + node _T_370 = bits(_T_360, 3, 3) @[CircuitMath.scala 32:12] + node _T_372 = bits(_T_360, 2, 2) @[CircuitMath.scala 32:12] + node _T_374 = bits(_T_360, 1, 1) @[CircuitMath.scala 30:8] + node _T_375 = mux(_T_372, UInt<2>("h02"), _T_374) @[CircuitMath.scala 32:10] + node _T_376 = mux(_T_370, UInt<2>("h03"), _T_375) @[CircuitMath.scala 32:10] + node _T_377 = mux(_T_362, _T_369, _T_376) @[CircuitMath.scala 38:21] + node _T_378 = cat(_T_362, _T_377) @[Cat.scala 30:58] + node _T_379 = bits(_T_356, 7, 4) @[CircuitMath.scala 35:17] + node _T_380 = bits(_T_356, 3, 0) @[CircuitMath.scala 36:17] + node _T_382 = neq(_T_379, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_383 = bits(_T_379, 3, 3) @[CircuitMath.scala 32:12] + node _T_385 = bits(_T_379, 2, 2) @[CircuitMath.scala 32:12] + node _T_387 = bits(_T_379, 1, 1) @[CircuitMath.scala 30:8] + node _T_388 = mux(_T_385, UInt<2>("h02"), _T_387) @[CircuitMath.scala 32:10] + node _T_389 = mux(_T_383, UInt<2>("h03"), _T_388) @[CircuitMath.scala 32:10] + node _T_390 = bits(_T_380, 3, 3) @[CircuitMath.scala 32:12] + node _T_392 = bits(_T_380, 2, 2) @[CircuitMath.scala 32:12] + node _T_394 = bits(_T_380, 1, 1) @[CircuitMath.scala 30:8] + node _T_395 = mux(_T_392, UInt<2>("h02"), _T_394) @[CircuitMath.scala 32:10] + node _T_396 = mux(_T_390, UInt<2>("h03"), _T_395) @[CircuitMath.scala 32:10] + node _T_397 = mux(_T_382, _T_389, _T_396) @[CircuitMath.scala 38:21] + node _T_398 = cat(_T_382, _T_397) @[Cat.scala 30:58] + node _T_399 = mux(_T_358, _T_378, _T_398) @[CircuitMath.scala 38:21] + node _T_400 = cat(_T_358, _T_399) @[Cat.scala 30:58] + node _T_401 = bits(_T_352, 15, 8) @[CircuitMath.scala 35:17] + node _T_402 = bits(_T_352, 7, 0) @[CircuitMath.scala 36:17] + node _T_404 = neq(_T_401, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_405 = bits(_T_401, 7, 4) @[CircuitMath.scala 35:17] + node _T_406 = bits(_T_401, 3, 0) @[CircuitMath.scala 36:17] + node _T_408 = neq(_T_405, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_409 = bits(_T_405, 3, 3) @[CircuitMath.scala 32:12] + node _T_411 = bits(_T_405, 2, 2) @[CircuitMath.scala 32:12] + node _T_413 = bits(_T_405, 1, 1) @[CircuitMath.scala 30:8] + node _T_414 = mux(_T_411, UInt<2>("h02"), _T_413) @[CircuitMath.scala 32:10] + node _T_415 = mux(_T_409, UInt<2>("h03"), _T_414) @[CircuitMath.scala 32:10] + node _T_416 = bits(_T_406, 3, 3) @[CircuitMath.scala 32:12] + node _T_418 = bits(_T_406, 2, 2) @[CircuitMath.scala 32:12] + node _T_420 = bits(_T_406, 1, 1) @[CircuitMath.scala 30:8] + node _T_421 = mux(_T_418, UInt<2>("h02"), _T_420) @[CircuitMath.scala 32:10] + node _T_422 = mux(_T_416, UInt<2>("h03"), _T_421) @[CircuitMath.scala 32:10] + node _T_423 = mux(_T_408, _T_415, _T_422) @[CircuitMath.scala 38:21] + node _T_424 = cat(_T_408, _T_423) @[Cat.scala 30:58] + node _T_425 = bits(_T_402, 7, 4) @[CircuitMath.scala 35:17] + node _T_426 = bits(_T_402, 3, 0) @[CircuitMath.scala 36:17] + node _T_428 = neq(_T_425, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_429 = bits(_T_425, 3, 3) @[CircuitMath.scala 32:12] + node _T_431 = bits(_T_425, 2, 2) @[CircuitMath.scala 32:12] + node _T_433 = bits(_T_425, 1, 1) @[CircuitMath.scala 30:8] + node _T_434 = mux(_T_431, UInt<2>("h02"), _T_433) @[CircuitMath.scala 32:10] + node _T_435 = mux(_T_429, UInt<2>("h03"), _T_434) @[CircuitMath.scala 32:10] + node _T_436 = bits(_T_426, 3, 3) @[CircuitMath.scala 32:12] + node _T_438 = bits(_T_426, 2, 2) @[CircuitMath.scala 32:12] + node _T_440 = bits(_T_426, 1, 1) @[CircuitMath.scala 30:8] + node _T_441 = mux(_T_438, UInt<2>("h02"), _T_440) @[CircuitMath.scala 32:10] + node _T_442 = mux(_T_436, UInt<2>("h03"), _T_441) @[CircuitMath.scala 32:10] + node _T_443 = mux(_T_428, _T_435, _T_442) @[CircuitMath.scala 38:21] + node _T_444 = cat(_T_428, _T_443) @[Cat.scala 30:58] + node _T_445 = mux(_T_404, _T_424, _T_444) @[CircuitMath.scala 38:21] + node _T_446 = cat(_T_404, _T_445) @[Cat.scala 30:58] + node _T_447 = mux(_T_354, _T_400, _T_446) @[CircuitMath.scala 38:21] + node _T_448 = cat(_T_354, _T_447) @[Cat.scala 30:58] + node _T_449 = mux(_T_252, _T_350, _T_448) @[CircuitMath.scala 38:21] + node _T_450 = cat(_T_252, _T_449) @[Cat.scala 30:58] + node _T_451 = bits(remainder, 63, 0) @[Multiplier.scala 137:39] + node _T_452 = bits(_T_451, 63, 32) @[CircuitMath.scala 35:17] + node _T_453 = bits(_T_451, 31, 0) @[CircuitMath.scala 36:17] + node _T_455 = neq(_T_452, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_456 = bits(_T_452, 31, 16) @[CircuitMath.scala 35:17] + node _T_457 = bits(_T_452, 15, 0) @[CircuitMath.scala 36:17] + node _T_459 = neq(_T_456, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_460 = bits(_T_456, 15, 8) @[CircuitMath.scala 35:17] + node _T_461 = bits(_T_456, 7, 0) @[CircuitMath.scala 36:17] + node _T_463 = neq(_T_460, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_464 = bits(_T_460, 7, 4) @[CircuitMath.scala 35:17] + node _T_465 = bits(_T_460, 3, 0) @[CircuitMath.scala 36:17] + node _T_467 = neq(_T_464, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_468 = bits(_T_464, 3, 3) @[CircuitMath.scala 32:12] + node _T_470 = bits(_T_464, 2, 2) @[CircuitMath.scala 32:12] + node _T_472 = bits(_T_464, 1, 1) @[CircuitMath.scala 30:8] + node _T_473 = mux(_T_470, UInt<2>("h02"), _T_472) @[CircuitMath.scala 32:10] + node _T_474 = mux(_T_468, UInt<2>("h03"), _T_473) @[CircuitMath.scala 32:10] + node _T_475 = bits(_T_465, 3, 3) @[CircuitMath.scala 32:12] + node _T_477 = bits(_T_465, 2, 2) @[CircuitMath.scala 32:12] + node _T_479 = bits(_T_465, 1, 1) @[CircuitMath.scala 30:8] + node _T_480 = mux(_T_477, UInt<2>("h02"), _T_479) @[CircuitMath.scala 32:10] + node _T_481 = mux(_T_475, UInt<2>("h03"), _T_480) @[CircuitMath.scala 32:10] + node _T_482 = mux(_T_467, _T_474, _T_481) @[CircuitMath.scala 38:21] + node _T_483 = cat(_T_467, _T_482) @[Cat.scala 30:58] + node _T_484 = bits(_T_461, 7, 4) @[CircuitMath.scala 35:17] + node _T_485 = bits(_T_461, 3, 0) @[CircuitMath.scala 36:17] + node _T_487 = neq(_T_484, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_488 = bits(_T_484, 3, 3) @[CircuitMath.scala 32:12] + node _T_490 = bits(_T_484, 2, 2) @[CircuitMath.scala 32:12] + node _T_492 = bits(_T_484, 1, 1) @[CircuitMath.scala 30:8] + node _T_493 = mux(_T_490, UInt<2>("h02"), _T_492) @[CircuitMath.scala 32:10] + node _T_494 = mux(_T_488, UInt<2>("h03"), _T_493) @[CircuitMath.scala 32:10] + node _T_495 = bits(_T_485, 3, 3) @[CircuitMath.scala 32:12] + node _T_497 = bits(_T_485, 2, 2) @[CircuitMath.scala 32:12] + node _T_499 = bits(_T_485, 1, 1) @[CircuitMath.scala 30:8] + node _T_500 = mux(_T_497, UInt<2>("h02"), _T_499) @[CircuitMath.scala 32:10] + node _T_501 = mux(_T_495, UInt<2>("h03"), _T_500) @[CircuitMath.scala 32:10] + node _T_502 = mux(_T_487, _T_494, _T_501) @[CircuitMath.scala 38:21] + node _T_503 = cat(_T_487, _T_502) @[Cat.scala 30:58] + node _T_504 = mux(_T_463, _T_483, _T_503) @[CircuitMath.scala 38:21] + node _T_505 = cat(_T_463, _T_504) @[Cat.scala 30:58] + node _T_506 = bits(_T_457, 15, 8) @[CircuitMath.scala 35:17] + node _T_507 = bits(_T_457, 7, 0) @[CircuitMath.scala 36:17] + node _T_509 = neq(_T_506, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_510 = bits(_T_506, 7, 4) @[CircuitMath.scala 35:17] + node _T_511 = bits(_T_506, 3, 0) @[CircuitMath.scala 36:17] + node _T_513 = neq(_T_510, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_514 = bits(_T_510, 3, 3) @[CircuitMath.scala 32:12] + node _T_516 = bits(_T_510, 2, 2) @[CircuitMath.scala 32:12] + node _T_518 = bits(_T_510, 1, 1) @[CircuitMath.scala 30:8] + node _T_519 = mux(_T_516, UInt<2>("h02"), _T_518) @[CircuitMath.scala 32:10] + node _T_520 = mux(_T_514, UInt<2>("h03"), _T_519) @[CircuitMath.scala 32:10] + node _T_521 = bits(_T_511, 3, 3) @[CircuitMath.scala 32:12] + node _T_523 = bits(_T_511, 2, 2) @[CircuitMath.scala 32:12] + node _T_525 = bits(_T_511, 1, 1) @[CircuitMath.scala 30:8] + node _T_526 = mux(_T_523, UInt<2>("h02"), _T_525) @[CircuitMath.scala 32:10] + node _T_527 = mux(_T_521, UInt<2>("h03"), _T_526) @[CircuitMath.scala 32:10] + node _T_528 = mux(_T_513, _T_520, _T_527) @[CircuitMath.scala 38:21] + node _T_529 = cat(_T_513, _T_528) @[Cat.scala 30:58] + node _T_530 = bits(_T_507, 7, 4) @[CircuitMath.scala 35:17] + node _T_531 = bits(_T_507, 3, 0) @[CircuitMath.scala 36:17] + node _T_533 = neq(_T_530, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_534 = bits(_T_530, 3, 3) @[CircuitMath.scala 32:12] + node _T_536 = bits(_T_530, 2, 2) @[CircuitMath.scala 32:12] + node _T_538 = bits(_T_530, 1, 1) @[CircuitMath.scala 30:8] + node _T_539 = mux(_T_536, UInt<2>("h02"), _T_538) @[CircuitMath.scala 32:10] + node _T_540 = mux(_T_534, UInt<2>("h03"), _T_539) @[CircuitMath.scala 32:10] + node _T_541 = bits(_T_531, 3, 3) @[CircuitMath.scala 32:12] + node _T_543 = bits(_T_531, 2, 2) @[CircuitMath.scala 32:12] + node _T_545 = bits(_T_531, 1, 1) @[CircuitMath.scala 30:8] + node _T_546 = mux(_T_543, UInt<2>("h02"), _T_545) @[CircuitMath.scala 32:10] + node _T_547 = mux(_T_541, UInt<2>("h03"), _T_546) @[CircuitMath.scala 32:10] + node _T_548 = mux(_T_533, _T_540, _T_547) @[CircuitMath.scala 38:21] + node _T_549 = cat(_T_533, _T_548) @[Cat.scala 30:58] + node _T_550 = mux(_T_509, _T_529, _T_549) @[CircuitMath.scala 38:21] + node _T_551 = cat(_T_509, _T_550) @[Cat.scala 30:58] + node _T_552 = mux(_T_459, _T_505, _T_551) @[CircuitMath.scala 38:21] + node _T_553 = cat(_T_459, _T_552) @[Cat.scala 30:58] + node _T_554 = bits(_T_453, 31, 16) @[CircuitMath.scala 35:17] + node _T_555 = bits(_T_453, 15, 0) @[CircuitMath.scala 36:17] + node _T_557 = neq(_T_554, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_558 = bits(_T_554, 15, 8) @[CircuitMath.scala 35:17] + node _T_559 = bits(_T_554, 7, 0) @[CircuitMath.scala 36:17] + node _T_561 = neq(_T_558, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_562 = bits(_T_558, 7, 4) @[CircuitMath.scala 35:17] + node _T_563 = bits(_T_558, 3, 0) @[CircuitMath.scala 36:17] + node _T_565 = neq(_T_562, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_566 = bits(_T_562, 3, 3) @[CircuitMath.scala 32:12] + node _T_568 = bits(_T_562, 2, 2) @[CircuitMath.scala 32:12] + node _T_570 = bits(_T_562, 1, 1) @[CircuitMath.scala 30:8] + node _T_571 = mux(_T_568, UInt<2>("h02"), _T_570) @[CircuitMath.scala 32:10] + node _T_572 = mux(_T_566, UInt<2>("h03"), _T_571) @[CircuitMath.scala 32:10] + node _T_573 = bits(_T_563, 3, 3) @[CircuitMath.scala 32:12] + node _T_575 = bits(_T_563, 2, 2) @[CircuitMath.scala 32:12] + node _T_577 = bits(_T_563, 1, 1) @[CircuitMath.scala 30:8] + node _T_578 = mux(_T_575, UInt<2>("h02"), _T_577) @[CircuitMath.scala 32:10] + node _T_579 = mux(_T_573, UInt<2>("h03"), _T_578) @[CircuitMath.scala 32:10] + node _T_580 = mux(_T_565, _T_572, _T_579) @[CircuitMath.scala 38:21] + node _T_581 = cat(_T_565, _T_580) @[Cat.scala 30:58] + node _T_582 = bits(_T_559, 7, 4) @[CircuitMath.scala 35:17] + node _T_583 = bits(_T_559, 3, 0) @[CircuitMath.scala 36:17] + node _T_585 = neq(_T_582, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_586 = bits(_T_582, 3, 3) @[CircuitMath.scala 32:12] + node _T_588 = bits(_T_582, 2, 2) @[CircuitMath.scala 32:12] + node _T_590 = bits(_T_582, 1, 1) @[CircuitMath.scala 30:8] + node _T_591 = mux(_T_588, UInt<2>("h02"), _T_590) @[CircuitMath.scala 32:10] + node _T_592 = mux(_T_586, UInt<2>("h03"), _T_591) @[CircuitMath.scala 32:10] + node _T_593 = bits(_T_583, 3, 3) @[CircuitMath.scala 32:12] + node _T_595 = bits(_T_583, 2, 2) @[CircuitMath.scala 32:12] + node _T_597 = bits(_T_583, 1, 1) @[CircuitMath.scala 30:8] + node _T_598 = mux(_T_595, UInt<2>("h02"), _T_597) @[CircuitMath.scala 32:10] + node _T_599 = mux(_T_593, UInt<2>("h03"), _T_598) @[CircuitMath.scala 32:10] + node _T_600 = mux(_T_585, _T_592, _T_599) @[CircuitMath.scala 38:21] + node _T_601 = cat(_T_585, _T_600) @[Cat.scala 30:58] + node _T_602 = mux(_T_561, _T_581, _T_601) @[CircuitMath.scala 38:21] + node _T_603 = cat(_T_561, _T_602) @[Cat.scala 30:58] + node _T_604 = bits(_T_555, 15, 8) @[CircuitMath.scala 35:17] + node _T_605 = bits(_T_555, 7, 0) @[CircuitMath.scala 36:17] + node _T_607 = neq(_T_604, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_608 = bits(_T_604, 7, 4) @[CircuitMath.scala 35:17] + node _T_609 = bits(_T_604, 3, 0) @[CircuitMath.scala 36:17] + node _T_611 = neq(_T_608, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_612 = bits(_T_608, 3, 3) @[CircuitMath.scala 32:12] + node _T_614 = bits(_T_608, 2, 2) @[CircuitMath.scala 32:12] + node _T_616 = bits(_T_608, 1, 1) @[CircuitMath.scala 30:8] + node _T_617 = mux(_T_614, UInt<2>("h02"), _T_616) @[CircuitMath.scala 32:10] + node _T_618 = mux(_T_612, UInt<2>("h03"), _T_617) @[CircuitMath.scala 32:10] + node _T_619 = bits(_T_609, 3, 3) @[CircuitMath.scala 32:12] + node _T_621 = bits(_T_609, 2, 2) @[CircuitMath.scala 32:12] + node _T_623 = bits(_T_609, 1, 1) @[CircuitMath.scala 30:8] + node _T_624 = mux(_T_621, UInt<2>("h02"), _T_623) @[CircuitMath.scala 32:10] + node _T_625 = mux(_T_619, UInt<2>("h03"), _T_624) @[CircuitMath.scala 32:10] + node _T_626 = mux(_T_611, _T_618, _T_625) @[CircuitMath.scala 38:21] + node _T_627 = cat(_T_611, _T_626) @[Cat.scala 30:58] + node _T_628 = bits(_T_605, 7, 4) @[CircuitMath.scala 35:17] + node _T_629 = bits(_T_605, 3, 0) @[CircuitMath.scala 36:17] + node _T_631 = neq(_T_628, UInt<1>("h00")) @[CircuitMath.scala 37:22] + node _T_632 = bits(_T_628, 3, 3) @[CircuitMath.scala 32:12] + node _T_634 = bits(_T_628, 2, 2) @[CircuitMath.scala 32:12] + node _T_636 = bits(_T_628, 1, 1) @[CircuitMath.scala 30:8] + node _T_637 = mux(_T_634, UInt<2>("h02"), _T_636) @[CircuitMath.scala 32:10] + node _T_638 = mux(_T_632, UInt<2>("h03"), _T_637) @[CircuitMath.scala 32:10] + node _T_639 = bits(_T_629, 3, 3) @[CircuitMath.scala 32:12] + node _T_641 = bits(_T_629, 2, 2) @[CircuitMath.scala 32:12] + node _T_643 = bits(_T_629, 1, 1) @[CircuitMath.scala 30:8] + node _T_644 = mux(_T_641, UInt<2>("h02"), _T_643) @[CircuitMath.scala 32:10] + node _T_645 = mux(_T_639, UInt<2>("h03"), _T_644) @[CircuitMath.scala 32:10] + node _T_646 = mux(_T_631, _T_638, _T_645) @[CircuitMath.scala 38:21] + node _T_647 = cat(_T_631, _T_646) @[Cat.scala 30:58] + node _T_648 = mux(_T_607, _T_627, _T_647) @[CircuitMath.scala 38:21] + node _T_649 = cat(_T_607, _T_648) @[Cat.scala 30:58] + node _T_650 = mux(_T_557, _T_603, _T_649) @[CircuitMath.scala 38:21] + node _T_651 = cat(_T_557, _T_650) @[Cat.scala 30:58] + node _T_652 = mux(_T_455, _T_553, _T_651) @[CircuitMath.scala 38:21] + node _T_653 = cat(_T_455, _T_652) @[Cat.scala 30:58] + node _T_655 = add(UInt<6>("h03f"), _T_450) @[Multiplier.scala 138:31] + node _T_656 = tail(_T_655, 1) @[Multiplier.scala 138:31] + node _T_657 = sub(_T_656, _T_653) @[Multiplier.scala 138:44] + node _T_658 = asUInt(_T_657) @[Multiplier.scala 138:44] + node _T_659 = tail(_T_658, 1) @[Multiplier.scala 138:44] + node _T_660 = gt(_T_450, _T_653) @[Multiplier.scala 139:33] + node _T_662 = eq(count, UInt<1>("h00")) @[Multiplier.scala 140:24] + node _T_664 = eq(_T_247, UInt<1>("h00")) @[Multiplier.scala 140:33] + node _T_665 = and(_T_662, _T_664) @[Multiplier.scala 140:30] + node _T_667 = geq(_T_659, UInt<1>("h01")) @[Multiplier.scala 140:53] + node _T_668 = or(_T_667, _T_660) @[Multiplier.scala 140:70] + node _T_669 = and(_T_665, _T_668) @[Multiplier.scala 140:41] + when _T_669 : @[Multiplier.scala 141:19] + node _T_671 = mux(_T_660, UInt<6>("h03f"), _T_659) @[Multiplier.scala 142:22] + node _T_672 = shr(_T_671, 0) @[Multiplier.scala 142:53] + node _T_673 = shl(_T_672, 0) @[Multiplier.scala 143:25] + node _T_674 = bits(remainder, 63, 0) @[Multiplier.scala 144:31] + node _T_675 = dshl(_T_674, _T_673) @[Multiplier.scala 144:39] + remainder <= _T_675 @[Multiplier.scala 144:19] + count <= _T_672 @[Multiplier.scala 145:15] + skip @[Multiplier.scala 141:19] + node _T_677 = eq(isHi, UInt<1>("h00")) @[Multiplier.scala 148:21] + node _T_678 = and(_T_247, _T_677) @[Multiplier.scala 148:18] + when _T_678 : @[Multiplier.scala 148:28] + neg_out <= UInt<1>("h00") @[Multiplier.scala 148:38] + skip @[Multiplier.scala 148:28] + skip @[Multiplier.scala 118:37] + node _T_680 = and(io.resp.ready, io.resp.valid) @[Decoupled.scala 30:37] + node _T_681 = or(_T_680, io.kill) @[Multiplier.scala 150:24] + when _T_681 : @[Multiplier.scala 150:36] + state <= UInt<3>("h00") @[Multiplier.scala 151:11] + skip @[Multiplier.scala 150:36] + node _T_682 = and(io.req.ready, io.req.valid) @[Decoupled.scala 30:37] + when _T_682 : @[Multiplier.scala 153:24] + node _T_684 = eq(cmdMul, UInt<1>("h00")) @[Multiplier.scala 154:42] + node _T_685 = and(rhs_sign, _T_684) @[Multiplier.scala 154:39] + node _T_686 = or(lhs_sign, _T_685) @[Multiplier.scala 154:27] + node _T_687 = mux(_T_686, UInt<3>("h01"), UInt<3>("h02")) @[Multiplier.scala 154:17] + state <= _T_687 @[Multiplier.scala 154:11] + isMul <= cmdMul @[Multiplier.scala 155:11] + isHi <= cmdHi @[Multiplier.scala 156:10] + count <= UInt<1>("h00") @[Multiplier.scala 157:11] + node _T_690 = eq(cmdMul, UInt<1>("h00")) @[Multiplier.scala 158:16] + node _T_691 = neq(lhs_sign, rhs_sign) @[Multiplier.scala 158:57] + node _T_692 = mux(cmdHi, lhs_sign, _T_691) @[Multiplier.scala 158:30] + node _T_693 = and(_T_690, _T_692) @[Multiplier.scala 158:24] + neg_out <= _T_693 @[Multiplier.scala 158:13] + node _T_694 = cat(rhs_sign, rhs_in) @[Cat.scala 30:58] + divisor <= _T_694 @[Multiplier.scala 159:13] + remainder <= lhs_in @[Multiplier.scala 160:15] + req <- io.req.bits @[Multiplier.scala 161:9] + skip @[Multiplier.scala 153:24] + io.resp.bits <- req @[Multiplier.scala 164:16] + node _T_697 = eq(req.dw, UInt<1>("h00")) @[Multiplier.scala 67:62] + node _T_698 = and(UInt<1>("h01"), _T_697) @[Multiplier.scala 67:52] + node _T_699 = bits(remainder, 31, 31) @[Multiplier.scala 165:67] + node _T_700 = bits(_T_699, 0, 0) @[Bitwise.scala 71:15] + node _T_703 = mux(_T_700, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 71:12] + node _T_704 = bits(remainder, 31, 0) @[Multiplier.scala 165:86] + node _T_705 = cat(_T_703, _T_704) @[Cat.scala 30:58] + node _T_706 = bits(remainder, 63, 0) @[Multiplier.scala 165:107] + node _T_707 = mux(_T_698, _T_705, _T_706) @[Multiplier.scala 165:27] + io.resp.bits.data <= _T_707 @[Multiplier.scala 165:21] + node _T_708 = eq(state, UInt<3>("h05")) @[Multiplier.scala 166:26] + io.resp.valid <= _T_708 @[Multiplier.scala 166:17] + node _T_709 = eq(state, UInt<3>("h00")) @[Multiplier.scala 167:25] + io.req.ready <= _T_709 @[Multiplier.scala 167:16] + + module RVCExpander : + input clock : Clock + input reset : UInt<1> + output io : {flip in : UInt<32>, out : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, rvc : UInt<1>} + + io is invalid + io is invalid + node _T_12 = bits(io.in, 1, 0) @[RVC.scala 162:20] + node _T_14 = neq(_T_12, UInt<2>("h03")) @[RVC.scala 162:26] + io.rvc <= _T_14 @[RVC.scala 162:12] + node _T_15 = bits(io.in, 12, 5) @[RVC.scala 53:22] + node _T_17 = neq(_T_15, UInt<1>("h00")) @[RVC.scala 53:29] + node _T_20 = mux(_T_17, UInt<7>("h013"), UInt<7>("h01f")) @[RVC.scala 53:20] + node _T_21 = bits(io.in, 10, 7) @[RVC.scala 34:26] + node _T_22 = bits(io.in, 12, 11) @[RVC.scala 34:35] + node _T_23 = bits(io.in, 5, 5) @[RVC.scala 34:45] + node _T_24 = bits(io.in, 6, 6) @[RVC.scala 34:51] + node _T_26 = cat(_T_24, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_27 = cat(_T_21, _T_22) @[Cat.scala 30:58] + node _T_28 = cat(_T_27, _T_23) @[Cat.scala 30:58] + node _T_29 = cat(_T_28, _T_26) @[Cat.scala 30:58] + node _T_33 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_34 = cat(UInt<2>("h01"), _T_33) @[Cat.scala 30:58] + node _T_35 = cat(_T_34, _T_20) @[Cat.scala 30:58] + node _T_36 = cat(_T_29, UInt<5>("h02")) @[Cat.scala 30:58] + node _T_37 = cat(_T_36, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_38 = cat(_T_37, _T_35) @[Cat.scala 30:58] + node _T_40 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_41 = cat(UInt<2>("h01"), _T_40) @[Cat.scala 30:58] + node _T_44 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_45 = cat(UInt<2>("h01"), _T_44) @[Cat.scala 30:58] + node _T_46 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_53 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_53 is invalid @[RVC.scala 21:19] + _T_53.bits <= _T_38 @[RVC.scala 22:14] + _T_53.rd <= _T_41 @[RVC.scala 23:12] + _T_53.rs1 <= UInt<5>("h02") @[RVC.scala 24:13] + _T_53.rs2 <= _T_45 @[RVC.scala 25:13] + _T_53.rs3 <= _T_46 @[RVC.scala 26:13] + node _T_59 = bits(io.in, 6, 5) @[RVC.scala 36:20] + node _T_60 = bits(io.in, 12, 10) @[RVC.scala 36:28] + node _T_62 = cat(_T_59, _T_60) @[Cat.scala 30:58] + node _T_63 = cat(_T_62, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_65 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_66 = cat(UInt<2>("h01"), _T_65) @[Cat.scala 30:58] + node _T_69 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_70 = cat(UInt<2>("h01"), _T_69) @[Cat.scala 30:58] + node _T_72 = cat(_T_70, UInt<7>("h07")) @[Cat.scala 30:58] + node _T_73 = cat(_T_63, _T_66) @[Cat.scala 30:58] + node _T_74 = cat(_T_73, UInt<3>("h03")) @[Cat.scala 30:58] + node _T_75 = cat(_T_74, _T_72) @[Cat.scala 30:58] + node _T_77 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_78 = cat(UInt<2>("h01"), _T_77) @[Cat.scala 30:58] + node _T_80 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_81 = cat(UInt<2>("h01"), _T_80) @[Cat.scala 30:58] + node _T_83 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_84 = cat(UInt<2>("h01"), _T_83) @[Cat.scala 30:58] + node _T_85 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_92 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_92 is invalid @[RVC.scala 21:19] + _T_92.bits <= _T_75 @[RVC.scala 22:14] + _T_92.rd <= _T_78 @[RVC.scala 23:12] + _T_92.rs1 <= _T_81 @[RVC.scala 24:13] + _T_92.rs2 <= _T_84 @[RVC.scala 25:13] + _T_92.rs3 <= _T_85 @[RVC.scala 26:13] + node _T_98 = bits(io.in, 5, 5) @[RVC.scala 35:20] + node _T_99 = bits(io.in, 12, 10) @[RVC.scala 35:26] + node _T_100 = bits(io.in, 6, 6) @[RVC.scala 35:36] + node _T_102 = cat(_T_100, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_103 = cat(_T_98, _T_99) @[Cat.scala 30:58] + node _T_104 = cat(_T_103, _T_102) @[Cat.scala 30:58] + node _T_106 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_107 = cat(UInt<2>("h01"), _T_106) @[Cat.scala 30:58] + node _T_110 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_111 = cat(UInt<2>("h01"), _T_110) @[Cat.scala 30:58] + node _T_113 = cat(_T_111, UInt<7>("h03")) @[Cat.scala 30:58] + node _T_114 = cat(_T_104, _T_107) @[Cat.scala 30:58] + node _T_115 = cat(_T_114, UInt<3>("h02")) @[Cat.scala 30:58] + node _T_116 = cat(_T_115, _T_113) @[Cat.scala 30:58] + node _T_118 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_119 = cat(UInt<2>("h01"), _T_118) @[Cat.scala 30:58] + node _T_121 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_122 = cat(UInt<2>("h01"), _T_121) @[Cat.scala 30:58] + node _T_124 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_125 = cat(UInt<2>("h01"), _T_124) @[Cat.scala 30:58] + node _T_126 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_133 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_133 is invalid @[RVC.scala 21:19] + _T_133.bits <= _T_116 @[RVC.scala 22:14] + _T_133.rd <= _T_119 @[RVC.scala 23:12] + _T_133.rs1 <= _T_122 @[RVC.scala 24:13] + _T_133.rs2 <= _T_125 @[RVC.scala 25:13] + _T_133.rs3 <= _T_126 @[RVC.scala 26:13] + node _T_139 = bits(io.in, 6, 5) @[RVC.scala 36:20] + node _T_140 = bits(io.in, 12, 10) @[RVC.scala 36:28] + node _T_142 = cat(_T_139, _T_140) @[Cat.scala 30:58] + node _T_143 = cat(_T_142, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_145 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_146 = cat(UInt<2>("h01"), _T_145) @[Cat.scala 30:58] + node _T_149 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_150 = cat(UInt<2>("h01"), _T_149) @[Cat.scala 30:58] + node _T_152 = cat(_T_150, UInt<7>("h03")) @[Cat.scala 30:58] + node _T_153 = cat(_T_143, _T_146) @[Cat.scala 30:58] + node _T_154 = cat(_T_153, UInt<3>("h03")) @[Cat.scala 30:58] + node _T_155 = cat(_T_154, _T_152) @[Cat.scala 30:58] + node _T_157 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_158 = cat(UInt<2>("h01"), _T_157) @[Cat.scala 30:58] + node _T_160 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_161 = cat(UInt<2>("h01"), _T_160) @[Cat.scala 30:58] + node _T_163 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_164 = cat(UInt<2>("h01"), _T_163) @[Cat.scala 30:58] + node _T_165 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_172 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_172 is invalid @[RVC.scala 21:19] + _T_172.bits <= _T_155 @[RVC.scala 22:14] + _T_172.rd <= _T_158 @[RVC.scala 23:12] + _T_172.rs1 <= _T_161 @[RVC.scala 24:13] + _T_172.rs2 <= _T_164 @[RVC.scala 25:13] + _T_172.rs3 <= _T_165 @[RVC.scala 26:13] + node _T_178 = bits(io.in, 5, 5) @[RVC.scala 35:20] + node _T_179 = bits(io.in, 12, 10) @[RVC.scala 35:26] + node _T_180 = bits(io.in, 6, 6) @[RVC.scala 35:36] + node _T_182 = cat(_T_180, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_183 = cat(_T_178, _T_179) @[Cat.scala 30:58] + node _T_184 = cat(_T_183, _T_182) @[Cat.scala 30:58] + node _T_185 = shr(_T_184, 5) @[RVC.scala 63:32] + node _T_187 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_188 = cat(UInt<2>("h01"), _T_187) @[Cat.scala 30:58] + node _T_190 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_191 = cat(UInt<2>("h01"), _T_190) @[Cat.scala 30:58] + node _T_193 = bits(io.in, 5, 5) @[RVC.scala 35:20] + node _T_194 = bits(io.in, 12, 10) @[RVC.scala 35:26] + node _T_195 = bits(io.in, 6, 6) @[RVC.scala 35:36] + node _T_197 = cat(_T_195, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_198 = cat(_T_193, _T_194) @[Cat.scala 30:58] + node _T_199 = cat(_T_198, _T_197) @[Cat.scala 30:58] + node _T_200 = bits(_T_199, 4, 0) @[RVC.scala 63:66] + node _T_202 = cat(UInt<3>("h02"), _T_200) @[Cat.scala 30:58] + node _T_203 = cat(_T_202, UInt<7>("h02f")) @[Cat.scala 30:58] + node _T_204 = cat(_T_185, _T_188) @[Cat.scala 30:58] + node _T_205 = cat(_T_204, _T_191) @[Cat.scala 30:58] + node _T_206 = cat(_T_205, _T_203) @[Cat.scala 30:58] + node _T_208 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_209 = cat(UInt<2>("h01"), _T_208) @[Cat.scala 30:58] + node _T_211 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_212 = cat(UInt<2>("h01"), _T_211) @[Cat.scala 30:58] + node _T_214 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_215 = cat(UInt<2>("h01"), _T_214) @[Cat.scala 30:58] + node _T_216 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_223 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_223 is invalid @[RVC.scala 21:19] + _T_223.bits <= _T_206 @[RVC.scala 22:14] + _T_223.rd <= _T_209 @[RVC.scala 23:12] + _T_223.rs1 <= _T_212 @[RVC.scala 24:13] + _T_223.rs2 <= _T_215 @[RVC.scala 25:13] + _T_223.rs3 <= _T_216 @[RVC.scala 26:13] + node _T_229 = bits(io.in, 6, 5) @[RVC.scala 36:20] + node _T_230 = bits(io.in, 12, 10) @[RVC.scala 36:28] + node _T_232 = cat(_T_229, _T_230) @[Cat.scala 30:58] + node _T_233 = cat(_T_232, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_234 = shr(_T_233, 5) @[RVC.scala 66:30] + node _T_236 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_237 = cat(UInt<2>("h01"), _T_236) @[Cat.scala 30:58] + node _T_239 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_240 = cat(UInt<2>("h01"), _T_239) @[Cat.scala 30:58] + node _T_242 = bits(io.in, 6, 5) @[RVC.scala 36:20] + node _T_243 = bits(io.in, 12, 10) @[RVC.scala 36:28] + node _T_245 = cat(_T_242, _T_243) @[Cat.scala 30:58] + node _T_246 = cat(_T_245, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_247 = bits(_T_246, 4, 0) @[RVC.scala 66:64] + node _T_249 = cat(UInt<3>("h03"), _T_247) @[Cat.scala 30:58] + node _T_250 = cat(_T_249, UInt<7>("h027")) @[Cat.scala 30:58] + node _T_251 = cat(_T_234, _T_237) @[Cat.scala 30:58] + node _T_252 = cat(_T_251, _T_240) @[Cat.scala 30:58] + node _T_253 = cat(_T_252, _T_250) @[Cat.scala 30:58] + node _T_255 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_256 = cat(UInt<2>("h01"), _T_255) @[Cat.scala 30:58] + node _T_258 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_259 = cat(UInt<2>("h01"), _T_258) @[Cat.scala 30:58] + node _T_261 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_262 = cat(UInt<2>("h01"), _T_261) @[Cat.scala 30:58] + node _T_263 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_270 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_270 is invalid @[RVC.scala 21:19] + _T_270.bits <= _T_253 @[RVC.scala 22:14] + _T_270.rd <= _T_256 @[RVC.scala 23:12] + _T_270.rs1 <= _T_259 @[RVC.scala 24:13] + _T_270.rs2 <= _T_262 @[RVC.scala 25:13] + _T_270.rs3 <= _T_263 @[RVC.scala 26:13] + node _T_276 = bits(io.in, 5, 5) @[RVC.scala 35:20] + node _T_277 = bits(io.in, 12, 10) @[RVC.scala 35:26] + node _T_278 = bits(io.in, 6, 6) @[RVC.scala 35:36] + node _T_280 = cat(_T_278, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_281 = cat(_T_276, _T_277) @[Cat.scala 30:58] + node _T_282 = cat(_T_281, _T_280) @[Cat.scala 30:58] + node _T_283 = shr(_T_282, 5) @[RVC.scala 65:29] + node _T_285 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_286 = cat(UInt<2>("h01"), _T_285) @[Cat.scala 30:58] + node _T_288 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_289 = cat(UInt<2>("h01"), _T_288) @[Cat.scala 30:58] + node _T_291 = bits(io.in, 5, 5) @[RVC.scala 35:20] + node _T_292 = bits(io.in, 12, 10) @[RVC.scala 35:26] + node _T_293 = bits(io.in, 6, 6) @[RVC.scala 35:36] + node _T_295 = cat(_T_293, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_296 = cat(_T_291, _T_292) @[Cat.scala 30:58] + node _T_297 = cat(_T_296, _T_295) @[Cat.scala 30:58] + node _T_298 = bits(_T_297, 4, 0) @[RVC.scala 65:63] + node _T_300 = cat(UInt<3>("h02"), _T_298) @[Cat.scala 30:58] + node _T_301 = cat(_T_300, UInt<7>("h023")) @[Cat.scala 30:58] + node _T_302 = cat(_T_283, _T_286) @[Cat.scala 30:58] + node _T_303 = cat(_T_302, _T_289) @[Cat.scala 30:58] + node _T_304 = cat(_T_303, _T_301) @[Cat.scala 30:58] + node _T_306 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_307 = cat(UInt<2>("h01"), _T_306) @[Cat.scala 30:58] + node _T_309 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_310 = cat(UInt<2>("h01"), _T_309) @[Cat.scala 30:58] + node _T_312 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_313 = cat(UInt<2>("h01"), _T_312) @[Cat.scala 30:58] + node _T_314 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_321 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_321 is invalid @[RVC.scala 21:19] + _T_321.bits <= _T_304 @[RVC.scala 22:14] + _T_321.rd <= _T_307 @[RVC.scala 23:12] + _T_321.rs1 <= _T_310 @[RVC.scala 24:13] + _T_321.rs2 <= _T_313 @[RVC.scala 25:13] + _T_321.rs3 <= _T_314 @[RVC.scala 26:13] + node _T_327 = bits(io.in, 6, 5) @[RVC.scala 36:20] + node _T_328 = bits(io.in, 12, 10) @[RVC.scala 36:28] + node _T_330 = cat(_T_327, _T_328) @[Cat.scala 30:58] + node _T_331 = cat(_T_330, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_332 = shr(_T_331, 5) @[RVC.scala 64:29] + node _T_334 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_335 = cat(UInt<2>("h01"), _T_334) @[Cat.scala 30:58] + node _T_337 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_338 = cat(UInt<2>("h01"), _T_337) @[Cat.scala 30:58] + node _T_340 = bits(io.in, 6, 5) @[RVC.scala 36:20] + node _T_341 = bits(io.in, 12, 10) @[RVC.scala 36:28] + node _T_343 = cat(_T_340, _T_341) @[Cat.scala 30:58] + node _T_344 = cat(_T_343, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_345 = bits(_T_344, 4, 0) @[RVC.scala 64:63] + node _T_347 = cat(UInt<3>("h03"), _T_345) @[Cat.scala 30:58] + node _T_348 = cat(_T_347, UInt<7>("h023")) @[Cat.scala 30:58] + node _T_349 = cat(_T_332, _T_335) @[Cat.scala 30:58] + node _T_350 = cat(_T_349, _T_338) @[Cat.scala 30:58] + node _T_351 = cat(_T_350, _T_348) @[Cat.scala 30:58] + node _T_353 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_354 = cat(UInt<2>("h01"), _T_353) @[Cat.scala 30:58] + node _T_356 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_357 = cat(UInt<2>("h01"), _T_356) @[Cat.scala 30:58] + node _T_359 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_360 = cat(UInt<2>("h01"), _T_359) @[Cat.scala 30:58] + node _T_361 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_368 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_368 is invalid @[RVC.scala 21:19] + _T_368.bits <= _T_351 @[RVC.scala 22:14] + _T_368.rd <= _T_354 @[RVC.scala 23:12] + _T_368.rs1 <= _T_357 @[RVC.scala 24:13] + _T_368.rs2 <= _T_360 @[RVC.scala 25:13] + _T_368.rs3 <= _T_361 @[RVC.scala 26:13] + node _T_374 = bits(io.in, 12, 12) @[RVC.scala 43:30] + node _T_375 = bits(_T_374, 0, 0) @[Bitwise.scala 71:15] + node _T_378 = mux(_T_375, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12] + node _T_379 = bits(io.in, 6, 2) @[RVC.scala 43:38] + node _T_380 = cat(_T_378, _T_379) @[Cat.scala 30:58] + node _T_381 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_383 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_385 = cat(_T_383, UInt<7>("h013")) @[Cat.scala 30:58] + node _T_386 = cat(_T_380, _T_381) @[Cat.scala 30:58] + node _T_387 = cat(_T_386, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_388 = cat(_T_387, _T_385) @[Cat.scala 30:58] + node _T_389 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_390 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_392 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_393 = cat(UInt<2>("h01"), _T_392) @[Cat.scala 30:58] + node _T_394 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_401 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_401 is invalid @[RVC.scala 21:19] + _T_401.bits <= _T_388 @[RVC.scala 22:14] + _T_401.rd <= _T_389 @[RVC.scala 23:12] + _T_401.rs1 <= _T_390 @[RVC.scala 24:13] + _T_401.rs2 <= _T_393 @[RVC.scala 25:13] + _T_401.rs3 <= _T_394 @[RVC.scala 26:13] + node _T_407 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_409 = neq(_T_407, UInt<1>("h00")) @[RVC.scala 77:24] + node _T_412 = mux(_T_409, UInt<7>("h01b"), UInt<7>("h01f")) @[RVC.scala 77:20] + node _T_413 = bits(io.in, 12, 12) @[RVC.scala 43:30] + node _T_414 = bits(_T_413, 0, 0) @[Bitwise.scala 71:15] + node _T_417 = mux(_T_414, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12] + node _T_418 = bits(io.in, 6, 2) @[RVC.scala 43:38] + node _T_419 = cat(_T_417, _T_418) @[Cat.scala 30:58] + node _T_420 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_422 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_423 = cat(_T_422, _T_412) @[Cat.scala 30:58] + node _T_424 = cat(_T_419, _T_420) @[Cat.scala 30:58] + node _T_425 = cat(_T_424, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_426 = cat(_T_425, _T_423) @[Cat.scala 30:58] + node _T_427 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_428 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_430 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_431 = cat(UInt<2>("h01"), _T_430) @[Cat.scala 30:58] + node _T_432 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_439 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_439 is invalid @[RVC.scala 21:19] + _T_439.bits <= _T_426 @[RVC.scala 22:14] + _T_439.rd <= _T_427 @[RVC.scala 23:12] + _T_439.rs1 <= _T_428 @[RVC.scala 24:13] + _T_439.rs2 <= _T_431 @[RVC.scala 25:13] + _T_439.rs3 <= _T_432 @[RVC.scala 26:13] + node _T_445 = bits(io.in, 12, 12) @[RVC.scala 43:30] + node _T_446 = bits(_T_445, 0, 0) @[Bitwise.scala 71:15] + node _T_449 = mux(_T_446, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12] + node _T_450 = bits(io.in, 6, 2) @[RVC.scala 43:38] + node _T_451 = cat(_T_449, _T_450) @[Cat.scala 30:58] + node _T_454 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_456 = cat(_T_454, UInt<7>("h013")) @[Cat.scala 30:58] + node _T_457 = cat(_T_451, UInt<5>("h00")) @[Cat.scala 30:58] + node _T_458 = cat(_T_457, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_459 = cat(_T_458, _T_456) @[Cat.scala 30:58] + node _T_460 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_463 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_464 = cat(UInt<2>("h01"), _T_463) @[Cat.scala 30:58] + node _T_465 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_472 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_472 is invalid @[RVC.scala 21:19] + _T_472.bits <= _T_459 @[RVC.scala 22:14] + _T_472.rd <= _T_460 @[RVC.scala 23:12] + _T_472.rs1 <= UInt<5>("h00") @[RVC.scala 24:13] + _T_472.rs2 <= _T_464 @[RVC.scala 25:13] + _T_472.rs3 <= _T_465 @[RVC.scala 26:13] + node _T_478 = bits(io.in, 12, 12) @[RVC.scala 43:30] + node _T_479 = bits(_T_478, 0, 0) @[Bitwise.scala 71:15] + node _T_482 = mux(_T_479, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12] + node _T_483 = bits(io.in, 6, 2) @[RVC.scala 43:38] + node _T_484 = cat(_T_482, _T_483) @[Cat.scala 30:58] + node _T_486 = neq(_T_484, UInt<1>("h00")) @[RVC.scala 90:29] + node _T_489 = mux(_T_486, UInt<7>("h037"), UInt<7>("h03f")) @[RVC.scala 90:20] + node _T_490 = bits(io.in, 12, 12) @[RVC.scala 41:30] + node _T_491 = bits(_T_490, 0, 0) @[Bitwise.scala 71:15] + node _T_494 = mux(_T_491, UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 71:12] + node _T_495 = bits(io.in, 6, 2) @[RVC.scala 41:38] + node _T_497 = cat(_T_494, _T_495) @[Cat.scala 30:58] + node _T_498 = cat(_T_497, UInt<12>("h00")) @[Cat.scala 30:58] + node _T_499 = bits(_T_498, 31, 12) @[RVC.scala 91:31] + node _T_500 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_501 = cat(_T_499, _T_500) @[Cat.scala 30:58] + node _T_502 = cat(_T_501, _T_489) @[Cat.scala 30:58] + node _T_503 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_504 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_506 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_507 = cat(UInt<2>("h01"), _T_506) @[Cat.scala 30:58] + node _T_508 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_515 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_515 is invalid @[RVC.scala 21:19] + _T_515.bits <= _T_502 @[RVC.scala 22:14] + _T_515.rd <= _T_503 @[RVC.scala 23:12] + _T_515.rs1 <= _T_504 @[RVC.scala 24:13] + _T_515.rs2 <= _T_507 @[RVC.scala 25:13] + _T_515.rs3 <= _T_508 @[RVC.scala 26:13] + node _T_521 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_523 = eq(_T_521, UInt<5>("h00")) @[RVC.scala 92:14] + node _T_524 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_526 = eq(_T_524, UInt<5>("h02")) @[RVC.scala 92:27] + node _T_527 = or(_T_523, _T_526) @[RVC.scala 92:21] + node _T_528 = bits(io.in, 12, 12) @[RVC.scala 43:30] + node _T_529 = bits(_T_528, 0, 0) @[Bitwise.scala 71:15] + node _T_532 = mux(_T_529, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12] + node _T_533 = bits(io.in, 6, 2) @[RVC.scala 43:38] + node _T_534 = cat(_T_532, _T_533) @[Cat.scala 30:58] + node _T_536 = neq(_T_534, UInt<1>("h00")) @[RVC.scala 86:29] + node _T_539 = mux(_T_536, UInt<7>("h013"), UInt<7>("h01f")) @[RVC.scala 86:20] + node _T_540 = bits(io.in, 12, 12) @[RVC.scala 42:34] + node _T_541 = bits(_T_540, 0, 0) @[Bitwise.scala 71:15] + node _T_544 = mux(_T_541, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 71:12] + node _T_545 = bits(io.in, 4, 3) @[RVC.scala 42:42] + node _T_546 = bits(io.in, 5, 5) @[RVC.scala 42:50] + node _T_547 = bits(io.in, 2, 2) @[RVC.scala 42:56] + node _T_548 = bits(io.in, 6, 6) @[RVC.scala 42:62] + node _T_550 = cat(_T_547, _T_548) @[Cat.scala 30:58] + node _T_551 = cat(_T_550, UInt<4>("h00")) @[Cat.scala 30:58] + node _T_552 = cat(_T_544, _T_545) @[Cat.scala 30:58] + node _T_553 = cat(_T_552, _T_546) @[Cat.scala 30:58] + node _T_554 = cat(_T_553, _T_551) @[Cat.scala 30:58] + node _T_555 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_557 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_558 = cat(_T_557, _T_539) @[Cat.scala 30:58] + node _T_559 = cat(_T_554, _T_555) @[Cat.scala 30:58] + node _T_560 = cat(_T_559, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_561 = cat(_T_560, _T_558) @[Cat.scala 30:58] + node _T_562 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_563 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_565 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_566 = cat(UInt<2>("h01"), _T_565) @[Cat.scala 30:58] + node _T_567 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_574 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_574 is invalid @[RVC.scala 21:19] + _T_574.bits <= _T_561 @[RVC.scala 22:14] + _T_574.rd <= _T_562 @[RVC.scala 23:12] + _T_574.rs1 <= _T_563 @[RVC.scala 24:13] + _T_574.rs2 <= _T_566 @[RVC.scala 25:13] + _T_574.rs3 <= _T_567 @[RVC.scala 26:13] + node _T_580 = mux(_T_527, _T_574, _T_515) @[RVC.scala 92:10] + node _T_586 = bits(io.in, 12, 12) @[RVC.scala 46:20] + node _T_587 = bits(io.in, 6, 2) @[RVC.scala 46:27] + node _T_588 = cat(_T_586, _T_587) @[Cat.scala 30:58] + node _T_590 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_591 = cat(UInt<2>("h01"), _T_590) @[Cat.scala 30:58] + node _T_594 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_595 = cat(UInt<2>("h01"), _T_594) @[Cat.scala 30:58] + node _T_597 = cat(_T_595, UInt<7>("h013")) @[Cat.scala 30:58] + node _T_598 = cat(_T_588, _T_591) @[Cat.scala 30:58] + node _T_599 = cat(_T_598, UInt<3>("h05")) @[Cat.scala 30:58] + node _T_600 = cat(_T_599, _T_597) @[Cat.scala 30:58] + node _T_601 = bits(io.in, 12, 12) @[RVC.scala 46:20] + node _T_602 = bits(io.in, 6, 2) @[RVC.scala 46:27] + node _T_603 = cat(_T_601, _T_602) @[Cat.scala 30:58] + node _T_605 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_606 = cat(UInt<2>("h01"), _T_605) @[Cat.scala 30:58] + node _T_609 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_610 = cat(UInt<2>("h01"), _T_609) @[Cat.scala 30:58] + node _T_612 = cat(_T_610, UInt<7>("h013")) @[Cat.scala 30:58] + node _T_613 = cat(_T_603, _T_606) @[Cat.scala 30:58] + node _T_614 = cat(_T_613, UInt<3>("h05")) @[Cat.scala 30:58] + node _T_615 = cat(_T_614, _T_612) @[Cat.scala 30:58] + node _T_617 = or(_T_615, UInt<31>("h040000000")) @[RVC.scala 99:23] + node _T_618 = bits(io.in, 12, 12) @[RVC.scala 43:30] + node _T_619 = bits(_T_618, 0, 0) @[Bitwise.scala 71:15] + node _T_622 = mux(_T_619, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 71:12] + node _T_623 = bits(io.in, 6, 2) @[RVC.scala 43:38] + node _T_624 = cat(_T_622, _T_623) @[Cat.scala 30:58] + node _T_626 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_627 = cat(UInt<2>("h01"), _T_626) @[Cat.scala 30:58] + node _T_630 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_631 = cat(UInt<2>("h01"), _T_630) @[Cat.scala 30:58] + node _T_633 = cat(_T_631, UInt<7>("h013")) @[Cat.scala 30:58] + node _T_634 = cat(_T_624, _T_627) @[Cat.scala 30:58] + node _T_635 = cat(_T_634, UInt<3>("h07")) @[Cat.scala 30:58] + node _T_636 = cat(_T_635, _T_633) @[Cat.scala 30:58] + node _T_645 = bits(io.in, 12, 12) @[RVC.scala 102:70] + node _T_646 = bits(io.in, 6, 5) @[RVC.scala 102:77] + node _T_647 = cat(_T_645, _T_646) @[Cat.scala 30:58] + node _T_649 = and(_T_647, UInt<2>("h03")) @[Package.scala 18:26] + node _T_651 = geq(_T_647, UInt<3>("h04")) @[Package.scala 19:17] + node _T_653 = and(_T_649, UInt<1>("h01")) @[Package.scala 18:26] + node _T_655 = geq(_T_649, UInt<2>("h02")) @[Package.scala 19:17] + node _T_657 = and(_T_653, UInt<1>("h00")) @[Package.scala 18:26] + node _T_659 = geq(_T_653, UInt<1>("h01")) @[Package.scala 19:17] + node _T_660 = mux(_T_659, UInt<2>("h03"), UInt<2>("h02")) @[Package.scala 19:12] + node _T_662 = and(_T_653, UInt<1>("h00")) @[Package.scala 18:26] + node _T_664 = geq(_T_653, UInt<1>("h01")) @[Package.scala 19:17] + node _T_665 = mux(_T_664, UInt<1>("h00"), UInt<1>("h00")) @[Package.scala 19:12] + node _T_666 = mux(_T_655, _T_660, _T_665) @[Package.scala 19:12] + node _T_668 = and(_T_649, UInt<1>("h01")) @[Package.scala 18:26] + node _T_670 = geq(_T_649, UInt<2>("h02")) @[Package.scala 19:17] + node _T_672 = and(_T_668, UInt<1>("h00")) @[Package.scala 18:26] + node _T_674 = geq(_T_668, UInt<1>("h01")) @[Package.scala 19:17] + node _T_675 = mux(_T_674, UInt<3>("h07"), UInt<3>("h06")) @[Package.scala 19:12] + node _T_677 = and(_T_668, UInt<1>("h00")) @[Package.scala 18:26] + node _T_679 = geq(_T_668, UInt<1>("h01")) @[Package.scala 19:17] + node _T_680 = mux(_T_679, UInt<3>("h04"), UInt<1>("h00")) @[Package.scala 19:12] + node _T_681 = mux(_T_670, _T_675, _T_680) @[Package.scala 19:12] + node _T_682 = mux(_T_651, _T_666, _T_681) @[Package.scala 19:12] + node _T_683 = bits(io.in, 6, 5) @[RVC.scala 103:24] + node _T_685 = eq(_T_683, UInt<1>("h00")) @[RVC.scala 103:30] + node _T_688 = mux(_T_685, UInt<31>("h040000000"), UInt<1>("h00")) @[RVC.scala 103:22] + node _T_689 = bits(io.in, 12, 12) @[RVC.scala 104:24] + node _T_692 = mux(_T_689, UInt<7>("h03b"), UInt<7>("h033")) @[RVC.scala 104:22] + node _T_694 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_695 = cat(UInt<2>("h01"), _T_694) @[Cat.scala 30:58] + node _T_697 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_698 = cat(UInt<2>("h01"), _T_697) @[Cat.scala 30:58] + node _T_700 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_701 = cat(UInt<2>("h01"), _T_700) @[Cat.scala 30:58] + node _T_702 = cat(_T_701, _T_692) @[Cat.scala 30:58] + node _T_703 = cat(_T_695, _T_698) @[Cat.scala 30:58] + node _T_704 = cat(_T_703, _T_682) @[Cat.scala 30:58] + node _T_705 = cat(_T_704, _T_702) @[Cat.scala 30:58] + node _T_706 = or(_T_705, _T_688) @[RVC.scala 105:43] + node _T_707 = bits(io.in, 11, 10) @[RVC.scala 107:42] + node _T_709 = and(_T_707, UInt<1>("h01")) @[Package.scala 18:26] + node _T_711 = geq(_T_707, UInt<2>("h02")) @[Package.scala 19:17] + node _T_713 = and(_T_709, UInt<1>("h00")) @[Package.scala 18:26] + node _T_715 = geq(_T_709, UInt<1>("h01")) @[Package.scala 19:17] + node _T_716 = mux(_T_715, _T_706, _T_636) @[Package.scala 19:12] + node _T_718 = and(_T_709, UInt<1>("h00")) @[Package.scala 18:26] + node _T_720 = geq(_T_709, UInt<1>("h01")) @[Package.scala 19:17] + node _T_721 = mux(_T_720, _T_617, _T_600) @[Package.scala 19:12] + node _T_722 = mux(_T_711, _T_716, _T_721) @[Package.scala 19:12] + node _T_724 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_725 = cat(UInt<2>("h01"), _T_724) @[Cat.scala 30:58] + node _T_727 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_728 = cat(UInt<2>("h01"), _T_727) @[Cat.scala 30:58] + node _T_730 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_731 = cat(UInt<2>("h01"), _T_730) @[Cat.scala 30:58] + node _T_732 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_739 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_739 is invalid @[RVC.scala 21:19] + _T_739.bits <= _T_722 @[RVC.scala 22:14] + _T_739.rd <= _T_725 @[RVC.scala 23:12] + _T_739.rs1 <= _T_728 @[RVC.scala 24:13] + _T_739.rs2 <= _T_731 @[RVC.scala 25:13] + _T_739.rs3 <= _T_732 @[RVC.scala 26:13] + node _T_745 = bits(io.in, 12, 12) @[RVC.scala 44:28] + node _T_746 = bits(_T_745, 0, 0) @[Bitwise.scala 71:15] + node _T_749 = mux(_T_746, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 71:12] + node _T_750 = bits(io.in, 8, 8) @[RVC.scala 44:36] + node _T_751 = bits(io.in, 10, 9) @[RVC.scala 44:42] + node _T_752 = bits(io.in, 6, 6) @[RVC.scala 44:51] + node _T_753 = bits(io.in, 7, 7) @[RVC.scala 44:57] + node _T_754 = bits(io.in, 2, 2) @[RVC.scala 44:63] + node _T_755 = bits(io.in, 11, 11) @[RVC.scala 44:69] + node _T_756 = bits(io.in, 5, 3) @[RVC.scala 44:76] + node _T_758 = cat(_T_756, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_759 = cat(_T_754, _T_755) @[Cat.scala 30:58] + node _T_760 = cat(_T_759, _T_758) @[Cat.scala 30:58] + node _T_761 = cat(_T_752, _T_753) @[Cat.scala 30:58] + node _T_762 = cat(_T_749, _T_750) @[Cat.scala 30:58] + node _T_763 = cat(_T_762, _T_751) @[Cat.scala 30:58] + node _T_764 = cat(_T_763, _T_761) @[Cat.scala 30:58] + node _T_765 = cat(_T_764, _T_760) @[Cat.scala 30:58] + node _T_766 = bits(_T_765, 20, 20) @[RVC.scala 94:26] + node _T_767 = bits(io.in, 12, 12) @[RVC.scala 44:28] + node _T_768 = bits(_T_767, 0, 0) @[Bitwise.scala 71:15] + node _T_771 = mux(_T_768, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 71:12] + node _T_772 = bits(io.in, 8, 8) @[RVC.scala 44:36] + node _T_773 = bits(io.in, 10, 9) @[RVC.scala 44:42] + node _T_774 = bits(io.in, 6, 6) @[RVC.scala 44:51] + node _T_775 = bits(io.in, 7, 7) @[RVC.scala 44:57] + node _T_776 = bits(io.in, 2, 2) @[RVC.scala 44:63] + node _T_777 = bits(io.in, 11, 11) @[RVC.scala 44:69] + node _T_778 = bits(io.in, 5, 3) @[RVC.scala 44:76] + node _T_780 = cat(_T_778, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_781 = cat(_T_776, _T_777) @[Cat.scala 30:58] + node _T_782 = cat(_T_781, _T_780) @[Cat.scala 30:58] + node _T_783 = cat(_T_774, _T_775) @[Cat.scala 30:58] + node _T_784 = cat(_T_771, _T_772) @[Cat.scala 30:58] + node _T_785 = cat(_T_784, _T_773) @[Cat.scala 30:58] + node _T_786 = cat(_T_785, _T_783) @[Cat.scala 30:58] + node _T_787 = cat(_T_786, _T_782) @[Cat.scala 30:58] + node _T_788 = bits(_T_787, 10, 1) @[RVC.scala 94:36] + node _T_789 = bits(io.in, 12, 12) @[RVC.scala 44:28] + node _T_790 = bits(_T_789, 0, 0) @[Bitwise.scala 71:15] + node _T_793 = mux(_T_790, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 71:12] + node _T_794 = bits(io.in, 8, 8) @[RVC.scala 44:36] + node _T_795 = bits(io.in, 10, 9) @[RVC.scala 44:42] + node _T_796 = bits(io.in, 6, 6) @[RVC.scala 44:51] + node _T_797 = bits(io.in, 7, 7) @[RVC.scala 44:57] + node _T_798 = bits(io.in, 2, 2) @[RVC.scala 44:63] + node _T_799 = bits(io.in, 11, 11) @[RVC.scala 44:69] + node _T_800 = bits(io.in, 5, 3) @[RVC.scala 44:76] + node _T_802 = cat(_T_800, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_803 = cat(_T_798, _T_799) @[Cat.scala 30:58] + node _T_804 = cat(_T_803, _T_802) @[Cat.scala 30:58] + node _T_805 = cat(_T_796, _T_797) @[Cat.scala 30:58] + node _T_806 = cat(_T_793, _T_794) @[Cat.scala 30:58] + node _T_807 = cat(_T_806, _T_795) @[Cat.scala 30:58] + node _T_808 = cat(_T_807, _T_805) @[Cat.scala 30:58] + node _T_809 = cat(_T_808, _T_804) @[Cat.scala 30:58] + node _T_810 = bits(_T_809, 11, 11) @[RVC.scala 94:48] + node _T_811 = bits(io.in, 12, 12) @[RVC.scala 44:28] + node _T_812 = bits(_T_811, 0, 0) @[Bitwise.scala 71:15] + node _T_815 = mux(_T_812, UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 71:12] + node _T_816 = bits(io.in, 8, 8) @[RVC.scala 44:36] + node _T_817 = bits(io.in, 10, 9) @[RVC.scala 44:42] + node _T_818 = bits(io.in, 6, 6) @[RVC.scala 44:51] + node _T_819 = bits(io.in, 7, 7) @[RVC.scala 44:57] + node _T_820 = bits(io.in, 2, 2) @[RVC.scala 44:63] + node _T_821 = bits(io.in, 11, 11) @[RVC.scala 44:69] + node _T_822 = bits(io.in, 5, 3) @[RVC.scala 44:76] + node _T_824 = cat(_T_822, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_825 = cat(_T_820, _T_821) @[Cat.scala 30:58] + node _T_826 = cat(_T_825, _T_824) @[Cat.scala 30:58] + node _T_827 = cat(_T_818, _T_819) @[Cat.scala 30:58] + node _T_828 = cat(_T_815, _T_816) @[Cat.scala 30:58] + node _T_829 = cat(_T_828, _T_817) @[Cat.scala 30:58] + node _T_830 = cat(_T_829, _T_827) @[Cat.scala 30:58] + node _T_831 = cat(_T_830, _T_826) @[Cat.scala 30:58] + node _T_832 = bits(_T_831, 19, 12) @[RVC.scala 94:58] + node _T_835 = cat(_T_832, UInt<5>("h00")) @[Cat.scala 30:58] + node _T_836 = cat(_T_835, UInt<7>("h06f")) @[Cat.scala 30:58] + node _T_837 = cat(_T_766, _T_788) @[Cat.scala 30:58] + node _T_838 = cat(_T_837, _T_810) @[Cat.scala 30:58] + node _T_839 = cat(_T_838, _T_836) @[Cat.scala 30:58] + node _T_842 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_843 = cat(UInt<2>("h01"), _T_842) @[Cat.scala 30:58] + node _T_845 = bits(io.in, 4, 2) @[RVC.scala 31:30] + node _T_846 = cat(UInt<2>("h01"), _T_845) @[Cat.scala 30:58] + node _T_847 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_854 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_854 is invalid @[RVC.scala 21:19] + _T_854.bits <= _T_839 @[RVC.scala 22:14] + _T_854.rd <= UInt<5>("h00") @[RVC.scala 23:12] + _T_854.rs1 <= _T_843 @[RVC.scala 24:13] + _T_854.rs2 <= _T_846 @[RVC.scala 25:13] + _T_854.rs3 <= _T_847 @[RVC.scala 26:13] + node _T_860 = bits(io.in, 12, 12) @[RVC.scala 45:27] + node _T_861 = bits(_T_860, 0, 0) @[Bitwise.scala 71:15] + node _T_864 = mux(_T_861, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12] + node _T_865 = bits(io.in, 6, 5) @[RVC.scala 45:35] + node _T_866 = bits(io.in, 2, 2) @[RVC.scala 45:43] + node _T_867 = bits(io.in, 11, 10) @[RVC.scala 45:49] + node _T_868 = bits(io.in, 4, 3) @[RVC.scala 45:59] + node _T_870 = cat(_T_867, _T_868) @[Cat.scala 30:58] + node _T_871 = cat(_T_870, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_872 = cat(_T_864, _T_865) @[Cat.scala 30:58] + node _T_873 = cat(_T_872, _T_866) @[Cat.scala 30:58] + node _T_874 = cat(_T_873, _T_871) @[Cat.scala 30:58] + node _T_875 = bits(_T_874, 12, 12) @[RVC.scala 95:29] + node _T_876 = bits(io.in, 12, 12) @[RVC.scala 45:27] + node _T_877 = bits(_T_876, 0, 0) @[Bitwise.scala 71:15] + node _T_880 = mux(_T_877, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12] + node _T_881 = bits(io.in, 6, 5) @[RVC.scala 45:35] + node _T_882 = bits(io.in, 2, 2) @[RVC.scala 45:43] + node _T_883 = bits(io.in, 11, 10) @[RVC.scala 45:49] + node _T_884 = bits(io.in, 4, 3) @[RVC.scala 45:59] + node _T_886 = cat(_T_883, _T_884) @[Cat.scala 30:58] + node _T_887 = cat(_T_886, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_888 = cat(_T_880, _T_881) @[Cat.scala 30:58] + node _T_889 = cat(_T_888, _T_882) @[Cat.scala 30:58] + node _T_890 = cat(_T_889, _T_887) @[Cat.scala 30:58] + node _T_891 = bits(_T_890, 10, 5) @[RVC.scala 95:39] + node _T_894 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_895 = cat(UInt<2>("h01"), _T_894) @[Cat.scala 30:58] + node _T_897 = bits(io.in, 12, 12) @[RVC.scala 45:27] + node _T_898 = bits(_T_897, 0, 0) @[Bitwise.scala 71:15] + node _T_901 = mux(_T_898, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12] + node _T_902 = bits(io.in, 6, 5) @[RVC.scala 45:35] + node _T_903 = bits(io.in, 2, 2) @[RVC.scala 45:43] + node _T_904 = bits(io.in, 11, 10) @[RVC.scala 45:49] + node _T_905 = bits(io.in, 4, 3) @[RVC.scala 45:59] + node _T_907 = cat(_T_904, _T_905) @[Cat.scala 30:58] + node _T_908 = cat(_T_907, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_909 = cat(_T_901, _T_902) @[Cat.scala 30:58] + node _T_910 = cat(_T_909, _T_903) @[Cat.scala 30:58] + node _T_911 = cat(_T_910, _T_908) @[Cat.scala 30:58] + node _T_912 = bits(_T_911, 4, 1) @[RVC.scala 95:72] + node _T_913 = bits(io.in, 12, 12) @[RVC.scala 45:27] + node _T_914 = bits(_T_913, 0, 0) @[Bitwise.scala 71:15] + node _T_917 = mux(_T_914, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12] + node _T_918 = bits(io.in, 6, 5) @[RVC.scala 45:35] + node _T_919 = bits(io.in, 2, 2) @[RVC.scala 45:43] + node _T_920 = bits(io.in, 11, 10) @[RVC.scala 45:49] + node _T_921 = bits(io.in, 4, 3) @[RVC.scala 45:59] + node _T_923 = cat(_T_920, _T_921) @[Cat.scala 30:58] + node _T_924 = cat(_T_923, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_925 = cat(_T_917, _T_918) @[Cat.scala 30:58] + node _T_926 = cat(_T_925, _T_919) @[Cat.scala 30:58] + node _T_927 = cat(_T_926, _T_924) @[Cat.scala 30:58] + node _T_928 = bits(_T_927, 11, 11) @[RVC.scala 95:83] + node _T_930 = cat(_T_928, UInt<7>("h063")) @[Cat.scala 30:58] + node _T_931 = cat(UInt<3>("h00"), _T_912) @[Cat.scala 30:58] + node _T_932 = cat(_T_931, _T_930) @[Cat.scala 30:58] + node _T_933 = cat(UInt<5>("h00"), _T_895) @[Cat.scala 30:58] + node _T_934 = cat(_T_875, _T_891) @[Cat.scala 30:58] + node _T_935 = cat(_T_934, _T_933) @[Cat.scala 30:58] + node _T_936 = cat(_T_935, _T_932) @[Cat.scala 30:58] + node _T_938 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_939 = cat(UInt<2>("h01"), _T_938) @[Cat.scala 30:58] + node _T_941 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_942 = cat(UInt<2>("h01"), _T_941) @[Cat.scala 30:58] + node _T_944 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_951 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_951 is invalid @[RVC.scala 21:19] + _T_951.bits <= _T_936 @[RVC.scala 22:14] + _T_951.rd <= _T_939 @[RVC.scala 23:12] + _T_951.rs1 <= _T_942 @[RVC.scala 24:13] + _T_951.rs2 <= UInt<5>("h00") @[RVC.scala 25:13] + _T_951.rs3 <= _T_944 @[RVC.scala 26:13] + node _T_957 = bits(io.in, 12, 12) @[RVC.scala 45:27] + node _T_958 = bits(_T_957, 0, 0) @[Bitwise.scala 71:15] + node _T_961 = mux(_T_958, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12] + node _T_962 = bits(io.in, 6, 5) @[RVC.scala 45:35] + node _T_963 = bits(io.in, 2, 2) @[RVC.scala 45:43] + node _T_964 = bits(io.in, 11, 10) @[RVC.scala 45:49] + node _T_965 = bits(io.in, 4, 3) @[RVC.scala 45:59] + node _T_967 = cat(_T_964, _T_965) @[Cat.scala 30:58] + node _T_968 = cat(_T_967, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_969 = cat(_T_961, _T_962) @[Cat.scala 30:58] + node _T_970 = cat(_T_969, _T_963) @[Cat.scala 30:58] + node _T_971 = cat(_T_970, _T_968) @[Cat.scala 30:58] + node _T_972 = bits(_T_971, 12, 12) @[RVC.scala 96:29] + node _T_973 = bits(io.in, 12, 12) @[RVC.scala 45:27] + node _T_974 = bits(_T_973, 0, 0) @[Bitwise.scala 71:15] + node _T_977 = mux(_T_974, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12] + node _T_978 = bits(io.in, 6, 5) @[RVC.scala 45:35] + node _T_979 = bits(io.in, 2, 2) @[RVC.scala 45:43] + node _T_980 = bits(io.in, 11, 10) @[RVC.scala 45:49] + node _T_981 = bits(io.in, 4, 3) @[RVC.scala 45:59] + node _T_983 = cat(_T_980, _T_981) @[Cat.scala 30:58] + node _T_984 = cat(_T_983, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_985 = cat(_T_977, _T_978) @[Cat.scala 30:58] + node _T_986 = cat(_T_985, _T_979) @[Cat.scala 30:58] + node _T_987 = cat(_T_986, _T_984) @[Cat.scala 30:58] + node _T_988 = bits(_T_987, 10, 5) @[RVC.scala 96:39] + node _T_991 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_992 = cat(UInt<2>("h01"), _T_991) @[Cat.scala 30:58] + node _T_994 = bits(io.in, 12, 12) @[RVC.scala 45:27] + node _T_995 = bits(_T_994, 0, 0) @[Bitwise.scala 71:15] + node _T_998 = mux(_T_995, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12] + node _T_999 = bits(io.in, 6, 5) @[RVC.scala 45:35] + node _T_1000 = bits(io.in, 2, 2) @[RVC.scala 45:43] + node _T_1001 = bits(io.in, 11, 10) @[RVC.scala 45:49] + node _T_1002 = bits(io.in, 4, 3) @[RVC.scala 45:59] + node _T_1004 = cat(_T_1001, _T_1002) @[Cat.scala 30:58] + node _T_1005 = cat(_T_1004, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_1006 = cat(_T_998, _T_999) @[Cat.scala 30:58] + node _T_1007 = cat(_T_1006, _T_1000) @[Cat.scala 30:58] + node _T_1008 = cat(_T_1007, _T_1005) @[Cat.scala 30:58] + node _T_1009 = bits(_T_1008, 4, 1) @[RVC.scala 96:72] + node _T_1010 = bits(io.in, 12, 12) @[RVC.scala 45:27] + node _T_1011 = bits(_T_1010, 0, 0) @[Bitwise.scala 71:15] + node _T_1014 = mux(_T_1011, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 71:12] + node _T_1015 = bits(io.in, 6, 5) @[RVC.scala 45:35] + node _T_1016 = bits(io.in, 2, 2) @[RVC.scala 45:43] + node _T_1017 = bits(io.in, 11, 10) @[RVC.scala 45:49] + node _T_1018 = bits(io.in, 4, 3) @[RVC.scala 45:59] + node _T_1020 = cat(_T_1017, _T_1018) @[Cat.scala 30:58] + node _T_1021 = cat(_T_1020, UInt<1>("h00")) @[Cat.scala 30:58] + node _T_1022 = cat(_T_1014, _T_1015) @[Cat.scala 30:58] + node _T_1023 = cat(_T_1022, _T_1016) @[Cat.scala 30:58] + node _T_1024 = cat(_T_1023, _T_1021) @[Cat.scala 30:58] + node _T_1025 = bits(_T_1024, 11, 11) @[RVC.scala 96:83] + node _T_1027 = cat(_T_1025, UInt<7>("h063")) @[Cat.scala 30:58] + node _T_1028 = cat(UInt<3>("h01"), _T_1009) @[Cat.scala 30:58] + node _T_1029 = cat(_T_1028, _T_1027) @[Cat.scala 30:58] + node _T_1030 = cat(UInt<5>("h00"), _T_992) @[Cat.scala 30:58] + node _T_1031 = cat(_T_972, _T_988) @[Cat.scala 30:58] + node _T_1032 = cat(_T_1031, _T_1030) @[Cat.scala 30:58] + node _T_1033 = cat(_T_1032, _T_1029) @[Cat.scala 30:58] + node _T_1036 = bits(io.in, 9, 7) @[RVC.scala 30:30] + node _T_1037 = cat(UInt<2>("h01"), _T_1036) @[Cat.scala 30:58] + node _T_1039 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1046 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1046 is invalid @[RVC.scala 21:19] + _T_1046.bits <= _T_1033 @[RVC.scala 22:14] + _T_1046.rd <= UInt<5>("h00") @[RVC.scala 23:12] + _T_1046.rs1 <= _T_1037 @[RVC.scala 24:13] + _T_1046.rs2 <= UInt<5>("h00") @[RVC.scala 25:13] + _T_1046.rs3 <= _T_1039 @[RVC.scala 26:13] + node _T_1052 = bits(io.in, 12, 12) @[RVC.scala 46:20] + node _T_1053 = bits(io.in, 6, 2) @[RVC.scala 46:27] + node _T_1054 = cat(_T_1052, _T_1053) @[Cat.scala 30:58] + node _T_1055 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1057 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1059 = cat(_T_1057, UInt<7>("h013")) @[Cat.scala 30:58] + node _T_1060 = cat(_T_1054, _T_1055) @[Cat.scala 30:58] + node _T_1061 = cat(_T_1060, UInt<3>("h01")) @[Cat.scala 30:58] + node _T_1062 = cat(_T_1061, _T_1059) @[Cat.scala 30:58] + node _T_1063 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1064 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1065 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1066 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1073 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1073 is invalid @[RVC.scala 21:19] + _T_1073.bits <= _T_1062 @[RVC.scala 22:14] + _T_1073.rd <= _T_1063 @[RVC.scala 23:12] + _T_1073.rs1 <= _T_1064 @[RVC.scala 24:13] + _T_1073.rs2 <= _T_1065 @[RVC.scala 25:13] + _T_1073.rs3 <= _T_1066 @[RVC.scala 26:13] + node _T_1079 = bits(io.in, 4, 2) @[RVC.scala 38:22] + node _T_1080 = bits(io.in, 12, 12) @[RVC.scala 38:30] + node _T_1081 = bits(io.in, 6, 5) @[RVC.scala 38:37] + node _T_1083 = cat(_T_1081, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1084 = cat(_T_1079, _T_1080) @[Cat.scala 30:58] + node _T_1085 = cat(_T_1084, _T_1083) @[Cat.scala 30:58] + node _T_1088 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1090 = cat(_T_1088, UInt<7>("h07")) @[Cat.scala 30:58] + node _T_1091 = cat(_T_1085, UInt<5>("h02")) @[Cat.scala 30:58] + node _T_1092 = cat(_T_1091, UInt<3>("h03")) @[Cat.scala 30:58] + node _T_1093 = cat(_T_1092, _T_1090) @[Cat.scala 30:58] + node _T_1094 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1096 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1097 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1104 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1104 is invalid @[RVC.scala 21:19] + _T_1104.bits <= _T_1093 @[RVC.scala 22:14] + _T_1104.rd <= _T_1094 @[RVC.scala 23:12] + _T_1104.rs1 <= UInt<5>("h02") @[RVC.scala 24:13] + _T_1104.rs2 <= _T_1096 @[RVC.scala 25:13] + _T_1104.rs3 <= _T_1097 @[RVC.scala 26:13] + node _T_1110 = bits(io.in, 3, 2) @[RVC.scala 37:22] + node _T_1111 = bits(io.in, 12, 12) @[RVC.scala 37:30] + node _T_1112 = bits(io.in, 6, 4) @[RVC.scala 37:37] + node _T_1114 = cat(_T_1112, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_1115 = cat(_T_1110, _T_1111) @[Cat.scala 30:58] + node _T_1116 = cat(_T_1115, _T_1114) @[Cat.scala 30:58] + node _T_1119 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1121 = cat(_T_1119, UInt<7>("h03")) @[Cat.scala 30:58] + node _T_1122 = cat(_T_1116, UInt<5>("h02")) @[Cat.scala 30:58] + node _T_1123 = cat(_T_1122, UInt<3>("h02")) @[Cat.scala 30:58] + node _T_1124 = cat(_T_1123, _T_1121) @[Cat.scala 30:58] + node _T_1125 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1127 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1128 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1135 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1135 is invalid @[RVC.scala 21:19] + _T_1135.bits <= _T_1124 @[RVC.scala 22:14] + _T_1135.rd <= _T_1125 @[RVC.scala 23:12] + _T_1135.rs1 <= UInt<5>("h02") @[RVC.scala 24:13] + _T_1135.rs2 <= _T_1127 @[RVC.scala 25:13] + _T_1135.rs3 <= _T_1128 @[RVC.scala 26:13] + node _T_1141 = bits(io.in, 4, 2) @[RVC.scala 38:22] + node _T_1142 = bits(io.in, 12, 12) @[RVC.scala 38:30] + node _T_1143 = bits(io.in, 6, 5) @[RVC.scala 38:37] + node _T_1145 = cat(_T_1143, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1146 = cat(_T_1141, _T_1142) @[Cat.scala 30:58] + node _T_1147 = cat(_T_1146, _T_1145) @[Cat.scala 30:58] + node _T_1150 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1152 = cat(_T_1150, UInt<7>("h03")) @[Cat.scala 30:58] + node _T_1153 = cat(_T_1147, UInt<5>("h02")) @[Cat.scala 30:58] + node _T_1154 = cat(_T_1153, UInt<3>("h03")) @[Cat.scala 30:58] + node _T_1155 = cat(_T_1154, _T_1152) @[Cat.scala 30:58] + node _T_1156 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1158 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1159 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1166 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1166 is invalid @[RVC.scala 21:19] + _T_1166.bits <= _T_1155 @[RVC.scala 22:14] + _T_1166.rd <= _T_1156 @[RVC.scala 23:12] + _T_1166.rs1 <= UInt<5>("h02") @[RVC.scala 24:13] + _T_1166.rs2 <= _T_1158 @[RVC.scala 25:13] + _T_1166.rs3 <= _T_1159 @[RVC.scala 26:13] + node _T_1172 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1175 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1177 = cat(_T_1175, UInt<7>("h033")) @[Cat.scala 30:58] + node _T_1178 = cat(_T_1172, UInt<5>("h00")) @[Cat.scala 30:58] + node _T_1179 = cat(_T_1178, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1180 = cat(_T_1179, _T_1177) @[Cat.scala 30:58] + node _T_1181 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1183 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1184 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1191 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1191 is invalid @[RVC.scala 21:19] + _T_1191.bits <= _T_1180 @[RVC.scala 22:14] + _T_1191.rd <= _T_1181 @[RVC.scala 23:12] + _T_1191.rs1 <= UInt<5>("h00") @[RVC.scala 24:13] + _T_1191.rs2 <= _T_1183 @[RVC.scala 25:13] + _T_1191.rs3 <= _T_1184 @[RVC.scala 26:13] + node _T_1197 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1198 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1200 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1202 = cat(_T_1200, UInt<7>("h033")) @[Cat.scala 30:58] + node _T_1203 = cat(_T_1197, _T_1198) @[Cat.scala 30:58] + node _T_1204 = cat(_T_1203, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1205 = cat(_T_1204, _T_1202) @[Cat.scala 30:58] + node _T_1206 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1207 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1208 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1209 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1216 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1216 is invalid @[RVC.scala 21:19] + _T_1216.bits <= _T_1205 @[RVC.scala 22:14] + _T_1216.rd <= _T_1206 @[RVC.scala 23:12] + _T_1216.rs1 <= _T_1207 @[RVC.scala 24:13] + _T_1216.rs2 <= _T_1208 @[RVC.scala 25:13] + _T_1216.rs3 <= _T_1209 @[RVC.scala 26:13] + node _T_1222 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1223 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1227 = cat(UInt<5>("h00"), UInt<7>("h067")) @[Cat.scala 30:58] + node _T_1228 = cat(_T_1222, _T_1223) @[Cat.scala 30:58] + node _T_1229 = cat(_T_1228, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1230 = cat(_T_1229, _T_1227) @[Cat.scala 30:58] + node _T_1231 = shr(_T_1230, 7) @[RVC.scala 132:29] + node _T_1233 = cat(_T_1231, UInt<7>("h01f")) @[Cat.scala 30:58] + node _T_1234 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1236 = neq(_T_1234, UInt<1>("h00")) @[RVC.scala 133:37] + node _T_1237 = mux(_T_1236, _T_1230, _T_1233) @[RVC.scala 133:33] + node _T_1239 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1240 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1241 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1248 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1248 is invalid @[RVC.scala 21:19] + _T_1248.bits <= _T_1237 @[RVC.scala 22:14] + _T_1248.rd <= UInt<5>("h00") @[RVC.scala 23:12] + _T_1248.rs1 <= _T_1239 @[RVC.scala 24:13] + _T_1248.rs2 <= _T_1240 @[RVC.scala 25:13] + _T_1248.rs3 <= _T_1241 @[RVC.scala 26:13] + node _T_1254 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1256 = neq(_T_1254, UInt<1>("h00")) @[RVC.scala 134:27] + node _T_1257 = mux(_T_1256, _T_1191, _T_1248) @[RVC.scala 134:22] + node _T_1263 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1264 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1268 = cat(UInt<5>("h01"), UInt<7>("h067")) @[Cat.scala 30:58] + node _T_1269 = cat(_T_1263, _T_1264) @[Cat.scala 30:58] + node _T_1270 = cat(_T_1269, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1271 = cat(_T_1270, _T_1268) @[Cat.scala 30:58] + node _T_1272 = shr(_T_1230, 7) @[RVC.scala 136:27] + node _T_1274 = cat(_T_1272, UInt<7>("h073")) @[Cat.scala 30:58] + node _T_1276 = or(_T_1274, UInt<21>("h0100000")) @[RVC.scala 136:47] + node _T_1277 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1279 = neq(_T_1277, UInt<1>("h00")) @[RVC.scala 137:37] + node _T_1280 = mux(_T_1279, _T_1271, _T_1276) @[RVC.scala 137:33] + node _T_1282 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1283 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1284 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1291 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1291 is invalid @[RVC.scala 21:19] + _T_1291.bits <= _T_1280 @[RVC.scala 22:14] + _T_1291.rd <= UInt<5>("h01") @[RVC.scala 23:12] + _T_1291.rs1 <= _T_1282 @[RVC.scala 24:13] + _T_1291.rs2 <= _T_1283 @[RVC.scala 25:13] + _T_1291.rs3 <= _T_1284 @[RVC.scala 26:13] + node _T_1297 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1299 = neq(_T_1297, UInt<1>("h00")) @[RVC.scala 138:30] + node _T_1300 = mux(_T_1299, _T_1216, _T_1291) @[RVC.scala 138:25] + node _T_1306 = bits(io.in, 12, 12) @[RVC.scala 139:12] + node _T_1307 = mux(_T_1306, _T_1300, _T_1257) @[RVC.scala 139:10] + node _T_1313 = bits(io.in, 9, 7) @[RVC.scala 40:22] + node _T_1314 = bits(io.in, 12, 10) @[RVC.scala 40:30] + node _T_1316 = cat(_T_1313, _T_1314) @[Cat.scala 30:58] + node _T_1317 = cat(_T_1316, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1318 = shr(_T_1317, 5) @[RVC.scala 123:34] + node _T_1319 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1322 = bits(io.in, 9, 7) @[RVC.scala 40:22] + node _T_1323 = bits(io.in, 12, 10) @[RVC.scala 40:30] + node _T_1325 = cat(_T_1322, _T_1323) @[Cat.scala 30:58] + node _T_1326 = cat(_T_1325, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1327 = bits(_T_1326, 4, 0) @[RVC.scala 123:67] + node _T_1329 = cat(UInt<3>("h03"), _T_1327) @[Cat.scala 30:58] + node _T_1330 = cat(_T_1329, UInt<7>("h027")) @[Cat.scala 30:58] + node _T_1331 = cat(_T_1318, _T_1319) @[Cat.scala 30:58] + node _T_1332 = cat(_T_1331, UInt<5>("h02")) @[Cat.scala 30:58] + node _T_1333 = cat(_T_1332, _T_1330) @[Cat.scala 30:58] + node _T_1334 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1336 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1337 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1344 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1344 is invalid @[RVC.scala 21:19] + _T_1344.bits <= _T_1333 @[RVC.scala 22:14] + _T_1344.rd <= _T_1334 @[RVC.scala 23:12] + _T_1344.rs1 <= UInt<5>("h02") @[RVC.scala 24:13] + _T_1344.rs2 <= _T_1336 @[RVC.scala 25:13] + _T_1344.rs3 <= _T_1337 @[RVC.scala 26:13] + node _T_1350 = bits(io.in, 8, 7) @[RVC.scala 39:22] + node _T_1351 = bits(io.in, 12, 9) @[RVC.scala 39:30] + node _T_1353 = cat(_T_1350, _T_1351) @[Cat.scala 30:58] + node _T_1354 = cat(_T_1353, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_1355 = shr(_T_1354, 5) @[RVC.scala 122:33] + node _T_1356 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1359 = bits(io.in, 8, 7) @[RVC.scala 39:22] + node _T_1360 = bits(io.in, 12, 9) @[RVC.scala 39:30] + node _T_1362 = cat(_T_1359, _T_1360) @[Cat.scala 30:58] + node _T_1363 = cat(_T_1362, UInt<2>("h00")) @[Cat.scala 30:58] + node _T_1364 = bits(_T_1363, 4, 0) @[RVC.scala 122:66] + node _T_1366 = cat(UInt<3>("h02"), _T_1364) @[Cat.scala 30:58] + node _T_1367 = cat(_T_1366, UInt<7>("h023")) @[Cat.scala 30:58] + node _T_1368 = cat(_T_1355, _T_1356) @[Cat.scala 30:58] + node _T_1369 = cat(_T_1368, UInt<5>("h02")) @[Cat.scala 30:58] + node _T_1370 = cat(_T_1369, _T_1367) @[Cat.scala 30:58] + node _T_1371 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1373 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1374 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1381 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1381 is invalid @[RVC.scala 21:19] + _T_1381.bits <= _T_1370 @[RVC.scala 22:14] + _T_1381.rd <= _T_1371 @[RVC.scala 23:12] + _T_1381.rs1 <= UInt<5>("h02") @[RVC.scala 24:13] + _T_1381.rs2 <= _T_1373 @[RVC.scala 25:13] + _T_1381.rs3 <= _T_1374 @[RVC.scala 26:13] + node _T_1387 = bits(io.in, 9, 7) @[RVC.scala 40:22] + node _T_1388 = bits(io.in, 12, 10) @[RVC.scala 40:30] + node _T_1390 = cat(_T_1387, _T_1388) @[Cat.scala 30:58] + node _T_1391 = cat(_T_1390, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1392 = shr(_T_1391, 5) @[RVC.scala 121:33] + node _T_1393 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1396 = bits(io.in, 9, 7) @[RVC.scala 40:22] + node _T_1397 = bits(io.in, 12, 10) @[RVC.scala 40:30] + node _T_1399 = cat(_T_1396, _T_1397) @[Cat.scala 30:58] + node _T_1400 = cat(_T_1399, UInt<3>("h00")) @[Cat.scala 30:58] + node _T_1401 = bits(_T_1400, 4, 0) @[RVC.scala 121:66] + node _T_1403 = cat(UInt<3>("h03"), _T_1401) @[Cat.scala 30:58] + node _T_1404 = cat(_T_1403, UInt<7>("h023")) @[Cat.scala 30:58] + node _T_1405 = cat(_T_1392, _T_1393) @[Cat.scala 30:58] + node _T_1406 = cat(_T_1405, UInt<5>("h02")) @[Cat.scala 30:58] + node _T_1407 = cat(_T_1406, _T_1404) @[Cat.scala 30:58] + node _T_1408 = bits(io.in, 11, 7) @[RVC.scala 33:13] + node _T_1410 = bits(io.in, 6, 2) @[RVC.scala 32:14] + node _T_1411 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1418 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1418 is invalid @[RVC.scala 21:19] + _T_1418.bits <= _T_1407 @[RVC.scala 22:14] + _T_1418.rd <= _T_1408 @[RVC.scala 23:12] + _T_1418.rs1 <= UInt<5>("h02") @[RVC.scala 24:13] + _T_1418.rs2 <= _T_1410 @[RVC.scala 25:13] + _T_1418.rs3 <= _T_1411 @[RVC.scala 26:13] + node _T_1424 = bits(io.in, 11, 7) @[RVC.scala 20:36] + node _T_1425 = bits(io.in, 19, 15) @[RVC.scala 20:57] + node _T_1426 = bits(io.in, 24, 20) @[RVC.scala 20:79] + node _T_1427 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1434 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1434 is invalid @[RVC.scala 21:19] + _T_1434.bits <= io.in @[RVC.scala 22:14] + _T_1434.rd <= _T_1424 @[RVC.scala 23:12] + _T_1434.rs1 <= _T_1425 @[RVC.scala 24:13] + _T_1434.rs2 <= _T_1426 @[RVC.scala 25:13] + _T_1434.rs3 <= _T_1427 @[RVC.scala 26:13] + node _T_1440 = bits(io.in, 11, 7) @[RVC.scala 20:36] + node _T_1441 = bits(io.in, 19, 15) @[RVC.scala 20:57] + node _T_1442 = bits(io.in, 24, 20) @[RVC.scala 20:79] + node _T_1443 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1450 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1450 is invalid @[RVC.scala 21:19] + _T_1450.bits <= io.in @[RVC.scala 22:14] + _T_1450.rd <= _T_1440 @[RVC.scala 23:12] + _T_1450.rs1 <= _T_1441 @[RVC.scala 24:13] + _T_1450.rs2 <= _T_1442 @[RVC.scala 25:13] + _T_1450.rs3 <= _T_1443 @[RVC.scala 26:13] + node _T_1456 = bits(io.in, 11, 7) @[RVC.scala 20:36] + node _T_1457 = bits(io.in, 19, 15) @[RVC.scala 20:57] + node _T_1458 = bits(io.in, 24, 20) @[RVC.scala 20:79] + node _T_1459 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1466 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1466 is invalid @[RVC.scala 21:19] + _T_1466.bits <= io.in @[RVC.scala 22:14] + _T_1466.rd <= _T_1456 @[RVC.scala 23:12] + _T_1466.rs1 <= _T_1457 @[RVC.scala 24:13] + _T_1466.rs2 <= _T_1458 @[RVC.scala 25:13] + _T_1466.rs3 <= _T_1459 @[RVC.scala 26:13] + node _T_1472 = bits(io.in, 11, 7) @[RVC.scala 20:36] + node _T_1473 = bits(io.in, 19, 15) @[RVC.scala 20:57] + node _T_1474 = bits(io.in, 24, 20) @[RVC.scala 20:79] + node _T_1475 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1482 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1482 is invalid @[RVC.scala 21:19] + _T_1482.bits <= io.in @[RVC.scala 22:14] + _T_1482.rd <= _T_1472 @[RVC.scala 23:12] + _T_1482.rs1 <= _T_1473 @[RVC.scala 24:13] + _T_1482.rs2 <= _T_1474 @[RVC.scala 25:13] + _T_1482.rs3 <= _T_1475 @[RVC.scala 26:13] + node _T_1488 = bits(io.in, 11, 7) @[RVC.scala 20:36] + node _T_1489 = bits(io.in, 19, 15) @[RVC.scala 20:57] + node _T_1490 = bits(io.in, 24, 20) @[RVC.scala 20:79] + node _T_1491 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1498 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1498 is invalid @[RVC.scala 21:19] + _T_1498.bits <= io.in @[RVC.scala 22:14] + _T_1498.rd <= _T_1488 @[RVC.scala 23:12] + _T_1498.rs1 <= _T_1489 @[RVC.scala 24:13] + _T_1498.rs2 <= _T_1490 @[RVC.scala 25:13] + _T_1498.rs3 <= _T_1491 @[RVC.scala 26:13] + node _T_1504 = bits(io.in, 11, 7) @[RVC.scala 20:36] + node _T_1505 = bits(io.in, 19, 15) @[RVC.scala 20:57] + node _T_1506 = bits(io.in, 24, 20) @[RVC.scala 20:79] + node _T_1507 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1514 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1514 is invalid @[RVC.scala 21:19] + _T_1514.bits <= io.in @[RVC.scala 22:14] + _T_1514.rd <= _T_1504 @[RVC.scala 23:12] + _T_1514.rs1 <= _T_1505 @[RVC.scala 24:13] + _T_1514.rs2 <= _T_1506 @[RVC.scala 25:13] + _T_1514.rs3 <= _T_1507 @[RVC.scala 26:13] + node _T_1520 = bits(io.in, 11, 7) @[RVC.scala 20:36] + node _T_1521 = bits(io.in, 19, 15) @[RVC.scala 20:57] + node _T_1522 = bits(io.in, 24, 20) @[RVC.scala 20:79] + node _T_1523 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1530 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1530 is invalid @[RVC.scala 21:19] + _T_1530.bits <= io.in @[RVC.scala 22:14] + _T_1530.rd <= _T_1520 @[RVC.scala 23:12] + _T_1530.rs1 <= _T_1521 @[RVC.scala 24:13] + _T_1530.rs2 <= _T_1522 @[RVC.scala 25:13] + _T_1530.rs3 <= _T_1523 @[RVC.scala 26:13] + node _T_1536 = bits(io.in, 11, 7) @[RVC.scala 20:36] + node _T_1537 = bits(io.in, 19, 15) @[RVC.scala 20:57] + node _T_1538 = bits(io.in, 24, 20) @[RVC.scala 20:79] + node _T_1539 = bits(io.in, 31, 27) @[RVC.scala 20:101] + wire _T_1546 : {bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} @[RVC.scala 21:19] + _T_1546 is invalid @[RVC.scala 21:19] + _T_1546.bits <= io.in @[RVC.scala 22:14] + _T_1546.rd <= _T_1536 @[RVC.scala 23:12] + _T_1546.rs1 <= _T_1537 @[RVC.scala 24:13] + _T_1546.rs2 <= _T_1538 @[RVC.scala 25:13] + _T_1546.rs3 <= _T_1539 @[RVC.scala 26:13] + node _T_1552 = bits(io.in, 1, 0) @[RVC.scala 150:12] + node _T_1553 = bits(io.in, 15, 13) @[RVC.scala 150:20] + node _T_1554 = cat(_T_1552, _T_1553) @[Cat.scala 30:58] + node _T_1556 = and(_T_1554, UInt<4>("h0f")) @[Package.scala 18:26] + node _T_1558 = geq(_T_1554, UInt<5>("h010")) @[Package.scala 19:17] + node _T_1560 = and(_T_1556, UInt<3>("h07")) @[Package.scala 18:26] + node _T_1562 = geq(_T_1556, UInt<4>("h08")) @[Package.scala 19:17] + node _T_1564 = and(_T_1560, UInt<2>("h03")) @[Package.scala 18:26] + node _T_1566 = geq(_T_1560, UInt<3>("h04")) @[Package.scala 19:17] + node _T_1568 = and(_T_1564, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1570 = geq(_T_1564, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1572 = and(_T_1568, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1574 = geq(_T_1568, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1575 = mux(_T_1574, _T_1546, _T_1530) @[Package.scala 19:12] + node _T_1582 = and(_T_1568, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1584 = geq(_T_1568, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1585 = mux(_T_1584, _T_1514, _T_1498) @[Package.scala 19:12] + node _T_1591 = mux(_T_1570, _T_1575, _T_1585) @[Package.scala 19:12] + node _T_1598 = and(_T_1564, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1600 = geq(_T_1564, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1602 = and(_T_1598, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1604 = geq(_T_1598, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1605 = mux(_T_1604, _T_1482, _T_1466) @[Package.scala 19:12] + node _T_1612 = and(_T_1598, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1614 = geq(_T_1598, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1615 = mux(_T_1614, _T_1450, _T_1434) @[Package.scala 19:12] + node _T_1621 = mux(_T_1600, _T_1605, _T_1615) @[Package.scala 19:12] + node _T_1627 = mux(_T_1566, _T_1591, _T_1621) @[Package.scala 19:12] + node _T_1634 = and(_T_1560, UInt<2>("h03")) @[Package.scala 18:26] + node _T_1636 = geq(_T_1560, UInt<3>("h04")) @[Package.scala 19:17] + node _T_1638 = and(_T_1634, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1640 = geq(_T_1634, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1642 = and(_T_1638, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1644 = geq(_T_1638, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1645 = mux(_T_1644, _T_1418, _T_1381) @[Package.scala 19:12] + node _T_1652 = and(_T_1638, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1654 = geq(_T_1638, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1655 = mux(_T_1654, _T_1344, _T_1307) @[Package.scala 19:12] + node _T_1661 = mux(_T_1640, _T_1645, _T_1655) @[Package.scala 19:12] + node _T_1668 = and(_T_1634, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1670 = geq(_T_1634, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1672 = and(_T_1668, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1674 = geq(_T_1668, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1675 = mux(_T_1674, _T_1166, _T_1135) @[Package.scala 19:12] + node _T_1682 = and(_T_1668, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1684 = geq(_T_1668, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1685 = mux(_T_1684, _T_1104, _T_1073) @[Package.scala 19:12] + node _T_1691 = mux(_T_1670, _T_1675, _T_1685) @[Package.scala 19:12] + node _T_1697 = mux(_T_1636, _T_1661, _T_1691) @[Package.scala 19:12] + node _T_1703 = mux(_T_1562, _T_1627, _T_1697) @[Package.scala 19:12] + node _T_1710 = and(_T_1556, UInt<3>("h07")) @[Package.scala 18:26] + node _T_1712 = geq(_T_1556, UInt<4>("h08")) @[Package.scala 19:17] + node _T_1714 = and(_T_1710, UInt<2>("h03")) @[Package.scala 18:26] + node _T_1716 = geq(_T_1710, UInt<3>("h04")) @[Package.scala 19:17] + node _T_1718 = and(_T_1714, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1720 = geq(_T_1714, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1722 = and(_T_1718, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1724 = geq(_T_1718, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1725 = mux(_T_1724, _T_1046, _T_951) @[Package.scala 19:12] + node _T_1732 = and(_T_1718, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1734 = geq(_T_1718, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1735 = mux(_T_1734, _T_854, _T_739) @[Package.scala 19:12] + node _T_1741 = mux(_T_1720, _T_1725, _T_1735) @[Package.scala 19:12] + node _T_1748 = and(_T_1714, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1750 = geq(_T_1714, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1752 = and(_T_1748, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1754 = geq(_T_1748, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1755 = mux(_T_1754, _T_580, _T_472) @[Package.scala 19:12] + node _T_1762 = and(_T_1748, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1764 = geq(_T_1748, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1765 = mux(_T_1764, _T_439, _T_401) @[Package.scala 19:12] + node _T_1771 = mux(_T_1750, _T_1755, _T_1765) @[Package.scala 19:12] + node _T_1777 = mux(_T_1716, _T_1741, _T_1771) @[Package.scala 19:12] + node _T_1784 = and(_T_1710, UInt<2>("h03")) @[Package.scala 18:26] + node _T_1786 = geq(_T_1710, UInt<3>("h04")) @[Package.scala 19:17] + node _T_1788 = and(_T_1784, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1790 = geq(_T_1784, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1792 = and(_T_1788, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1794 = geq(_T_1788, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1795 = mux(_T_1794, _T_368, _T_321) @[Package.scala 19:12] + node _T_1802 = and(_T_1788, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1804 = geq(_T_1788, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1805 = mux(_T_1804, _T_270, _T_223) @[Package.scala 19:12] + node _T_1811 = mux(_T_1790, _T_1795, _T_1805) @[Package.scala 19:12] + node _T_1818 = and(_T_1784, UInt<1>("h01")) @[Package.scala 18:26] + node _T_1820 = geq(_T_1784, UInt<2>("h02")) @[Package.scala 19:17] + node _T_1822 = and(_T_1818, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1824 = geq(_T_1818, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1825 = mux(_T_1824, _T_172, _T_133) @[Package.scala 19:12] + node _T_1832 = and(_T_1818, UInt<1>("h00")) @[Package.scala 18:26] + node _T_1834 = geq(_T_1818, UInt<1>("h01")) @[Package.scala 19:17] + node _T_1835 = mux(_T_1834, _T_92, _T_53) @[Package.scala 19:12] + node _T_1841 = mux(_T_1820, _T_1825, _T_1835) @[Package.scala 19:12] + node _T_1847 = mux(_T_1786, _T_1811, _T_1841) @[Package.scala 19:12] + node _T_1853 = mux(_T_1712, _T_1777, _T_1847) @[Package.scala 19:12] + node _T_1859 = mux(_T_1558, _T_1703, _T_1853) @[Package.scala 19:12] + io.out <- _T_1859 @[RVC.scala 163:12] + diff --git a/scripts/formal_equiv.sh b/scripts/formal_equiv.sh index 9e744d46..2e9fa74d 100644..100755 --- a/scripts/formal_equiv.sh +++ b/scripts/formal_equiv.sh @@ -1,16 +1,19 @@ +#!/usr/bin/env bash # This script is for formally comparing the Verilog emitted by different git revisions # There must be two valid git revision arguments set -e -if [ $# -ne 2 ]; then - echo "There must be exactly two arguments!" +if [ $# -ne 3 ]; then + echo "There must be exactly three arguments!" exit -1 fi HASH1=`git rev-parse $1` HASH2=`git rev-parse $2` -echo "Comparing git revisions $HASH1 and $HASH2" +DUT=$3 + +echo "Comparing git revisions $HASH1 and $HASH2 on $DUT" if [ $HASH1 = $HASH2 ]; then echo "Both git revisions are the same! Nothing to do!" @@ -20,10 +23,10 @@ fi RET="" make_verilog () { git checkout $1 - local filename="rob.$1.v" + local filename="$DUT.$1.v" sbt clean - sbt "run-main firrtl.Driver -i regress/Rob.fir -o $filename -X verilog" + sbt "run-main firrtl.Driver -i $DUT.fir -o $filename -X verilog" RET=$filename } @@ -43,11 +46,18 @@ else echo "Running equivalence check using Yosys" yosys -q -p " read_verilog $FILE1 - rename Rob top1 + rename $DUT top1 + proc + memory + flatten top1 + hierarchy -top top1 + read_verilog $FILE2 - rename Rob top2 + rename $DUT top2 proc memory + flatten top2 + equiv_make top1 top2 equiv hierarchy -top equiv clean -purge |