Remove stanza (#231)

* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)

4 files changed, 0 insertions, 234 deletions

diff --git a/test/passes/infer-widths/dsh.fir b/test/passes/infer-widths/dsh.fir
deleted file mode 100644
index f36b8ad4..00000000
--- a/test/passes/infer-widths/dsh.fir
+++ /dev/null
@@ -1,28 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out | FileCheck %s
-
-;CHECK: Infer Widths
-
-circuit top :
-   module top :
-      wire x : UInt<16>
-      wire z : SInt<16>
-      wire y : UInt<3>
-      wire a : UInt
-      wire b : SInt
-      wire c : UInt
-      wire d : SInt
-      x <= UInt(1)
-      y <= UInt(1)
-      z <= SInt(1)
-
-      a <= dshl(x,y)
-      b <= dshl(z,y)
-      c <= dshr(x,y)
-      d <= dshr(z,y)
-
-
-; CHECK: wire a : UInt<23>
-; CHECK: wire b : SInt<23>
-; CHECK: wire c : UInt<16>
-; CHECK: wire d : SInt<16>
-; CHECK: Finished Infer Widths
diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir
deleted file mode 100644
index 1333fbda..00000000
--- a/test/passes/infer-widths/gcd.fir
+++ /dev/null
@@ -1,49 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p ctd 2>&1 | tee %s.out | FileCheck %s
-
-;CHECK: Infer Widths
-circuit top :
-   module subtracter :
-      input x : UInt
-      input y : UInt
-      output q : UInt
-      q <= tail(sub(x, y),1)
-   module gcd :
-      input a : UInt<16>
-      input b : UInt<16>
-      input e : UInt<1>
-      input clk : Clock
-      input reset : UInt<1>
-      output z : UInt<16>
-      reg x : UInt,clk with :
-         reset => (reset,UInt(0))
-      reg y : UInt,clk with :
-         reset => (reset,UInt(42))
-      when gt(x, y) :
-         inst s of subtracter
-         s.x <= x
-         s.y <= y
-         x <= s.q
-      else :
-         inst s2 of subtracter
-         s2.x <= x
-         s2.y <= y
-         y <= s2.q
-      when e :
-         x <= a
-         y <= b
-      z <= x
-   module top :
-      input a : UInt<16>
-      input b : UInt<16>
-      input clk : Clock
-      input reset : UInt<1>
-      output z : UInt
-      inst i of gcd
-      i.a <= a
-      i.b <= b
-      i.clk <= clk
-      i.reset <= reset
-      i.e <= UInt(1)
-      z <= i.z
-
-; CHECK: Finished Infer Widths
diff --git a/test/passes/infer-widths/shr.fir b/test/passes/infer-widths/shr.fir
deleted file mode 100644
index 6a918ba9..00000000
--- a/test/passes/infer-widths/shr.fir
+++ /dev/null
@@ -1,129 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-
-;CHECK: Infer Widths
-; CHECK: Finished Infer Widths
-
-circuit MemSerdes : 
-  module MemSerdes : 
-    input clock : Clock
-    input reset : UInt<1>
-    input wide : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<7>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<7>}}}
-    output narrow : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}}
-    
-    wide.resp.bits.tag <= UInt<1>("h00")
-    wide.resp.bits.data <= UInt<1>("h00")
-    wide.resp.valid <= UInt<1>("h00")
-    wide.req_data.ready <= UInt<1>("h00")
-    wide.req_cmd.ready <= UInt<1>("h00")
-    narrow.req.bits <= UInt<1>("h00")
-    narrow.req.valid <= UInt<1>("h00")
-    
-    node T_218961 = cat(wide.req_cmd.bits.tag, wide.req_cmd.bits.rw)
-    node T_218962 = cat(wide.req_cmd.bits.addr, T_218961)
-    reg out_buf : UInt, clock with :
-       reset => ( reset, out_buf)
-    reg in_buf : UInt, clock with :
-       reset => ( reset, in_buf)
-    reg state : UInt<3>, clock with :
-       reset => ( reset,UInt<3>("h00"))
-    reg send_cnt : UInt<3>, clock with :
-       reset => ( reset, UInt<3>("h00"))
-    reg data_send_cnt : UInt<2>, clock with :
-       reset => ( reset, UInt<2>("h00"))
-    node T_218984 = eq(send_cnt, UInt<2>("h02"))
-    node adone = and(narrow.req.ready, T_218984)
-    node T_218987 = eq(send_cnt, UInt<3>("h07"))
-    node ddone = and(narrow.req.ready, T_218987)
-    
-    node T_218989 = and(narrow.req.valid, narrow.req.ready)
-    when T_218989 : 
-      node T_218991 = tail(add(send_cnt, UInt<1>("h01")),1)
-      send_cnt <= T_218991
-      node T_218992 = shr(out_buf, 16)
-      out_buf <= T_218992
-    
-    node T_218993 = and(wide.req_cmd.valid, wide.req_cmd.ready)
-    when T_218993 : 
-      node T_218994 = cat(wide.req_cmd.bits.tag, wide.req_cmd.bits.rw)
-      node T_218995 = cat(wide.req_cmd.bits.addr, T_218994)
-      out_buf <= T_218995
-    
-    node T_218996 = and(wide.req_data.valid, wide.req_data.ready)
-    when T_218996 : out_buf <= wide.req_data.bits.data
-    node T_218997 = eq(state, UInt<3>("h00"))
-    wide.req_cmd.ready <= T_218997
-    node T_218998 = eq(state, UInt<3>("h03"))
-    wide.req_data.ready <= T_218998
-    node T_218999 = eq(state, UInt<3>("h01"))
-    node T_219000 = eq(state, UInt<3>("h02"))
-    node T_219001 = or(T_218999, T_219000)
-    node T_219002 = eq(state, UInt<3>("h04"))
-    node T_219003 = or(T_219001, T_219002)
-    narrow.req.valid <= T_219003
-    narrow.req.bits <= out_buf
-    
-    
-    node T_219004 = eq(state, UInt<3>("h00"))
-    node T_219005 = and(T_219004, wide.req_cmd.valid)
-    when T_219005 : 
-      node T_219006 = mux(wide.req_cmd.bits.rw, UInt<3>("h02"), UInt<3>("h01"))
-      state <= T_219006
-    
-    
-    node T_219007 = eq(state, UInt<3>("h01"))
-    node T_219008 = and(T_219007, adone)
-    when T_219008 : 
-      state <= UInt<3>("h00")
-      send_cnt <= UInt<1>("h00")
-    
-    
-    node T_219010 = eq(state, UInt<3>("h02"))
-    node T_219011 = and(T_219010, adone)
-    when T_219011 : 
-      state <= UInt<3>("h03")
-      send_cnt <= UInt<1>("h00")
-    
-    
-    node T_219013 = eq(state, UInt<3>("h03"))
-    node T_219014 = and(T_219013, wide.req_data.valid)
-    when T_219014 : state <= UInt<3>("h04")
-    
-    
-    node T_219015 = eq(state, UInt<3>("h04"))
-    node T_219016 = and(T_219015, ddone)
-    when T_219016 : 
-      node T_219018 = tail(add(data_send_cnt, UInt<1>("h01")),1)
-      data_send_cnt <= T_219018
-      node T_219020 = eq(data_send_cnt, UInt<2>("h03"))
-      node T_219021 = mux(T_219020, UInt<3>("h00"), UInt<3>("h03"))
-      state <= T_219021
-      send_cnt <= UInt<1>("h00")
-    reg recv_cnt : UInt<4>, clock with :
-       reset => ( reset, UInt<4>("h00"))
-    reg data_recv_cnt : UInt<2>, clock with :
-       reset => ( reset, UInt<2>("h00"))
-    reg resp_val : UInt<1>, clock with :
-       reset => ( reset, UInt<1>("h00"))
-    resp_val <= UInt<1>("h00")
-    when narrow.resp.valid : 
-      node T_219031 = tail(add(recv_cnt, UInt<1>("h01")),1)
-      recv_cnt <= T_219031
-      
-      node T_219033 = eq(recv_cnt, UInt<4>("h08"))
-      when T_219033 : 
-        recv_cnt <= UInt<1>("h00")
-        node T_219036 = tail(add(data_recv_cnt, UInt<1>("h01")),1)
-        data_recv_cnt <= T_219036
-        resp_val <= UInt<1>("h01")
-      node T_219038 = bits(in_buf, 143, 16)
-      node T_219039 = cat(narrow.resp.bits, T_219038)
-      in_buf <= T_219039
-    wide.resp.valid <= resp_val
-    wire T_219043 : {data : UInt<128>, tag : UInt<7>}
-    T_219043.tag <= UInt<1>("h00")
-    T_219043.data <= UInt<1>("h00")
-    node T_219048 = bits(in_buf, 6, 0)
-    T_219043.tag <= T_219048
-    node T_219049 = bits(in_buf, 134, 7)
-    T_219043.data <= T_219049
-    wide.resp.bits <- T_219043
diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir
deleted file mode 100644
index 63b31a32..00000000
--- a/test/passes/infer-widths/simple.fir
+++ /dev/null
@@ -1,28 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p cTwd 2>&1 | tee %s.out | FileCheck %s
-
-;CHECK: Infer Widths
-circuit top :
-   module top :
-      input clk : Clock
-      input reset : UInt<1>
-      wire e : UInt<30>
-      e <= UInt(1)
-      reg y : UInt,clk with :
-         reset => (reset,y)
-      y <= e
-
-      wire a : UInt<20>
-      a <= UInt(1)
-      wire b : UInt<10>
-      b <= UInt(1)
-      wire c : UInt
-      c <= UInt(1)
-      wire z : UInt
-       
-      z <= mux(c,a,b)
-
-   
-
-; CHECK: Finished Infer Widths
-; CHECK: Done!
-