diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/features/TwoClocks.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/features/TwoClocks.fir')
| -rw-r--r-- | test/features/TwoClocks.fir | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/test/features/TwoClocks.fir b/test/features/TwoClocks.fir index 9665c153..f68a2769 100644 --- a/test/features/TwoClocks.fir +++ b/test/features/TwoClocks.fir @@ -8,14 +8,14 @@ circuit Top : reg src : UInt<10>, clk1, reset1 reg sink : UInt<10>, clk2, reset2 - onreset src := UInt(0) - src := addw(src,UInt(1)) + onreset src <= UInt(0) + src <= addw(src,UInt(1)) reg sync_A : UInt<10>, clk2, reset2 - sync_A := src + sync_A <= src reg sync_B : UInt<10>, clk2, reset2 - sync_B := sync_A + sync_B <= sync_A - sink := sync_B + sink <= sync_B ;CHECK: Done! |