From be78d49aa01c097978f69a3b022acb2047fdf438 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 9 Dec 2015 18:31:45 -0800
Subject: New memory works with verilog. Slowly changing tests and fixing bugs.
 Decided to not have Conditionally in low firrtl - instead, Print and Stop
 have enables

---
 test/features/TwoClocks.fir | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'test/features/TwoClocks.fir')

diff --git a/test/features/TwoClocks.fir b/test/features/TwoClocks.fir
index 9665c153..f68a2769 100644
--- a/test/features/TwoClocks.fir
+++ b/test/features/TwoClocks.fir
@@ -8,14 +8,14 @@ circuit Top :
     reg src : UInt<10>, clk1, reset1
     reg sink : UInt<10>, clk2, reset2
 
-    onreset src := UInt(0)
-    src := addw(src,UInt(1))
+    onreset src <= UInt(0)
+    src <= addw(src,UInt(1))
 
     reg sync_A : UInt<10>, clk2, reset2
-    sync_A := src
+    sync_A <= src
     reg sync_B : UInt<10>, clk2, reset2
-    sync_B := sync_A
+    sync_B <= sync_A
 
-    sink := sync_B
+    sink <= sync_B
 
 ;CHECK: Done!
-- 
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