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authorazidar2015-12-09 18:31:45 -0800
committerazidar2016-01-16 14:28:17 -0800
commitbe78d49aa01c097978f69a3b022acb2047fdf438 (patch)
tree76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/errors/width/NegWidth.fir
parentc427b31a1ef8361b643d5f7435aeb42472dfe626 (diff)
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
Diffstat (limited to 'test/errors/width/NegWidth.fir')
-rw-r--r--test/errors/width/NegWidth.fir2
1 files changed, 1 insertions, 1 deletions
diff --git a/test/errors/width/NegWidth.fir b/test/errors/width/NegWidth.fir
index 5d5bbf43..e02884a8 100644
--- a/test/errors/width/NegWidth.fir
+++ b/test/errors/width/NegWidth.fir
@@ -6,4 +6,4 @@ circuit Top :
output y : UInt
wire x : UInt<2>
- y := shr(x,4)
+ y <= shr(x,4)