From be78d49aa01c097978f69a3b022acb2047fdf438 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 9 Dec 2015 18:31:45 -0800
Subject: New memory works with verilog. Slowly changing tests and fixing bugs.
 Decided to not have Conditionally in low firrtl - instead, Print and Stop
 have enables

---
 test/errors/width/NegWidth.fir | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'test/errors/width/NegWidth.fir')

diff --git a/test/errors/width/NegWidth.fir b/test/errors/width/NegWidth.fir
index 5d5bbf43..e02884a8 100644
--- a/test/errors/width/NegWidth.fir
+++ b/test/errors/width/NegWidth.fir
@@ -6,4 +6,4 @@ circuit Top :
     output y : UInt
 
     wire x : UInt<2>
-    y := shr(x,4)
+    y <= shr(x,4)
-- 
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