Remove stanza (#231)

* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)

5 files changed, 0 insertions, 73 deletions

diff --git a/test/errors/type/AccessIndexUInt.fir b/test/errors/type/AccessIndexUInt.fir
deleted file mode 100644
index d47bb7c6..00000000
--- a/test/errors/type/AccessIndexUInt.fir
+++ /dev/null
@@ -1,8 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-;CHECK: AccessIndexUInt.fir@8.4: [module Top]  Access index must be a UInt type.
-circuit Top : 
-  module Top : 
-    input b : UInt<32>[62]
-    input a : SInt<8>
-    output c : UInt<32>
-    c <= b[a]
diff --git a/test/errors/type/BulkConnect.fir b/test/errors/type/BulkConnect.fir
deleted file mode 100644
index 26f5c156..00000000
--- a/test/errors/type/BulkConnect.fir
+++ /dev/null
@@ -1,32 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-;CHECK: BulkConnect.fir@10.4: [module Top]  Type mismatch.
-;CHECK: BulkConnect.fir@14.4: [module Top]  Type mismatch.
-;CHECK: BulkConnect.fir@26.4: [module Top]  Type mismatch.
-;CHECK: BulkConnect.fir@30.4: [module Top]  Type mismatch.
-circuit Top : 
-  module Top : 
-    wire a : { w : UInt<42>}
-    wire b : { w : SInt<42>}
-    a <- b 
-
-    wire c : { w : UInt<10>}
-    wire d : { flip w : UInt<12> }
-    c <- d
-
-    wire e : { w : UInt<10>}
-    wire f : { x : UInt<12> }
-    e <- f
-
-    wire g : { w : { y : UInt<10> }}
-    wire h : { w : { x : UInt<12> }}
-    g <- h
-
-    wire i : { w : { flip y : UInt<10> }}
-    wire j : { w : { y : UInt<12> }}
-    i <- j
-
-    wire k : { w : { y : SInt<10> }}
-    wire l : { w : { y : UInt<12> }}
-    k <- l
-
-
diff --git a/test/errors/type/MuxWithFlips.fir b/test/errors/type/MuxWithFlips.fir
deleted file mode 100644
index 9a8b2170..00000000
--- a/test/errors/type/MuxWithFlips.fir
+++ /dev/null
@@ -1,12 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; CHECK: [module Top]  Must mux between passive types.
-; CHECK: [module Top]  A mux condition must be of type UInt.
-
-circuit Top : 
-  module Top : 
-    input c : SInt<1>
-    input x : {x : UInt, flip y : UInt}
-    input y : {x : UInt, flip y : UInt}
-    output z : {x : UInt, flip y : UInt}
-    z <= mux(c,x,y)
-
diff --git a/test/errors/type/NodeWithFlips.fir b/test/errors/type/NodeWithFlips.fir
deleted file mode 100644
index 2030955f..00000000
--- a/test/errors/type/NodeWithFlips.fir
+++ /dev/null
@@ -1,8 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; CHECK: Node must be a passive type.
-
-circuit Top : 
-  module Top : 
-    wire x : {x : UInt, flip y : UInt}
-    node z = x
-
diff --git a/test/errors/type/Primop.fir b/test/errors/type/Primop.fir
deleted file mode 100644
index dcf19935..00000000
--- a/test/errors/type/Primop.fir
+++ /dev/null
@@ -1,13 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; CHECK: Must mux between equivalent types.
-; CHECK: Primop add cannot operate on non-ground types.
-; CHECK: A mux condition must be of type UInt.
-
-circuit Top : 
-  module Top :
-    node x = mux(UInt(1),SInt(1),UInt(1))
-    wire a : { q : UInt<1> }
-    node y = add(a,a)
-    node z = bits(SInt<10>(-1),1,2)
-    node zz = mux(SInt(1),UInt(1),UInt(1))
-