| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-08-15 | Remove stanza (#231) | Adam Izraelevitz |
| 2016-01-24 | Added muxing on passive aggregate types | azidar |
| 2016-01-17 | Added check for uint on access index type | azidar |
| 2016-01-16 | Fixed all tests so they either pass are marked as expected failures | azidar |
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar |
| 2015-08-24 | Changed all tests to use verilog backend. | azidar |
| 2015-08-20 | Added tests, cleaned up repo | azidar |
| 2015-08-03 | Changed name mangling to use _ as a delin. Fixed bug in checking for | azidar |
| 2015-07-31 | Added errors for bulk connects where field names match but types/flips don't | azidar |
| 2015-07-30 | Updated error and feature tests. Fixed bug in detecting incorrect genders | azidar |
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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