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authorazidar2015-07-31 16:31:10 -0700
committerazidar2015-07-31 16:31:10 -0700
commitba55a55ee07805d28995b535beb5a19bd4a99c5c (patch)
treebc636b7f11efb34166a357678a1b4c2471f33552 /test/errors/type
parent0fc3314eb15c6f2e42b21a175978a69217810879 (diff)
Added errors for bulk connects where field names match but types/flips don't
Diffstat (limited to 'test/errors/type')
-rw-r--r--test/errors/type/BulkConnect.fir32
1 files changed, 32 insertions, 0 deletions
diff --git a/test/errors/type/BulkConnect.fir b/test/errors/type/BulkConnect.fir
new file mode 100644
index 00000000..da62ef4d
--- /dev/null
+++ b/test/errors/type/BulkConnect.fir
@@ -0,0 +1,32 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
+;CHECK: BulkConnect.fir@10.4: [module Top] Type mismatch.
+;CHECK: BulkConnect.fir@14.4: [module Top] Type mismatch.
+;CHECK: BulkConnect.fir@26.4: [module Top] Type mismatch.
+;CHECK: BulkConnect.fir@30.4: [module Top] Type mismatch.
+circuit Top :
+ module Top :
+ wire a : { w : UInt<42>}
+ wire b : { w : SInt<42>}
+ a <> b
+
+ wire c : { w : UInt<10>}
+ wire d : { flip w : UInt<12> }
+ c <> d
+
+ wire e : { w : UInt<10>}
+ wire f : { x : UInt<12> }
+ e <> f
+
+ wire g : { w : { y : UInt<10> }}
+ wire h : { w : { x : UInt<12> }}
+ g <> h
+
+ wire i : { w : { flip y : UInt<10> }}
+ wire j : { w : { y : UInt<12> }}
+ i <> j
+
+ wire k : { w : { y : SInt<10> }}
+ wire l : { w : { y : UInt<12> }}
+ k <> l
+
+