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authorAdam Izraelevitz2016-08-15 10:32:41 -0700
committerGitHub2016-08-15 10:32:41 -0700
commitbebd04c4c68c320b2b72325e348c726dc33beae6 (patch)
tree69f6d4da577977cc7ff428b0545bb4735507aad0 /test/errors/high-form/RemoveScope.fir
parentcca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff)
Remove stanza (#231)
* Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before)
Diffstat (limited to 'test/errors/high-form/RemoveScope.fir')
-rw-r--r--test/errors/high-form/RemoveScope.fir18
1 files changed, 0 insertions, 18 deletions
diff --git a/test/errors/high-form/RemoveScope.fir b/test/errors/high-form/RemoveScope.fir
deleted file mode 100644
index 63dfb4de..00000000
--- a/test/errors/high-form/RemoveScope.fir
+++ /dev/null
@@ -1,18 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; XFAIL: *
-; CHECK: Done!
-
-circuit Top :
- module Top :
- wire x : UInt<1>
- node p = UInt(1)
- when p :
- wire x : UInt<1>
- x <= UInt(1)
- node y = add(x,UInt(1))
- else :
- wire x : UInt<1>
- x <= UInt(1)
- node z = add(x,UInt(1))
- x <= UInt(1)
- node w = add(x,UInt(1))