diff options
| author | azidar | 2015-08-24 10:58:49 -0700 |
|---|---|---|
| committer | azidar | 2015-08-24 10:58:49 -0700 |
| commit | 50cf7a4823d69967dcb2b10cdef892b0ab5f2184 (patch) | |
| tree | b8a4d9fc9b2063703a5f37fec538f7a220cc7681 /test/chisel3/ModuleWire.fir | |
| parent | 02a7fb53fc424346a1693f23661a1b1a4a867c4f (diff) | |
Removed old chisel3 tests that all failed for syntax reasons. Tests should now be small examples, categorized by either passes, errors, or features.
Diffstat (limited to 'test/chisel3/ModuleWire.fir')
| -rw-r--r-- | test/chisel3/ModuleWire.fir | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/test/chisel3/ModuleWire.fir b/test/chisel3/ModuleWire.fir deleted file mode 100644 index 3be7f928..00000000 --- a/test/chisel3/ModuleWire.fir +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s -;CHECK: Done! - -circuit ModuleWire : - module Inc : - input in : UInt<32> - output out : UInt<32> - - node T_12 = add-wrap(in, UInt<1>(1)) - out := T_12 - module ModuleWire : - input in : UInt<32> - output out : UInt<32> - - inst T_13 of Inc - T_13.in := in - out := T_13.out |