From 50cf7a4823d69967dcb2b10cdef892b0ab5f2184 Mon Sep 17 00:00:00 2001
From: azidar
Date: Mon, 24 Aug 2015 10:58:49 -0700
Subject: Removed old chisel3 tests that all failed for syntax reasons. Tests
 should now be small examples, categorized by either passes, errors, or
 features.

---
 test/chisel3/ModuleWire.fir | 17 -----------------
 1 file changed, 17 deletions(-)
 delete mode 100644 test/chisel3/ModuleWire.fir

(limited to 'test/chisel3/ModuleWire.fir')

diff --git a/test/chisel3/ModuleWire.fir b/test/chisel3/ModuleWire.fir
deleted file mode 100644
index 3be7f928..00000000
--- a/test/chisel3/ModuleWire.fir
+++ /dev/null
@@ -1,17 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
-;CHECK: Done!
-
-circuit ModuleWire : 
-  module Inc : 
-    input in : UInt<32>
-    output out : UInt<32>
-    
-    node T_12 = add-wrap(in, UInt<1>(1))
-    out := T_12
-  module ModuleWire : 
-    input in : UInt<32>
-    output out : UInt<32>
-    
-    inst T_13 of Inc
-    T_13.in := in
-    out := T_13.out
-- 
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