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| author | Albert Magyar | 2020-04-13 14:01:35 -0700 |
|---|---|---|
| committer | Albert Magyar | 2020-04-13 17:48:00 -0700 |
| commit | 66c3695550f60903efe90bb6839d0f75cad4d7fd (patch) | |
| tree | cb56c8bc801403ba17964b2d8024624dec71abe4 /src/test | |
| parent | bda5a61ad6abc965b21f390b47f0e9b1002eea02 (diff) | |
Ensure PadWidths is run in mverilog compiler
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/LoweringCompilersSpec.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala index 648e45cd..ea591450 100644 --- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala +++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala @@ -102,6 +102,7 @@ class LoweringCompilersSpec extends FlatSpec with Matchers { new firrtl.transforms.DeadCodeElimination) case _: MinimumLowFirrtlOptimization => Seq( passes.RemoveValidIf, + passes.PadWidths, passes.Legalize, passes.memlib.VerilogMemDelays, // TODO move to Verilog emitter passes.SplitExpressions) |