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Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/LoweringCompilersSpec.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala index 648e45cd..ea591450 100644 --- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala +++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala @@ -102,6 +102,7 @@ class LoweringCompilersSpec extends FlatSpec with Matchers { new firrtl.transforms.DeadCodeElimination) case _: MinimumLowFirrtlOptimization => Seq( passes.RemoveValidIf, + passes.PadWidths, passes.Legalize, passes.memlib.VerilogMemDelays, // TODO move to Verilog emitter passes.SplitExpressions) |