diff options
| author | Albert Magyar | 2020-04-13 14:01:35 -0700 |
|---|---|---|
| committer | Albert Magyar | 2020-04-13 17:48:00 -0700 |
| commit | 66c3695550f60903efe90bb6839d0f75cad4d7fd (patch) | |
| tree | cb56c8bc801403ba17964b2d8024624dec71abe4 /src | |
| parent | bda5a61ad6abc965b21f390b47f0e9b1002eea02 (diff) | |
Ensure PadWidths is run in mverilog compiler
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/passes/PadWidths.scala | 5 | ||||
| -rw-r--r-- | src/main/scala/firrtl/stage/Forms.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/LoweringCompilersSpec.scala | 1 |
3 files changed, 5 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala index 0b318511..163b2270 100644 --- a/src/main/scala/firrtl/passes/PadWidths.scala +++ b/src/main/scala/firrtl/passes/PadWidths.scala @@ -17,8 +17,9 @@ object PadWidths extends Pass { ((new mutable.LinkedHashSet()) ++ firrtl.stage.Forms.LowForm - Dependency(firrtl.passes.Legalize) - + Dependency(firrtl.passes.RemoveValidIf) - + Dependency[firrtl.transforms.ConstantPropagation]).toSeq + + Dependency(firrtl.passes.RemoveValidIf)).toSeq + + override val optionalPrerequisites = Seq(Dependency[firrtl.transforms.ConstantPropagation]) override val dependents = Seq( Dependency(firrtl.passes.memlib.VerilogMemDelays), diff --git a/src/main/scala/firrtl/stage/Forms.scala b/src/main/scala/firrtl/stage/Forms.scala index 76587abc..1c3f4816 100644 --- a/src/main/scala/firrtl/stage/Forms.scala +++ b/src/main/scala/firrtl/stage/Forms.scala @@ -67,12 +67,12 @@ object Forms { val LowFormMinimumOptimized: Seq[TransformDependency] = LowForm ++ Seq( Dependency(passes.RemoveValidIf), + Dependency(passes.PadWidths), Dependency(passes.memlib.VerilogMemDelays), Dependency(passes.SplitExpressions) ) val LowFormOptimized: Seq[TransformDependency] = LowFormMinimumOptimized ++ Seq( Dependency[firrtl.transforms.ConstantPropagation], - Dependency(passes.PadWidths), Dependency[firrtl.transforms.CombineCats], Dependency(passes.CommonSubexpressionElimination), Dependency[firrtl.transforms.DeadCodeElimination] ) diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala index 648e45cd..ea591450 100644 --- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala +++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala @@ -102,6 +102,7 @@ class LoweringCompilersSpec extends FlatSpec with Matchers { new firrtl.transforms.DeadCodeElimination) case _: MinimumLowFirrtlOptimization => Seq( passes.RemoveValidIf, + passes.PadWidths, passes.Legalize, passes.memlib.VerilogMemDelays, // TODO move to Verilog emitter passes.SplitExpressions) |