Merge pull request #1512 from freechipsproject/issue-1511

Fix mixed -E and -e emission

2 files changed, 19 insertions, 5 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 91b04349..1ba218f0 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -143,10 +143,10 @@ sealed abstract class FirrtlEmitter(form: CircuitForm) extends Transform with Em
 
   override def execute(state: CircuitState): CircuitState = {
     val newAnnos = state.annotations.flatMap {
-      case EmitCircuitAnnotation(_) =>
+      case EmitCircuitAnnotation(a) if this.getClass == a =>
         Seq(EmittedFirrtlCircuitAnnotation(
               EmittedFirrtlCircuit(state.circuit.main, state.circuit.serialize, outputSuffix)))
-      case EmitAllModulesAnnotation(_) =>
+      case EmitAllModulesAnnotation(a) if this.getClass == a =>
         emitAllModules(state.circuit) map (EmittedFirrtlModuleAnnotation(_))
       case _ => Seq()
     }
@@ -1077,12 +1077,12 @@ class VerilogEmitter extends SeqTransform with Emitter {
 
   override def execute(state: CircuitState): CircuitState = {
     val newAnnos = state.annotations.flatMap {
-      case EmitCircuitAnnotation(_) =>
+      case EmitCircuitAnnotation(a) if this.getClass == a =>
         val writer = new java.io.StringWriter
         emit(state, writer)
         Seq(EmittedVerilogCircuitAnnotation(EmittedVerilogCircuit(state.circuit.main, writer.toString, outputSuffix)))
 
-      case EmitAllModulesAnnotation(_) =>
+      case EmitAllModulesAnnotation(a) if this.getClass == a =>
         val cs = runTransforms(state)
         val emissionOptions = new EmissionOptions(cs.annotations)
         val moduleMap = cs.circuit.modules.map(m => m.name -> m).toMap
diff --git a/src/test/scala/firrtlTests/stage/FirrtlMainSpec.scala b/src/test/scala/firrtlTests/stage/FirrtlMainSpec.scala
index 15f7a021..9529507d 100644
--- a/src/test/scala/firrtlTests/stage/FirrtlMainSpec.scala
+++ b/src/test/scala/firrtlTests/stage/FirrtlMainSpec.scala
@@ -22,11 +22,12 @@ class FirrtlMainSpec extends AnyFeatureSpec with GivenWhenThen with Matchers wit
     with BackendCompilationUtilities {
 
   /** Parameterizes one test of [[FirrtlMain]]. Running the [[FirrtlMain]] `main` with certain args should produce
-    * certain files.
+    * certain files and not produce others.
     * @param args arguments to pass
     * @param circuit a [[FirrtlCircuitFixture]] to use. This will generate an appropriate '-i $targetDir/$main.fi'
     * argument.
     * @param files expected files that will be created
+    * @param files files that should NOT be created
     * @param stdout expected stdout string, None if no output expected
     * @param stderr expected stderr string, None if no output expected
     * @param result expected exit code
@@ -35,6 +36,7 @@ class FirrtlMainSpec extends AnyFeatureSpec with GivenWhenThen with Matchers wit
     args: Array[String],
     circuit: Option[FirrtlCircuitFixture] = Some(new SimpleFirrtlCircuitFixture),
     files: Seq[String] = Seq.empty,
+    notFiles: Seq[String] = Seq.empty,
     stdout: Option[String] = None,
     stderr: Option[String] = None,
     result: Int = 0) {
@@ -66,6 +68,7 @@ class FirrtlMainSpec extends AnyFeatureSpec with GivenWhenThen with Matchers wit
       }
 
       p.files.foreach( f => new File(td.buildDir + s"/$f").delete() )
+      p.notFiles.foreach( f => new File(td.buildDir + s"/$f").delete() )
 
       When(s"""the user tries to compile with '${p.argsString}'""")
       val (stdout, stderr, result) =
@@ -103,6 +106,12 @@ class FirrtlMainSpec extends AnyFeatureSpec with GivenWhenThen with Matchers wit
         val out = new File(td.buildDir + s"/$f")
         out should (exist)
       }
+
+      p.notFiles.foreach { f =>
+        And(s"file '$f' should NOT be emitted in the target directory")
+        val out = new File(td.buildDir + s"/$f")
+        out should not (exist)
+      }
     }
   }
 
@@ -207,6 +216,11 @@ class FirrtlMainSpec extends AnyFeatureSpec with GivenWhenThen with Matchers wit
                       files  = Seq("Top.sv", "Child.sv"),
                       stdout = Some("SystemVerilog Compiler behaves the same as the Verilog Compiler!")),
 
+      /* Test mixing of -E with -e */
+      FirrtlMainTest(args     = Array("-X", "middle", "-E", "high", "-e", "middle"),
+                     files    = Seq("Top.hi.fir", "Top.mid.fir", "Child.mid.fir"),
+                     notFiles = Seq("Child.hi.fir")),
+
       /* Test changes to output file name */
       FirrtlMainTest(args   = Array("-X", "none", "-E", "chirrtl", "-o", "foo"),
                       files  = Seq("foo.fir")),