From 66c3695550f60903efe90bb6839d0f75cad4d7fd Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Mon, 13 Apr 2020 14:01:35 -0700
Subject: Ensure PadWidths is run in mverilog compiler

---
 src/test/scala/firrtlTests/LoweringCompilersSpec.scala | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
index 648e45cd..ea591450 100644
--- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
+++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
@@ -102,6 +102,7 @@ class LoweringCompilersSpec extends FlatSpec with Matchers {
       new firrtl.transforms.DeadCodeElimination)
     case _: MinimumLowFirrtlOptimization => Seq(
       passes.RemoveValidIf,
+      passes.PadWidths,
       passes.Legalize,
       passes.memlib.VerilogMemDelays, // TODO move to Verilog emitter
       passes.SplitExpressions)
-- 
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