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AgeCommit message (Expand)Author
2016-08-09counter(inc,n) example should reflect actual use (#252)Colin Schmidt
2016-07-31Remove deprecated FileSystemUtilitiesAndrew Waterman
2016-07-31Fix two deprecation warningsAndrew Waterman
2016-07-20Generate better names for nodes (#190)Jack Koenig
2016-07-11bitpat should keep the width of uint (#232)Donggyu
2016-07-07Don't check GCD result before sending it a requestAndrew Waterman
2016-07-07Improve QoR for Log2Andrew Waterman
2016-07-07Improve Fill code generationAndrew Waterman
2016-07-07Correct erroneous Log2 documentationAndrew Waterman
2016-07-07Avoid needlessly creating VecsAndrew Waterman
2016-06-28Merge branch 'master' into renamechisel3Jim Lawson
2016-06-27Guard firrtl stop, fixing pipelined resetAndrew Waterman
2016-06-24Merge branch 'master' into renamechisel3Jim Lawson
2016-06-23Expose FIRRTL stop constructAndrew Waterman
2016-06-22Merge branch 'master' into renamechisel3Jim Lawson
2016-06-20make sure MuxCase and MuxLookup can take all subclasses of Data (#222)Howard Mao
2016-06-20Rename "package", "import", and explicit references to "chisel3".Jim Lawson
2016-06-20Rename chisel3 package.Jim Lawson
2016-06-08Move deprecated debug into compatibilityducky
2016-06-08Package split chisel coreducky
2016-06-08Move chisel/... to chisel/core/..., make chisel/compatibility package/folder,...ducky
2016-06-08Move utils into utilsducky
2016-06-08Add implicit xToLiteral, add Element, use internal package objectducky
2016-06-08Rename Chisel -> chisel in testsducky
2016-06-08Rename packages to lowercase chisel, add compatibility layerducky
2016-06-01Fix a fairly serious bug whereby Vec's could incorrectly compare as equal (#204)Wesley W. Terpstra
2016-05-31Remove unsafe implicit conversions from BitPatducky
2016-05-31Move BitPat out of core/frontend, add implicit conversionDucky
2016-05-26Fix type constraint on PriorityMuxAndrew Waterman
2016-05-20Merge pull request #186 from ucb-bar/sloc_implRichard Lin
2016-05-20Implementation of source locatorsducky
2016-05-20Update BackendCompilationUtilities.verilogToCpp to specify top-modulejackkoenig
2016-05-12remove Tester.scala because chiselMain is now implemented in the chisel-teste...Danny
2016-05-11RegNext and RegInit should match Reg(next=) and Reg(init=)Andrew Waterman
2016-05-10Move emit out of IRducky
2016-05-09remove vpi source filesDonggyu Kim
2016-05-09fix width inference in enumDonggyu Kim
2016-05-09get -> getOrElseDonggyu Kim
2016-05-05Move Chisel API into separate chiselFrontend compilation unit in preparation ...ducky
2016-05-04Multiple assign testerducky
2016-05-04Remove dependences from Chisel core on Chisel utilsAndrew Waterman
2016-05-04Support writing literals like 1.U or -1.SAndrew Waterman
2016-05-04clock|reset to _clock|_reset, added explanatory commentStephen Twigg
2016-05-04Change BlackBox.io.setRef into commentStephen Twigg
2016-05-04Rewrite BlackBox IO contract, replace _clock|_resetStephen Twigg
2016-05-04Add HasId=Module|Data.suggestName, TransitName utilStephen Twigg
2016-05-02more kind assert on chiselMainDonggyu Kim
2016-04-26Replace deprecated usage in tests. Issue #149Jim Lawson
2016-04-26Scalastyle fixes and "ignores". - No functional changes.Jim Lawson
2016-04-18Add whenever method to TblSpec forall to weed out invalid test values.Jim Lawson