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AgeCommit message (Expand)Author
2017-03-08Correct Fill's exception behavior; avoid log2UpAndrew Waterman
2017-02-28Use test_run_dir for more tests. (#534)Jim Lawson
2017-02-27Add test for digit field names in RecordsJack Koenig
2017-02-27Update BetterNamingTests to use NamedModuleTesterJack Koenig
2017-02-24Fix mismatch between Chisel and Firrtl on UInt -& UIntJack Koenig
2017-02-24Test that large Vecs can have widths inferredjackkoenig
2017-02-24Escape % in assertion messagesJack Koenig
2017-02-22Bugfix #513. Fix BPSet width inference in Chisel3 (#523)Adam Izraelevitz
2017-02-16Add support for clock and reset scoping (#509)Jack Koenig
2017-02-15Implement asTypeOf, refactor internal APIs (#450)Richard Lin
2017-02-15Fixed point factory stuff (#505)Chick Markley
2017-02-08Fix random failures in CompatibilitySpec (#498)Jack Koenig
2017-02-08Add Analog typeJack Koenig
2017-02-08Fix up deprecation warnings and clean up CompatibiltySpec code. (#471)Jim Lawson
2017-02-07Fix up Absolute value #abs (#491)Chick Markley
2017-02-07Add generateFirrtl() method to ChiselSpec.scala (#423)Jim Lawson
2017-02-07Name all the thingsducky
2017-02-07Rename SeqMem to SyncReadMem. (#490)Jim Lawson
2017-02-03Added vec IO tests for #104 (#480)Jim Lawson
2017-02-02Revamp VendingMachine.scala as cookbook examplejackkoenig
2017-02-02Bring cookbook up to date with chisel3 APIjackkoenig
2017-02-01Move backend compilation utilities (#400)Jim Lawson
2017-01-31Make Module and Bundle properly use empty namespacesJack
2017-01-31Add compile [to Verilog] to ChiselRunnersJack
2017-01-31Fix spelling of ChiselExecutionSuccessJack
2017-01-31Move blackbox verilog implementations within reach of verilator (#453)Chick Markley
2017-01-30Add shift register with reset (#439)Stevo
2017-01-27Deprecate firrtlToVerilog in favor of compileFirrtlToVerilog (#367)Jack Koenig
2017-01-27Make uselessly public fields in utils privatejackkoenig
2017-01-27Add basic Chisel2 compatibility sanity checks. (#340)Jim Lawson
2017-01-27Provide package-level text to reduce ScalaDoc white space. (#432)Jim Lawson
2017-01-26doesn't lose old firrtl options annotations + transforms (#458)Angie Wang
2017-01-25Better name propagation by macros (#327)Richard Lin
2017-01-20Add Record as new superclass of Bundle (#366)Jack Koenig
2017-01-20Mark Annotation and FixedPoint as experimental (#444)Chick Markley
2017-01-13Make fromBits work with types other than UInt (#424)grebe
2017-01-11Merge branch 'master' into fixedPointFromBitsAdam Izraelevitz
2017-01-10Make stop() immediately end simulation for Verilator tests (#434)Jack Koenig
2016-12-22Merge branch 'master' into fixedPointFromBitsgrebe
2016-12-19Merge branch 'master' into exceptionfixJim Lawson
2016-12-15Merge branch 'master' into fixedPointFromBitsgrebe
2016-12-14Final steps for annotations getting from chisel to firrtl (#405)Chick Markley
2016-12-14Change noenq in ReadyValid to use an uninitialized Wire instead of zero (#364)Jack Koenig
2016-12-13Fix test.Paul Rigge
2016-12-13CheckpointPaul Rigge
2016-12-13Add a test for fromBits on fixed point numbers.Paul Rigge
2016-12-12Add Cookbook examples Reg of Vec and FSM (#404)Jack Koenig
2016-12-07Support for creating chisel annotations that are consumed by firrtl (#393)Chick Markley
2016-12-06utils scaladoc examples for BitPat through CircuitMath (#398)Richard Lin
2016-12-05Merge branch 'master' into exceptionfixJack Koenig
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