diff options
| author | Jack Koenig | 2016-12-14 12:32:04 -0800 |
|---|---|---|
| committer | GitHub | 2016-12-14 12:32:04 -0800 |
| commit | 72e6c884b3f66a379982e5b3efc01afc563275cd (patch) | |
| tree | 86a5dc5cdc031a6bfff8fe0e22a5549e89d587a2 /src | |
| parent | c5b39d05dc723daf4297c7b016de745ce4712460 (diff) | |
Change noenq in ReadyValid to use an uninitialized Wire instead of zero (#364)
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index fcda6943..4a97724a 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -37,12 +37,13 @@ object ReadyValidIO { dat } - /** Indicate no enqueue occurs. Valid is set to false, and all bits are set to zero. + /** Indicate no enqueue occurs. Valid is set to false, and bits are + * connected to an uninitialized wire */ def noenq(): Unit = { target.valid := false.B // We want the type from the following, not any existing binding. - target.bits := target.bits.cloneType.fromBits(0.asUInt) + target.bits := Wire(target.bits.cloneType) } /** Assert ready on this port and return the associated data bits. |
