diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index fcda6943..4a97724a 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -37,12 +37,13 @@ object ReadyValidIO { dat } - /** Indicate no enqueue occurs. Valid is set to false, and all bits are set to zero. + /** Indicate no enqueue occurs. Valid is set to false, and bits are + * connected to an uninitialized wire */ def noenq(): Unit = { target.valid := false.B // We want the type from the following, not any existing binding. - target.bits := target.bits.cloneType.fromBits(0.asUInt) + target.bits := Wire(target.bits.cloneType) } /** Assert ready on this port and return the associated data bits. |