| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-08-30 | Merge branch 'master' into gsdt | Jim Lawson | |
| 2016-08-30 | Make compileOptions in the Chisel package effective. | Jim Lawson | |
| Remove references to the Chisel package in favor of explicit chisel3 imports in tests, | |||
| 2016-08-30 | Explicitly clone the target type in noenq() to avoid "already bound" errors ↵ | Jim Lawson | |
| for io ports. | |||
| 2016-08-30 | Allow compileOptions as optional arguments to elaborate() and emit(). | Jim Lawson | |
| 2016-08-30 | Correct parameter name (topModule) in ScalaDoc. | Jim Lawson | |
| 2016-08-29 | Check module-specific compile options. | Jim Lawson | |
| Import chisel3.NotStrict.CompileOptions in Chisel package. Add CompileOptions tests. | |||
| 2016-08-29 | Rename CompileOptions implicit objects. | Jim Lawson | |
| 2016-08-29 | Pass compileOptions as an implicit Module parameter. | Jim Lawson | |
| 2016-08-25 | fix a bug in setModName | Donggyu Kim | |
| 2016-08-22 | Purely cosmetic changes to placate the scalastyle checker. | Jim Lawson | |
| 2016-08-22 | Fix firrtlDirection for class DeqIO. | Jim Lawson | |
| 2016-08-21 | provides signal name methods for firrtl annotation and chisel testers | Donggyu Kim | |
| * signalName: returns the chirrtl name of the signal * pathName: returns the full path name of the signal from the top module * parentPathName: returns the full path of the signal's parent module instance from the top module * parentModName: returns the signal's parent **module(not instance)** name. | |||
| 2016-08-18 | Merge branch 'sdtwigg_connectwrap_renamechisel3' into gsdt_tests | Jim Lawson | |
| Revive support for firrtl flip direction. Remove compileOptions.internalConnectionToInputOk | |||
| 2016-08-17 | Reduce rocket-chip elaboration errors. | Jim Lawson | |
| 2016-08-16 | Merge branch 'master' into sdtwigg_connectwrap_renamechisel3 | Jim Lawson | |
| 2016-08-15 | Make "def width" a private API; expose isWidthKnown instead (#257) | Andrew Waterman | |
| * Make "def width" a private API; expose isWidthKnown instead Resolves #256. Since width was used to determine whether getWidth would succeed, I added def isWidthKnown: Boolean but another option would be to expose something like def widthOption: Option[Int] ...thoughts? * Document getWidth/isWidthKnown * Add widthOption for more idiomatic Scala manipulation of widths | |||
| 2016-08-11 | Merge branch 'master' into sdtwigg_connectwrap_renamechisel3 | Jim Lawson | |
| 2016-08-09 | Support Module name overrides with "override def desiredName" | Andrew Waterman | |
| The API allowed this before, but not safely, as users could create name conflicts. This exposes the pre-deduplication/sanitization naming API, and closes the other one. | |||
| 2016-08-09 | counter(inc,n) example should reflect actual use (#252) | Colin Schmidt | |
| 2016-08-03 | Merge branch 'master' into sdtwigg_connectwrap_renamechisel3 | Jim Lawson | |
| 2016-08-03 | Merge "package" code into "compatibility". | Jim Lawson | |
| 2016-07-31 | Remove deprecated FileSystemUtilities | Andrew Waterman | |
| This has been deprecated for a long time now (and really shouldn't have existed to begin with). | |||
| 2016-07-31 | Fix two deprecation warnings | Andrew Waterman | |
| 2016-07-28 | Add missing Decoupled object pointer. | Jim Lawson | |
| 2016-07-27 | More compatibility fixes | Jim Lawson | |
| 2016-07-27 | Correct EnqIO/DeqIO Flipped-ness. | Jim Lawson | |
| 2016-07-27 | Additional compatibility code. | Jim Lawson | |
| 2016-07-27 | Correct EnqIO/DeqIO Flipped-ness. | Jim Lawson | |
| 2016-07-27 | Correct EnqIO/DeqIO Flipped-ness. | Jim Lawson | |
| 2016-07-26 | Add ValidIO definition for old code. | Jim Lawson | |
| 2016-07-25 | Minimize differences with master. | Jim Lawson | |
| Remove .Lit(x) usage. Undo "private" scope change. Change "firing" back to "fire". Add package level NODIR definition. | |||
| 2016-07-25 | Merge branch 'master' into sdtwigg_connectwrap_renamechisel3 | Jim Lawson | |
| 2016-07-25 | Use more idiomatic ScalaTest exception expecting code. | Jim Lawson | |
| 2016-07-25 | Add missing compatibility.scala. | Jim Lawson | |
| 2016-07-21 | Introduce chiselCloneType to distinguish from cloneType. | Jim Lawson | |
| Still fails one test - DirectionSpec in Direction.scala | |||
| 2016-07-20 | More literal/width rangling. | Jim Lawson | |
| 2016-07-20 | Distinguish between ?Int.Lit and ?Int.width | Jim Lawson | |
| 2016-07-20 | Compile ok. | Jim Lawson | |
| Need to convert UInt(x) into UInt.Lit(x) or UInt.width(x) | |||
| 2016-07-19 | Incorporate connection logic. | Jim Lawson | |
| Compiles but fails tests. | |||
| 2016-07-19 | Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3 | Jim Lawson | |
| 2016-07-18 | Update Chisel -> chisel3 references. | Jim Lawson | |
| 2016-07-18 | Rename "Chisel" to "chisel3" (only git mv). | Jim Lawson | |
| 2016-07-11 | bitpat should keep the width of uint (#232) | Donggyu | |
| 2016-07-07 | Improve QoR for Log2 | Andrew Waterman | |
| For reasonable circuit delay, need to divide & conquer. | |||
| 2016-07-07 | Improve Fill code generation | Andrew Waterman | |
| 2016-07-07 | Correct erroneous Log2 documentation | Andrew Waterman | |
| 2016-07-07 | Avoid needlessly creating Vecs | Andrew Waterman | |
| 2016-06-28 | Merge branch 'master' into renamechisel3 | Jim Lawson | |
| 2016-06-27 | Guard firrtl stop, fixing pipelined reset | Andrew Waterman | |
| 2016-06-24 | Merge branch 'master' into renamechisel3 | Jim Lawson | |
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index : chiselX | |
| Chisel with SFC compatibility |
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