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authorJim Lawson2016-07-27 09:13:15 -0700
committerJim Lawson2016-07-27 09:13:15 -0700
commitddeff65c1c50f0a7c3604cdc254538fbf1263d4f (patch)
tree2e52f9e5aead33fd42263bc4c9920d2e9db1c3e2 /src/main
parentbdbc554c0ccf490dd75d57c57b171452ac3de14b (diff)
Correct EnqIO/DeqIO Flipped-ness.
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/chisel3/compatibility.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 041553e0..3b613a5e 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -108,10 +108,10 @@ package object Chisel {
type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T]
val DecoupledIO = chisel3.util.DecoupledIO
object EnqIO {
- def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(DecoupledIO(gen))
+ def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen)
}
object DeqIO {
- def apply[T<:Data](gen: T): DecoupledIO[T] = DecoupledIO(gen)
+ def apply[T<:Data](gen: T): DecoupledIO[T] = Flipped(DecoupledIO(gen))
}
type QueueIO[T <: Data] = chisel3.util.QueueIO[T]
type Queue[T <: Data] = chisel3.util.Queue[T]