Reduce rocket-chip elaboration errors.

1 files changed, 4 insertions, 3 deletions

diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index f77a9667..37c28b14 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -25,13 +25,14 @@ object RegInit {
 object RegEnable
 {
   def apply[T <: Data](updateData: T, enable: Bool): T = {
-    val r = Reg(updateData)
-    when (enable) { r := updateData.chiselCloneType }
+    val clonedUpdateData = updateData.chiselCloneType
+    val r = Reg(clonedUpdateData)
+    when (enable) { r := updateData }
     r
   }
   def apply[T <: Data](updateData: T, resetData: T, enable: Bool): T = {
     val r = RegInit(resetData)
-    when (enable) { r := updateData.chiselCloneType }
+    when (enable) { r := updateData }
     r
   }
 }