diff options
| author | Jim Lawson | 2016-07-20 14:49:35 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-07-20 14:49:35 -0700 |
| commit | 2dce378deda1cc33833eb378c89a1c5415817bae (patch) | |
| tree | e3bc5361030d63e017d065491e9e7e4cf788fe3c /src/main | |
| parent | 28e80311f172ae4d1d477e8bb47ca3719c9a8fc5 (diff) | |
Distinguish between ?Int.Lit and ?Int.width
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/chisel3/package.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Arbiter.scala | 12 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/CircuitMath.scala | 4 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Counter.scala | 10 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 4 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/ImplicitConversions.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/OneHot.scala | 4 |
7 files changed, 19 insertions, 19 deletions
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala index 86fce6a2..e43434c0 100644 --- a/src/main/scala/chisel3/package.scala +++ b/src/main/scala/chisel3/package.scala @@ -95,7 +95,7 @@ package object chisel3 { def asSInt(width: Int) = SInt(x, width) } implicit class fromStringToLiteral(val x: String) extends AnyVal { - def U: UInt = UInt(x) + def U: UInt = UInt.Lit(x) } implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal { def B: Bool = Bool(x) diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala index a5397682..44cc88b6 100644 --- a/src/main/scala/chisel3/util/Arbiter.scala +++ b/src/main/scala/chisel3/util/Arbiter.scala @@ -36,7 +36,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo if (count > 1) { val lockCount = Counter(count) val lockIdx = Reg(UInt()) - val locked = lockCount.value =/= UInt(0) + val locked = lockCount.value =/= UInt.Lit(0) val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true)) when (io.out.firing && wantsLock) { @@ -46,7 +46,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo when (locked) { io.chosen := lockIdx } for ((in, (g, i)) <- io.in zip grant.zipWithIndex) - in.ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready + in.ready := Mux(locked, lockIdx === UInt.Lit(i), g) && io.out.ready } else { for ((in, g) <- io.in zip grant) in.ready := g && io.out.ready @@ -66,9 +66,9 @@ class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[ override lazy val choice = Wire(init=UInt(n-1)) for (i <- n-2 to 0 by -1) - when (io.in(i).valid) { choice := UInt(i) } + when (io.in(i).valid) { choice := UInt.Lit(i) } for (i <- n-1 to 1 by -1) - when (validMask(i)) { choice := UInt(i) } + when (validMask(i)) { choice := UInt.Lit(i) } } class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None) @@ -77,7 +77,7 @@ class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T override lazy val choice = Wire(init=UInt(n-1)) for (i <- n-2 to 0 by -1) - when (io.in(i).valid) { choice := UInt(i) } + when (io.in(i).valid) { choice := UInt.Lit(i) } } /** Hardware module that is used to sequence n producers into 1 consumer. @@ -107,7 +107,7 @@ class Arbiter[T <: Data](gen: T, n: Int) extends Module { io.out.bits := io.in(n-1).bits for (i <- n-2 to 0 by -1) { when (io.in(i).valid) { - io.chosen := UInt(i) + io.chosen := UInt.Lit(i) io.out.bits := io.in(i).bits } } diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala index 1174c71c..5e93b009 100644 --- a/src/main/scala/chisel3/util/CircuitMath.scala +++ b/src/main/scala/chisel3/util/CircuitMath.scala @@ -11,12 +11,12 @@ import chisel3._ * An alternative interpretation is it computes the minimum number of bits needed to represent x * @example * {{{ data_out := Log2(data_in) }}} - * @note Truncation is used so Log2(UInt(12412)) = 13*/ + * @note Truncation is used so Log2(UInt.Lit(12412)) = 13*/ object Log2 { /** Compute the Log2 on the least significant n bits of x */ def apply(x: Bits, width: Int): UInt = { if (width < 2) { - UInt(0) + UInt.Lit(0) } else if (width == 2) { x(1) } else { diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala index 40615769..05d8fba8 100644 --- a/src/main/scala/chisel3/util/Counter.scala +++ b/src/main/scala/chisel3/util/Counter.scala @@ -10,17 +10,17 @@ import chisel3._ */ class Counter(val n: Int) { require(n >= 0) - val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt(0) + val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt.Lit(0) /** Increment the counter, returning whether the counter currently is at the * maximum and will wrap. The incremented value is registered and will be * visible on the next cycle. */ def inc(): Bool = { if (n > 1) { - val wrap = value === UInt(n-1) - value := value + UInt(1) + val wrap = value === UInt.Lit(n-1) + value := value + UInt.Lit(1) if (!isPow2(n)) { - when (wrap) { value := UInt(0) } + when (wrap) { value := UInt.Lit(0) } } wrap } else { @@ -33,7 +33,7 @@ class Counter(val n: Int) { * Example Usage: * {{{ val countOn = Bool(true) // increment counter every clock cycle * val myCounter = Counter(countOn, n) - * when ( myCounter.value === UInt(3) ) { ... } }}}*/ + * when ( myCounter.value === UInt.Lit(3) ) { ... } }}}*/ object Counter { def apply(n: Int): Counter = new Counter(n) diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index fb1ee6b9..5958c744 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -153,9 +153,9 @@ extends Module(override_reset=override_reset) { } else { io.count := Mux(ptr_match, Mux(maybe_full, - UInt(entries), UInt(0)), + UInt.Lit(entries), UInt.Lit(0)), Mux(deq_ptr.value > enq_ptr.value, - UInt(entries) + ptr_diff, ptr_diff)) + UInt.Lit(entries) + ptr_diff, ptr_diff)) } } diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala index 4d816a19..3a9089c5 100644 --- a/src/main/scala/chisel3/util/ImplicitConversions.scala +++ b/src/main/scala/chisel3/util/ImplicitConversions.scala @@ -5,6 +5,6 @@ package chisel3.util import chisel3._ object ImplicitConversions { - implicit def intToUInt(x: Int): UInt = UInt(x) + implicit def intToUInt(x: Int): UInt = UInt.Lit(x) implicit def booleanToBool(x: Boolean): Bool = Bool(x) } diff --git a/src/main/scala/chisel3/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala index 820c72d6..8a5caf44 100644 --- a/src/main/scala/chisel3/util/OneHot.scala +++ b/src/main/scala/chisel3/util/OneHot.scala @@ -41,9 +41,9 @@ object UIntToOH { def apply(in: UInt, width: Int = -1): UInt = if (width == -1) { - UInt(1) << in + UInt.Lit(1) << in } else { - (UInt(1) << in(log2Up(width)-1,0))(width-1,0) + (UInt.Lit(1) << in(log2Up(width)-1,0))(width-1,0) } } |
