Minimize differences with master.

Remove .Lit(x) usage.
Undo "private" scope change.
Change "firing" back to "fire".
Add package level NODIR definition.

8 files changed, 31 insertions, 29 deletions

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index b7020b5e..041553e0 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -7,6 +7,7 @@ package object Chisel {
   type Direction = chisel3.core.Direction
   val INPUT = chisel3.core.Direction.Input
   val OUTPUT = chisel3.core.Direction.Output
+  val NODIR = chisel3.core.Direction.Unspecified
   object Flipped {
     def apply[T<:Data](target: T): T = chisel3.core.Flipped[T](target)
   }
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 9a79b109..774455c4 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -95,7 +95,7 @@ package object chisel3 {
     def asSInt(width: Int) = SInt(x, width)
   }
   implicit class fromStringToLiteral(val x: String) extends AnyVal {
-    def U: UInt = UInt.Lit(x)
+    def U: UInt = UInt(x)
   }
   implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal {
     def B: Bool = Bool(x)
@@ -113,5 +113,6 @@ package object chisel3 {
 
   val INPUT = chisel3.core.Direction.Input
   val OUTPUT = chisel3.core.Direction.Output
+  val NODIR = chisel3.core.Direction.Unspecified
   type ChiselException = chisel3.internal.ChiselException
 }
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index 0ece3a0a..5875b3f2 100644
--- a/src/main/scala/chisel3/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -36,17 +36,17 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
   if (count > 1) {
     val lockCount = Counter(count)
     val lockIdx = Reg(UInt())
-    val locked = lockCount.value =/= UInt.Lit(0)
+    val locked = lockCount.value =/= UInt(0)
     val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true))
 
-    when (io.out.firing && wantsLock) {
+    when (io.out.fire() && wantsLock) {
       lockIdx := io.chosen
       lockCount.inc()
     }
 
     when (locked) { io.chosen := lockIdx }
     for ((in, (g, i)) <- io.in zip grant.zipWithIndex)
-      in.ready := Mux(locked, lockIdx === UInt.Lit(i), g) && io.out.ready
+      in.ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready
   } else {
     for ((in, g) <- io.in zip grant)
       in.ready := g && io.out.ready
@@ -55,8 +55,8 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
 
 class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
     extends LockingArbiterLike[T](gen, n, count, needsLock) {
-  lazy val lastGrant = RegEnable(io.chosen, io.out.firing)
-  lazy val grantMask = (0 until n).map(UInt.Lit(_) > lastGrant)
+  lazy val lastGrant = RegEnable(io.chosen, io.out.fire())
+  lazy val grantMask = (0 until n).map(UInt(_) > lastGrant)
   lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g }
 
   override def grant: Seq[Bool] = {
@@ -64,20 +64,20 @@ class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[
     (0 until n).map(i => ctrl(i) && grantMask(i) || ctrl(i + n))
   }
 
-  override lazy val choice = Wire(init=UInt.Lit(n-1))
+  override lazy val choice = Wire(init=UInt(n-1))
   for (i <- n-2 to 0 by -1)
-    when (io.in(i).valid) { choice := UInt.Lit(i) }
+    when (io.in(i).valid) { choice := UInt(i) }
   for (i <- n-1 to 1 by -1)
-    when (validMask(i)) { choice := UInt.Lit(i) }
+    when (validMask(i)) { choice := UInt(i) }
 }
 
 class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
     extends LockingArbiterLike[T](gen, n, count, needsLock) {
   def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid))
 
-  override lazy val choice = Wire(init=UInt.Lit(n-1))
+  override lazy val choice = Wire(init=UInt(n-1))
   for (i <- n-2 to 0 by -1)
-    when (io.in(i).valid) { choice := UInt.Lit(i) }
+    when (io.in(i).valid) { choice := UInt(i) }
 }
 
 /** Hardware module that is used to sequence n producers into 1 consumer.
@@ -103,11 +103,11 @@ class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1)
 class Arbiter[T <: Data](gen: T, n: Int) extends Module {
   val io = IO(new ArbiterIO(gen, n))
 
-  io.chosen := UInt.Lit(n-1)
+  io.chosen := UInt(n-1)
   io.out.bits := io.in(n-1).bits
   for (i <- n-2 to 0 by -1) {
     when (io.in(i).valid) {
-      io.chosen := UInt.Lit(i)
+      io.chosen := UInt(i)
       io.out.bits := io.in(i).bits
     }
   }
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index 27bd7bfb..c809e14b 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -16,11 +16,11 @@ object Log2 {
   /** Compute the Log2 on the least significant n bits of x */
   def apply(x: Bits, width: Int): UInt = {
     if (width < 2) {
-      UInt.Lit(0)
+      UInt(0)
     } else if (width == 2) {
       x(1)
     } else if (width <= divideAndConquerThreshold) {
-      Mux(x(width-1), UInt.Lit(width-1), apply(x, width-1))
+      Mux(x(width-1), UInt(width-1), apply(x, width-1))
     } else {
       val mid = 1 << (log2Ceil(width) - 1)
       val hi = x(width-1, mid)
diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index 05d8fba8..40615769 100644
--- a/src/main/scala/chisel3/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -10,17 +10,17 @@ import chisel3._
   */
 class Counter(val n: Int) {
   require(n >= 0)
-  val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt.Lit(0)
+  val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt(0)
   /** Increment the counter, returning whether the counter currently is at the
     * maximum and will wrap. The incremented value is registered and will be
     * visible on the next cycle.
     */
   def inc(): Bool = {
     if (n > 1) {
-      val wrap = value === UInt.Lit(n-1)
-      value := value + UInt.Lit(1)
+      val wrap = value === UInt(n-1)
+      value := value + UInt(1)
       if (!isPow2(n)) {
-        when (wrap) { value := UInt.Lit(0) }
+        when (wrap) { value := UInt(0) }
       }
       wrap
     } else {
@@ -33,7 +33,7 @@ class Counter(val n: Int) {
   * Example Usage:
   * {{{ val countOn = Bool(true) // increment counter every clock cycle
   * val myCounter = Counter(countOn, n)
-  * when ( myCounter.value === UInt.Lit(3) ) { ... } }}}*/
+  * when ( myCounter.value === UInt(3) ) { ... } }}}*/
 object Counter
 {
   def apply(n: Int): Counter = new Counter(n)
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 76bf4842..68c3ae88 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -23,7 +23,7 @@ object DecoupledIO {
   def apply[T <: Data](gen: T): DecoupledIO[T] = new DecoupledIO(gen)
 
   implicit class AddMethodsToDecoupled[T<:Data](val target: DecoupledIO[T]) extends AnyVal {
-    def firing: Bool = target.ready && target.valid
+    def fire(): Bool = target.ready && target.valid
 
     /** push dat onto the output bits of this interface to let the consumer know it has happened.
       * @param dat the values to assign to bits.
@@ -114,8 +114,8 @@ extends Module(override_reset=override_reset) {
   val ptr_match = enq_ptr.value === deq_ptr.value
   val empty = ptr_match && !maybe_full
   val full = ptr_match && maybe_full
-  val do_enq = Wire(init=io.enq.firing)
-  val do_deq = Wire(init=io.deq.firing)
+  val do_enq = Wire(init=io.enq.fire())
+  val do_deq = Wire(init=io.deq.fire())
 
   when (do_enq) {
     ram(enq_ptr.value) := io.enq.bits
@@ -151,9 +151,9 @@ extends Module(override_reset=override_reset) {
   } else {
     io.count := Mux(ptr_match,
                     Mux(maybe_full,
-                      UInt.Lit(entries), UInt.Lit(0)),
+                      UInt(entries), UInt(0)),
                     Mux(deq_ptr.value > enq_ptr.value,
-                      UInt.Lit(entries) + ptr_diff, ptr_diff))
+                      UInt(entries) + ptr_diff, ptr_diff))
   }
 }
 
diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
index 3a9089c5..4d816a19 100644
--- a/src/main/scala/chisel3/util/ImplicitConversions.scala
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
@@ -5,6 +5,6 @@ package chisel3.util
 import chisel3._
 
 object ImplicitConversions {
-  implicit def intToUInt(x: Int): UInt = UInt.Lit(x)
+  implicit def intToUInt(x: Int): UInt = UInt(x)
   implicit def booleanToBool(x: Boolean): Bool = Bool(x)
 }
diff --git a/src/main/scala/chisel3/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala
index 49661115..abede61e 100644
--- a/src/main/scala/chisel3/util/OneHot.scala
+++ b/src/main/scala/chisel3/util/OneHot.scala
@@ -31,7 +31,7 @@ object OHToUInt {
   * @example {{{ data_out := PriorityEncoder(data_in) }}}
   */
 object PriorityEncoder {
-  def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt.Lit(_)))
+  def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt(_)))
   def apply(in: Bits): UInt = apply(in.toBools)
 }
 
@@ -41,9 +41,9 @@ object UIntToOH
 {
   def apply(in: UInt, width: Int = -1): UInt =
     if (width == -1) {
-      UInt.Lit(1) << in
+      UInt(1) << in
     } else {
-      (UInt.Lit(1) << in(log2Up(width)-1,0))(width-1,0)
+      (UInt(1) << in(log2Up(width)-1,0))(width-1,0)
     }
 }