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AgeCommit message (Expand)Author
2019-07-18Add width utility functions to avoid incorrect usage of bare log2Ceil(). (#819)Jim Lawson
2019-06-11Added documentation to Decoupled, Conditionals, Counter (#1015)Adam Izraelevitz
2019-05-22Make Driver a ChiselStage compatibility layerSchuyler Eldridge
2019-05-22Add toAnnotations method to ChiselExecutionOptionsSchuyler Eldridge
2019-05-22Add Driver Compatibility LayerSchuyler Eldridge
2019-05-22Add chisel3.stage.ChiselStageSchuyler Eldridge
2019-05-22Add chisel3.stage.phases.MaybeFirrtlStageSchuyler Eldridge
2019-05-22Add stage.phases.AddImplicitOutputAnnotationFileSchuyler Eldridge
2019-05-22Add chisel.stage.phases.AddImplicitOutputFileSchuyler Eldridge
2019-05-22Add chisel3.stage.phases.Emitter PhaseSchuyler Eldridge
2019-05-22Add chisel3.stage.phases.Convert PhaseSchuyler Eldridge
2019-05-22Add chisel3.stage.phases.Elaborate PhaseSchuyler Eldridge
2019-05-22Add chisel3.stage.phases.Checks PhaseSchuyler Eldridge
2019-05-22Add ChiselOptionsViewSchuyler Eldridge
2019-05-22Add chisel3.stage.ChiselOptionsSchuyler Eldridge
2019-05-22Add chisel3.stage.ChiselCliSchuyler Eldridge
2019-05-22Add chisel3.stage AnnotationsSchuyler Eldridge
2019-05-20Repackagecore rebase (#1078)Jim Lawson
2019-05-13Fix miscellaneous Scaladoc warningsSchuyler Eldridge
2019-05-12Cleanup loadMemoryFromFile documentationSchuyler Eldridge
2019-05-10Change LFSR16 deprecation from 3.3 -> 3.2Schuyler Eldridge
2019-05-10Fix LFSR regressionAndrew Waterman
2019-05-09PRNG state UInt->Vec[Bool], make async reset safeSchuyler Eldridge
2019-05-09Deprecate LFSR16, use FibonacciLFSR internallySchuyler Eldridge
2019-05-09Add chisel3.util.random lib w/ LFSR generatorSchuyler Eldridge
2019-05-05Expand upon ScalaDoc in Driveredwardcwang
2019-04-26Bundle literals implementation (#1057)Richard Lin
2019-04-15Avoid silently truncating BigInt to IntAndrew Waterman
2019-03-23move doNotDedup to experimental (#1008)Sequencer
2019-03-21Remove @chiselName from MixedVec (#1045)Richard Lin
2019-03-18Split #974 into two PRs - scalastyle updates (#1037)Jim Lawson
2019-03-15Use TransitName for improved Pipe naming (#1024)Schuyler Eldridge
2019-03-14Decouple implementation details from LoadMemoryAnnotation. (#1034)Jim Lawson
2019-03-11ScalaDocs improvement for utils Math, MixedVec (#1019)Richard Lin
2019-02-25Docs for ListLookup (#1028)Richard Lin
2019-02-19Add HasBlackBoxPath to BlackBoxUtils.scala (#903)Albert Chen
2019-02-19ScalaDoc for Mux (examples added) (#1014)Martin Schoeberl
2019-02-19Add Scaladoc for chisel3.util.TransitNameSchuyler Eldridge
2019-02-19Mainline Chisel multi-clock functionality (#1013)edwardcwang
2019-02-19Util doc lsfr (#1021)Chick Markley
2019-02-19Documentation for Reg utilities (#1018)Martin Schoeberl
2019-02-19ScalaDoc for OneHot (#1016)Martin Schoeberl
2019-02-18Add requirement that Pipe latency >= 0Schuyler Eldridge
2019-02-18Add Scaladoc for chisel3.util.PipeSchuyler Eldridge
2019-02-18Add Scaldoc for chisel3.util.ValidSchuyler Eldridge
2019-01-25WireDefault instead of WireInit, keep WireInit around (#986)Martin Schoeberl
2019-01-22Changes to BoringUtils Scaladoc, paramater nameSchuyler Eldridge
2019-01-22Fix BoringUtils deduplication bugSchuyler Eldridge
2019-01-22Add Rocket Chip-style clonemodule as CloneModuleAsRecord to experimental (#943)Albert Magyar
2019-01-21Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) M...Richard Lin
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