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authorSchuyler Eldridge2019-01-14 11:59:48 -0500
committerSchuyler Eldridge2019-05-22 16:17:17 -0400
commit20ba486ab1988e57e2b2ca163c9c83e1d8904bba (patch)
tree3956ff9443b4f566844862579e5a441b096e07cb /src/main
parent325e48809587fdf47d398578a1d94f856ab1f275 (diff)
Add chisel3.stage.phases.Emitter Phase
This adds an Emitter Phase that writes a ChiselCircuitAnnotation to a file if a ChiselOutputFileAnnotation is present. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/chisel3/stage/phases/Emitter.scala44
1 files changed, 44 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/stage/phases/Emitter.scala b/src/main/scala/chisel3/stage/phases/Emitter.scala
new file mode 100644
index 00000000..1bdb9f8d
--- /dev/null
+++ b/src/main/scala/chisel3/stage/phases/Emitter.scala
@@ -0,0 +1,44 @@
+// See LICENSE for license details.
+
+package chisel3.stage.phases
+
+import firrtl.{AnnotationSeq, EmittedFirrtlCircuit, EmittedFirrtlCircuitAnnotation}
+import firrtl.annotations.DeletedAnnotation
+import firrtl.options.{Phase, StageOptions}
+import firrtl.options.Viewer.view
+
+import chisel3.internal.firrtl.{Emitter => OldEmitter}
+import chisel3.stage.{ChiselCircuitAnnotation, ChiselOptions}
+
+import java.io.{File, FileWriter}
+
+/** Emit a [[chisel3.stage.ChiselCircuitAnnotation]] to a file if a [[chisel3.stage.ChiselOutputFileAnnotation]] is
+ * present. A deleted [[firrtl.EmittedFirrtlCircuitAnnotation]] is added.
+ *
+ * @todo This should be switched to support correct emission of multiple circuits to multiple files. The API should
+ * likely mirror how the [[firrtl.stage.phases.Compiler]] parses annotations into "global" annotations and
+ * left-associative per-circuit annotations.
+ * @todo The use of the deleted [[firrtl.EmittedFirrtlCircuitAnnotation]] is a kludge to provide some breadcrumbs such
+ * that the emitted CHIRRTL can be provided back to the old Driver. This should be removed or a better solution
+ * developed.
+ */
+class Emitter extends Phase {
+
+ def transform(annotations: AnnotationSeq): AnnotationSeq = {
+ val copts = view[ChiselOptions](annotations)
+ val sopts = view[StageOptions](annotations)
+
+ annotations.flatMap {
+ case a: ChiselCircuitAnnotation if copts.outputFile.isDefined =>
+ val file = new File(sopts.getBuildFileName(copts.outputFile.get, Some(".fir")))
+ val emitted = OldEmitter.emit(a.circuit)
+ val w = new FileWriter(file)
+ w.write(emitted)
+ w.close()
+ val anno = EmittedFirrtlCircuitAnnotation(EmittedFirrtlCircuit(a.circuit.name, emitted, ".fir"))
+ Seq(DeletedAnnotation(name, anno), a)
+ case a => Some(a)
+ }
+ }
+
+}