From 20ba486ab1988e57e2b2ca163c9c83e1d8904bba Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Mon, 14 Jan 2019 11:59:48 -0500 Subject: Add chisel3.stage.phases.Emitter Phase This adds an Emitter Phase that writes a ChiselCircuitAnnotation to a file if a ChiselOutputFileAnnotation is present. Signed-off-by: Schuyler Eldridge --- src/main/scala/chisel3/stage/phases/Emitter.scala | 44 +++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 src/main/scala/chisel3/stage/phases/Emitter.scala (limited to 'src/main') diff --git a/src/main/scala/chisel3/stage/phases/Emitter.scala b/src/main/scala/chisel3/stage/phases/Emitter.scala new file mode 100644 index 00000000..1bdb9f8d --- /dev/null +++ b/src/main/scala/chisel3/stage/phases/Emitter.scala @@ -0,0 +1,44 @@ +// See LICENSE for license details. + +package chisel3.stage.phases + +import firrtl.{AnnotationSeq, EmittedFirrtlCircuit, EmittedFirrtlCircuitAnnotation} +import firrtl.annotations.DeletedAnnotation +import firrtl.options.{Phase, StageOptions} +import firrtl.options.Viewer.view + +import chisel3.internal.firrtl.{Emitter => OldEmitter} +import chisel3.stage.{ChiselCircuitAnnotation, ChiselOptions} + +import java.io.{File, FileWriter} + +/** Emit a [[chisel3.stage.ChiselCircuitAnnotation]] to a file if a [[chisel3.stage.ChiselOutputFileAnnotation]] is + * present. A deleted [[firrtl.EmittedFirrtlCircuitAnnotation]] is added. + * + * @todo This should be switched to support correct emission of multiple circuits to multiple files. The API should + * likely mirror how the [[firrtl.stage.phases.Compiler]] parses annotations into "global" annotations and + * left-associative per-circuit annotations. + * @todo The use of the deleted [[firrtl.EmittedFirrtlCircuitAnnotation]] is a kludge to provide some breadcrumbs such + * that the emitted CHIRRTL can be provided back to the old Driver. This should be removed or a better solution + * developed. + */ +class Emitter extends Phase { + + def transform(annotations: AnnotationSeq): AnnotationSeq = { + val copts = view[ChiselOptions](annotations) + val sopts = view[StageOptions](annotations) + + annotations.flatMap { + case a: ChiselCircuitAnnotation if copts.outputFile.isDefined => + val file = new File(sopts.getBuildFileName(copts.outputFile.get, Some(".fir"))) + val emitted = OldEmitter.emit(a.circuit) + val w = new FileWriter(file) + w.write(emitted) + w.close() + val anno = EmittedFirrtlCircuitAnnotation(EmittedFirrtlCircuit(a.circuit.name, emitted, ".fir")) + Seq(DeletedAnnotation(name, anno), a) + case a => Some(a) + } + } + +} -- cgit v1.2.3