Fix miscellaneous Scaladoc warnings

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

4 files changed, 5 insertions, 5 deletions

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index d0f6f6bd..9071491b 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -151,7 +151,7 @@ object Driver extends BackendCompilationUtilities {
     * Emit the annotations of a circuit
     *
     * @param ir The circuit containing annotations to be emitted
-    * @param optName An optional filename (will use s"${ir.name}.json" otherwise)
+    * @param optName An optional filename (will use s"\${ir.name}.json" otherwise)
     */
   def dumpAnnotations(ir: Circuit, optName: Option[File]): File = {
     val f = optName.getOrElse(new File(ir.name + ".anno.json"))
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 4ba762b5..c6458b9d 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -61,7 +61,7 @@ class Valid[+T <: Data](gen: T) extends Bundle {
   * }}}
   *
   * In addition to adding the `valid` bit, a [[Valid.fire]] method is also added that returns the `valid` bit. This
-  * provides a similarly named interface to [[DecoupledIO.fire]].
+  * provides a similarly named interface to [[DecoupledIO]]'s fire.
   *
   * @see [[Decoupled$ DecoupledIO Factory]]
   * @see [[Irrevocable$ IrrevocableIO Factory]]
diff --git a/src/main/scala/chisel3/util/experimental/BoringUtils.scala b/src/main/scala/chisel3/util/experimental/BoringUtils.scala
index 67a6b6d0..a6f2d52a 100644
--- a/src/main/scala/chisel3/util/experimental/BoringUtils.scala
+++ b/src/main/scala/chisel3/util/experimental/BoringUtils.scala
@@ -18,7 +18,7 @@ import chisel3.internal.Namespace
 class BoringUtilsException(message: String) extends Exception(message)
 
 /** Utilities for generating synthesizable cross module references that "bore" through the hierarchy. The underlying
-  * cross module connects are handled by FIRRTL's Wiring Transform ([[firrtl.passes.wiring.WiringTransform]]).
+  * cross module connects are handled by FIRRTL's Wiring Transform.
   *
   * Consider the following exmple where you want to connect a component in one module to a component in another. Module
   * `Constant` has a wire tied to `42` and `Expect` will assert unless connected to `42`:
diff --git a/src/main/scala/chisel3/util/experimental/Inline.scala b/src/main/scala/chisel3/util/experimental/Inline.scala
index 8ec5219b..753c36af 100644
--- a/src/main/scala/chisel3/util/experimental/Inline.scala
+++ b/src/main/scala/chisel3/util/experimental/Inline.scala
@@ -28,8 +28,8 @@ import firrtl.annotations.{CircuitName, ModuleName, ComponentName, Annotation}
   * class Bar extends Module with Internals with HasSub
   * /* The resulting instances will be:
   *  - Top
-  *  - Top.x$sub
-  *  - Top.y$sub
+  *  - Top.x\$sub
+  *  - Top.y\$sub
   *  - Top.z
   *  - Top.z.sub */
   * class Top extends Module with Internals {