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2016-07-27Correct EnqIO/DeqIO Flipped-ness.Jim Lawson
2016-07-27Additional compatibility code.Jim Lawson
2016-07-27Correct EnqIO/DeqIO Flipped-ness.Jim Lawson
2016-07-27Correct EnqIO/DeqIO Flipped-ness.Jim Lawson
2016-07-26Add ValidIO definition for old code.Jim Lawson
2016-07-25Minimize differences with master.Jim Lawson
Remove .Lit(x) usage. Undo "private" scope change. Change "firing" back to "fire". Add package level NODIR definition.
2016-07-25Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-07-25Use more idiomatic ScalaTest exception expecting code.Jim Lawson
2016-07-25Add missing compatibility.scala.Jim Lawson
2016-07-21Introduce chiselCloneType to distinguish from cloneType.Jim Lawson
Still fails one test - DirectionSpec in Direction.scala
2016-07-20More literal/width rangling.Jim Lawson
2016-07-20Distinguish between ?Int.Lit and ?Int.widthJim Lawson
2016-07-20Compile ok.Jim Lawson
Need to convert UInt(x) into UInt.Lit(x) or UInt.width(x)
2016-07-19Incorporate connection logic.Jim Lawson
Compiles but fails tests.
2016-07-19Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3Jim Lawson
2016-07-18Update Chisel -> chisel3 references.Jim Lawson
2016-07-18Rename "Chisel" to "chisel3" (only git mv).Jim Lawson
2016-07-11bitpat should keep the width of uint (#232)Donggyu
2016-07-07Improve QoR for Log2Andrew Waterman
For reasonable circuit delay, need to divide & conquer.
2016-07-07Improve Fill code generationAndrew Waterman
2016-07-07Correct erroneous Log2 documentationAndrew Waterman
2016-07-07Avoid needlessly creating VecsAndrew Waterman
2016-06-28Merge branch 'master' into renamechisel3Jim Lawson
2016-06-27Guard firrtl stop, fixing pipelined resetAndrew Waterman
2016-06-24Merge branch 'master' into renamechisel3Jim Lawson
2016-06-23Expose FIRRTL stop constructAndrew Waterman
2016-06-22Merge branch 'master' into renamechisel3Jim Lawson
2016-06-21Most of the remaining tests with Module, IO wrapping.Jim Lawson
2016-06-21New Module, IO, Input/Output wrapping.Jim Lawson
2016-06-20make sure MuxCase and MuxLookup can take all subclasses of Data (#222)Howard Mao
2016-06-20Rename "package", "import", and explicit references to "chisel3".Jim Lawson
2016-06-20Rename chisel3 package.Jim Lawson
2016-06-08Move deprecated debug into compatibilityducky
2016-06-08Package split chisel coreducky
2016-06-08Move chisel/... to chisel/core/..., make chisel/compatibility ↵ducky
package/folder, move more things into utils
2016-06-08Move utils into utilsducky
2016-06-08Add implicit xToLiteral, add Element, use internal package objectducky
2016-06-08Rename packages to lowercase chisel, add compatibility layerducky
2016-05-31Remove unsafe implicit conversions from BitPatducky
2016-05-31Move BitPat out of core/frontend, add implicit conversionDucky
2016-05-26Fix type constraint on PriorityMuxAndrew Waterman
2016-05-20Merge pull request #186 from ucb-bar/sloc_implRichard Lin
Source locators
2016-05-20Implementation of source locatorsducky
2016-05-20Update BackendCompilationUtilities.verilogToCpp to specify top-modulejackkoenig
This prevents Verilator from erroring when it cannot determine the top-module. It also changes the PRINTF_COND guard to correctly use the top-level reset instead of just the top of the Chisel-generated code.
2016-05-12remove Tester.scala because chiselMain is now implemented in the ↵Danny
chisel-testers repo
2016-05-11RegNext and RegInit should match Reg(next=) and Reg(init=)Andrew Waterman
2016-05-10Move emit out of IRducky
2016-05-09remove vpi source filesDonggyu Kim
2016-05-09fix width inference in enumDonggyu Kim
2016-05-09get -> getOrElseDonggyu Kim
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