Move utils into utils

17 files changed, 103 insertions, 72 deletions

diff --git a/src/main/scala/chisel/compatibility.scala b/src/main/scala/chisel/compatibility.scala
index fd45987b..9cdef80d 100644
--- a/src/main/scala/chisel/compatibility.scala
+++ b/src/main/scala/chisel/compatibility.scala
@@ -71,80 +71,80 @@ package object Chisel {
   }
 
 
-  val log2Up = chisel.log2Up
-  val log2Ceil = chisel.log2Ceil
-  val log2Down = chisel.log2Down
-  val log2Floor = chisel.log2Floor
-  val isPow2 = chisel.isPow2
+  val log2Up = chisel.util.log2Up
+  val log2Ceil = chisel.util.log2Ceil
+  val log2Down = chisel.util.log2Down
+  val log2Floor = chisel.util.log2Floor
+  val isPow2 = chisel.util.isPow2
 
-  type ArbiterIO[T <: Data] = chisel.ArbiterIO[T]
-  type LockingArbiterLike[T <: Data] = chisel.LockingArbiterLike[T]
-  type LockingRRArbiter[T <: Data] = chisel.LockingRRArbiter[T]
-  type LockingArbiter[T <: Data] = chisel.LockingArbiter[T]
-  type RRArbiter[T <: Data] = chisel.RRArbiter[T]
-  type Arbiter[T <: Data] = chisel.Arbiter[T]
+  type ArbiterIO[T <: Data] = chisel.util.ArbiterIO[T]
+  type LockingArbiterLike[T <: Data] = chisel.util.LockingArbiterLike[T]
+  type LockingRRArbiter[T <: Data] = chisel.util.LockingRRArbiter[T]
+  type LockingArbiter[T <: Data] = chisel.util.LockingArbiter[T]
+  type RRArbiter[T <: Data] = chisel.util.RRArbiter[T]
+  type Arbiter[T <: Data] = chisel.util.Arbiter[T]
 
-  val FillInterleaved = chisel.FillInterleaved
-  val PopCount = chisel.PopCount
-  val Fill = chisel.Fill
-  val Reverse = chisel.Reverse
+  val FillInterleaved = chisel.util.FillInterleaved
+  val PopCount = chisel.util.PopCount
+  val Fill = chisel.util.Fill
+  val Reverse = chisel.util.Reverse
 
-  val Cat = chisel.Cat
+  val Cat = chisel.util.Cat
 
-  val Log2 = chisel.Log2
+  val Log2 = chisel.util.Log2
 
-  val unless = chisel.unless
-  type SwitchContext[T <: Bits] = chisel.SwitchContext[T]
-  val is = chisel.is
-  val switch = chisel.switch
+  val unless = chisel.util.unless
+  type SwitchContext[T <: Bits] = chisel.util.SwitchContext[T]
+  val is = chisel.util.is
+  val switch = chisel.util.switch
 
-  type Counter = chisel.Counter
-  val Counter = chisel.Counter
+  type Counter = chisel.util.Counter
+  val Counter = chisel.util.Counter
 
-  type DecoupledIO[+T <: Data] = chisel.DecoupledIO[T]
-  val Decoupled = chisel.Decoupled
-  type EnqIO[T <: Data] = chisel.EnqIO[T]
-  type DeqIO[T <: Data] = chisel.DeqIO[T]
-  type DecoupledIOC[+T <: Data] = chisel.DecoupledIOC[T]
-  type QueueIO[T <: Data] = chisel.QueueIO[T]
-  type Queue[T <: Data] = chisel.Queue[T]
-  val Queue = chisel.Queue
+  type DecoupledIO[+T <: Data] = chisel.util.DecoupledIO[T]
+  val Decoupled = chisel.util.Decoupled
+  type EnqIO[T <: Data] = chisel.util.EnqIO[T]
+  type DeqIO[T <: Data] = chisel.util.DeqIO[T]
+  type DecoupledIOC[+T <: Data] = chisel.util.DecoupledIOC[T]
+  type QueueIO[T <: Data] = chisel.util.QueueIO[T]
+  type Queue[T <: Data] = chisel.util.Queue[T]
+  val Queue = chisel.util.Queue
 
-  val Enum = chisel.Enum
+  val Enum = chisel.util.Enum
 
-  val LFSR16 = chisel.LFSR16
+  val LFSR16 = chisel.util.LFSR16
 
-  val ListLookup = chisel.ListLookup
-  val Lookup = chisel.Lookup
+  val ListLookup = chisel.util.ListLookup
+  val Lookup = chisel.util.Lookup
 
-  val Mux1H = chisel.Mux1H
-  val PriorityMux = chisel.PriorityMux
-  val MuxLookup = chisel.MuxLookup
-  val MuxCase = chisel.MuxCase
+  val Mux1H = chisel.util.Mux1H
+  val PriorityMux = chisel.util.PriorityMux
+  val MuxLookup = chisel.util.MuxLookup
+  val MuxCase = chisel.util.MuxCase
 
-  val OHToUInt = chisel.OHToUInt
-  val PriorityEncoder = chisel.PriorityEncoder
-  val UIntToOH = chisel.UIntToOH
-  val PriorityEncoderOH = chisel.PriorityEncoderOH
+  val OHToUInt = chisel.util.OHToUInt
+  val PriorityEncoder = chisel.util.PriorityEncoder
+  val UIntToOH = chisel.util.UIntToOH
+  val PriorityEncoderOH = chisel.util.PriorityEncoderOH
 
-  val RegNext = chisel.RegNext
-  val RegInit = chisel.RegInit
-  val RegEnable = chisel.RegEnable
-  val ShiftRegister = chisel.ShiftRegister
+  val RegNext = chisel.util.RegNext
+  val RegInit = chisel.util.RegInit
+  val RegEnable = chisel.util.RegEnable
+  val ShiftRegister = chisel.util.ShiftRegister
 
-  type ValidIO[+T <: Data] = chisel.ValidIO[T]
-  val Valid = chisel.Valid
-  val Pipe = chisel.Pipe
-  type Pipe[T <: Data] = chisel.Pipe[T]
+  type ValidIO[+T <: Data] = chisel.util.ValidIO[T]
+  val Valid = chisel.util.Valid
+  val Pipe = chisel.util.Pipe
+  type Pipe[T <: Data] = chisel.util.Pipe[T]
 
 
   import chisel.internal.firrtl.Width
-  implicit def fromBigIntToLiteral(x: BigInt): chisel.fromBigIntToLiteral = 
+  implicit def fromBigIntToLiteral(x: BigInt): chisel.fromBigIntToLiteral =
     new chisel.fromBigIntToLiteral(x)
-  implicit def fromIntToLiteral(x: Int): chisel.fromIntToLiteral= 
+  implicit def fromIntToLiteral(x: Int): chisel.fromIntToLiteral=
     new chisel.fromIntToLiteral(x)
-  implicit def fromStringToLiteral(x: String): chisel.fromStringToLiteral= 
+  implicit def fromStringToLiteral(x: String): chisel.fromStringToLiteral=
     new chisel.fromStringToLiteral(x)
-  implicit def fromBooleanToLiteral(x: Boolean): chisel.fromBooleanToLiteral= 
+  implicit def fromBooleanToLiteral(x: Boolean): chisel.fromBooleanToLiteral=
     new chisel.fromBooleanToLiteral(x)
 }
diff --git a/src/main/scala/chisel/util/Arbiter.scala b/src/main/scala/chisel/util/Arbiter.scala
index afe48963..3723f2a9 100644
--- a/src/main/scala/chisel/util/Arbiter.scala
+++ b/src/main/scala/chisel/util/Arbiter.scala
@@ -3,7 +3,9 @@
 /** Arbiters in all shapes and sizes.
   */
 
-package chisel
+package chisel.util
+
+import chisel._
 
 /** An I/O bundle for the Arbiter */
 class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
diff --git a/src/main/scala/chisel/util/Bitwise.scala b/src/main/scala/chisel/util/Bitwise.scala
index 27064059..94413fc7 100644
--- a/src/main/scala/chisel/util/Bitwise.scala
+++ b/src/main/scala/chisel/util/Bitwise.scala
@@ -3,7 +3,9 @@
 /** Miscellaneous circuit generators operating on bits.
   */
 
-package chisel
+package chisel.util
+
+import chisel._
 
 object FillInterleaved
 {
diff --git a/src/main/scala/chisel/util/Cat.scala b/src/main/scala/chisel/util/Cat.scala
index a35619df..5b3c613e 100644
--- a/src/main/scala/chisel/util/Cat.scala
+++ b/src/main/scala/chisel/util/Cat.scala
@@ -1,6 +1,8 @@
 // See LICENSE for license details.
 
-package chisel
+package chisel.util
+
+import chisel._
 
 object Cat {
   /** Combine data elements together
diff --git a/src/main/scala/chisel/util/CircuitMath.scala b/src/main/scala/chisel/util/CircuitMath.scala
index 001be802..c3b94fdb 100644
--- a/src/main/scala/chisel/util/CircuitMath.scala
+++ b/src/main/scala/chisel/util/CircuitMath.scala
@@ -3,7 +3,9 @@
 /** Circuit-land math operations.
   */
 
-package chisel
+package chisel.util
+
+import chisel._
 
 /** Compute Log2 with truncation of a UInt in hardware using a Mux Tree
   * An alternative interpretation is it computes the minimum number of bits needed to represent x
diff --git a/src/main/scala/chisel/util/Conditional.scala b/src/main/scala/chisel/util/Conditional.scala
index 94f00080..01c12799 100644
--- a/src/main/scala/chisel/util/Conditional.scala
+++ b/src/main/scala/chisel/util/Conditional.scala
@@ -3,13 +3,15 @@
 /** Conditional blocks.
   */
 
-package chisel
+package chisel.util
 
 import scala.language.reflectiveCalls
 import scala.language.experimental.macros
 import scala.reflect.runtime.universe._
 import scala.reflect.macros.blackbox._
 
+import chisel._
+
 /** This is identical to [[Chisel.when when]] with the condition inverted */
 object unless {  // scalastyle:ignore object.name
   def apply(c: Bool)(block: => Unit) {
@@ -61,7 +63,7 @@ object switch {  // scalastyle:ignore object.name
     def extractIsStatement(tree: Tree): List[c.universe.Tree] = tree match {
       // TODO: remove when Chisel compatibility package is removed
       case q"Chisel.`package`.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
-      case q"chisel.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
+      case q"chisel.util.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
       case b => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.")
     }
     val q"..$body" = x
diff --git a/src/main/scala/chisel/util/Counter.scala b/src/main/scala/chisel/util/Counter.scala
index dde1e347..1c0b0203 100644
--- a/src/main/scala/chisel/util/Counter.scala
+++ b/src/main/scala/chisel/util/Counter.scala
@@ -1,6 +1,8 @@
 // See LICENSE for license details.
 
-package chisel
+package chisel.util
+
+import chisel._
 
 /** A counter module
   * @param n number of counts before the counter resets (or one more than the
diff --git a/src/main/scala/chisel/util/Decoupled.scala b/src/main/scala/chisel/util/Decoupled.scala
index 955b0870..89b0e39d 100644
--- a/src/main/scala/chisel/util/Decoupled.scala
+++ b/src/main/scala/chisel/util/Decoupled.scala
@@ -3,7 +3,9 @@
 /** Wrappers for ready-valid (Decoupled) interfaces and associated circuit generators using them.
   */
 
-package chisel
+package chisel.util
+
+import chisel._
 
 /** An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'*/
 class DecoupledIO[+T <: Data](gen: T) extends Bundle
diff --git a/src/main/scala/chisel/util/Enum.scala b/src/main/scala/chisel/util/Enum.scala
index 2757a06c..8babcd23 100644
--- a/src/main/scala/chisel/util/Enum.scala
+++ b/src/main/scala/chisel/util/Enum.scala
@@ -3,7 +3,9 @@
 /** Enum generators, allowing circuit constants to have more meaningful names.
   */
 
-package chisel
+package chisel.util
+
+import chisel._
 
 object Enum {
   /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */
diff --git a/src/main/scala/chisel/util/LFSR.scala b/src/main/scala/chisel/util/LFSR.scala
index 1befb8ca..f70630bf 100644
--- a/src/main/scala/chisel/util/LFSR.scala
+++ b/src/main/scala/chisel/util/LFSR.scala
@@ -3,7 +3,9 @@
 /** LFSRs in all shapes and sizes.
   */
 
-package chisel
+package chisel.util
+
+import chisel._
 
 // scalastyle:off magic.number
 /** linear feedback shift register
diff --git a/src/main/scala/chisel/util/Lookup.scala b/src/main/scala/chisel/util/Lookup.scala
index 1fdfd6ae..d32d9aec 100644
--- a/src/main/scala/chisel/util/Lookup.scala
+++ b/src/main/scala/chisel/util/Lookup.scala
@@ -1,6 +1,8 @@
 // See LICENSE for license details.
 
-package chisel
+package chisel.util
+
+import chisel._
 
 object ListLookup {
   def apply[T <: Data](addr: UInt, default: List[T], mapping: Array[(BitPat, List[T])]): List[T] = {
diff --git a/src/main/scala/chisel/util/Math.scala b/src/main/scala/chisel/util/Math.scala
index 1bf667ce..69464d15 100644
--- a/src/main/scala/chisel/util/Math.scala
+++ b/src/main/scala/chisel/util/Math.scala
@@ -3,7 +3,9 @@
 /** Scala-land math helper functions, like logs.
   */
 
-package chisel
+package chisel.util
+
+import chisel._
 
 /** Compute the log2 rounded up with min value of 1 */
 object log2Up {
diff --git a/src/main/scala/chisel/util/Mux.scala b/src/main/scala/chisel/util/Mux.scala
index 97467240..cfff4485 100644
--- a/src/main/scala/chisel/util/Mux.scala
+++ b/src/main/scala/chisel/util/Mux.scala
@@ -3,7 +3,9 @@
 /** Mux circuit generators.
   */
 
-package chisel
+package chisel.util
+
+import chisel._
 
 /** Builds a Mux tree out of the input signal vector using a one hot encoded
   select signal. Returns the output of the Mux tree.
diff --git a/src/main/scala/chisel/util/OneHot.scala b/src/main/scala/chisel/util/OneHot.scala
index 5d1de1a7..ef21c65d 100644
--- a/src/main/scala/chisel/util/OneHot.scala
+++ b/src/main/scala/chisel/util/OneHot.scala
@@ -3,7 +3,9 @@
 /** Circuit generators for working with one-hot representations.
   */
 
-package chisel
+package chisel.util
+
+import chisel._
 
 /** Converts from One Hot Encoding to a UInt indicating which bit is active
   * This is the inverse of [[Chisel.UIntToOH UIntToOH]]*/
diff --git a/src/main/scala/chisel/util/Reg.scala b/src/main/scala/chisel/util/Reg.scala
index 1808af76..1b40646d 100644
--- a/src/main/scala/chisel/util/Reg.scala
+++ b/src/main/scala/chisel/util/Reg.scala
@@ -3,7 +3,9 @@
 /** Variations and helpers for registers.
   */
 
-package chisel
+package chisel.util
+
+import chisel._
 
 object RegNext {
 
diff --git a/src/main/scala/chisel/util/TransitName.scala b/src/main/scala/chisel/util/TransitName.scala
index 141b10bc..04e1995b 100644
--- a/src/main/scala/chisel/util/TransitName.scala
+++ b/src/main/scala/chisel/util/TransitName.scala
@@ -1,5 +1,6 @@
-package chisel
+package chisel.util
 
+import chisel._
 import internal.HasId
 
 object TransitName {
diff --git a/src/main/scala/chisel/util/Valid.scala b/src/main/scala/chisel/util/Valid.scala
index cffed0a7..56ac9abb 100644
--- a/src/main/scala/chisel/util/Valid.scala
+++ b/src/main/scala/chisel/util/Valid.scala
@@ -3,7 +3,9 @@
 /** Wrappers for valid interfaces and associated circuit generators using them.
   */
 
-package chisel
+package chisel.util
+
+import chisel._
 
 /** An I/O Bundle containing data and a signal determining if it is valid */
 class ValidIO[+T <: Data](gen2: T) extends Bundle