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* Change RawModule._commands to a VectorBuilder (#2839)
* Change RawModule._commands to a VectorBuilder
Use the resulting Vector to build the underlying Component's commands
and then use those instead of copying the original ArrayBuffer when
iterating on commands. Previously, the Component was using a List to
hold the commands which is particularly memory inefficient, especially
for large modules.
* Optimize Converter's handling of Seq[Command]
It previously converted the Commands to a List (which, while not
captured in the type system, they were already a List) and then used
head and tail iteration. This is less efficient with the new underlying
Vector implementation.
(cherry picked from commit 48a1ef0a3872c6b68d46145764d977926923a270)
* Waive false binary compatibility failures
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Switch to using experimental trait for OpaqueTypes (#2783)
This makes it more clear that the feature is experimental. Users may
still override the opaqueType method for more dynamic control over when
instances of a given Record are OpaqueTypes or not, but they are
discouraged from doing so.
(cherry picked from commit 7525dc71ccc2050d8e4a68b38f3b76920ba693fc)
* Fix cloneType in RecordSpec
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Bugfix converter clearing flips (#2788)
* Bugfix: Output on Vec of bundle with mixed field orientations
* Bugfix OpaqueTypes clearing flips
(cherry picked from commit f05bff1a337589bafebd08783bb0f6a72092a95a)
# Conflicts:
# src/test/scala/chiselTests/Direction.scala
* Resolve backport conflicts
Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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We need to ensure that contextual names stay contextual (ie. sensitive
to the module context which is important for naming ports).
(cherry picked from commit cee255216c4a1bb658a2d8ddc03d966ce7ffb877)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Bugfix - OpaqueSlot replace invalid localName (#2701)
(cherry picked from commit fb8ea2a2fac227f2570da992d7877de2eb1cf801)
* Fix cloneTypes (#2703)
Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
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* Add OpaqueType support to Records (#2662)
OpaqueTypes are essentially type aliases that hide the underlying type.
They are implemented in Chisel as Records of a single, unnamed element
where the wrapping Record does not exist in the emitted FIRRTL.
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit df5afee2d41b5bcd82d4013b977965c0dfe046fd)
* Fix test compilation
* Fix OpaqueType tests in RecordSpec
Need to implement cloneType correctly and to warn instead of error when
accessing .toTarget of non-hardware types because that is a warning (not
error) in 3.5.
* Waive MiMa false positives
Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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(cherry picked from commit 4b10cf7a276e90b280c1fd57070566acac3d80d3)
Co-authored-by: Girish Pai <girish.pai@sifive.com>
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* Define leading '_' as API for creating temporaries
Chisel and FIRRTL have long used signals with names beginning with an
underscore as an API to specify that the name does not really matter.
Tools like Verilator follow a similar convention and exclude signals
with underscore names from waveform dumps by default. With the
introduction of compiler-plugin prefixing in Chisel 3.4, the convention
remained but was hard for users to use unless the unnnamed signal
existed outside of any prefix domain. Notably, unnamed signals are most
useful when creating wires inside of utility methods which almost always
results in the signal ending up with a prefix.
With this commit, Chisel explicitly recognizes signals whos val names
start with an underscore and preserve that underscore regardless of any
prefixing. Chisel will also ignore such underscores when generating
prefixes based on the temporary signal, preventing accidental double
underscores in the names of signals that are prefixed by the temporary.
(cherry picked from commit bd94366290886f3489d58f88b9768c7c11fa2cb6)
* Remove unused defaultPrefix argument from _computeName
(cherry picked from commit ec178aa20a830df2c8c756b9e569709a59073554)
# Conflicts:
# core/src/main/scala/chisel3/Module.scala
# core/src/main/scala/chisel3/experimental/hierarchy/ModuleClone.scala
* Resolve backport conflicts
* Waive false positive binary compatibility errors
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Command:
sbt scalafmtAll
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This reverts commit 21e324727e99f0bc124aaddea7fe294b4111c23a.
Note that I am keeping the change making Arg sealed.
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Also clean up deprecation warnings for replacement APIs and add
clarifying ScalaDoc.
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Provides a more intuitive implementation of toString for Data.
Utilizes the fact that the compiler plugin provides names earlier than
Chisel had in the past so we can accurately guess the name of
signals even in the currently elaborating module.
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
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This introduces a new experimental API for module instantiation that disentagles
elaborating the definition (or implementation) from instantiation of
a given module. This solves Chisel's longstanding reliance on
"Deduplication" for generating Verilog with multiple instances of the
same module.
The new API resides in package chisel3.experimental.hierarchy. Please
see the hierarchy ScalaDoc, documentation, and tests for examples of
use.
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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This will be slightly slower as it involves converting from Chisel
modules to FIRRTL modules before turning them into Strings. This cost is
somewhat mitigated by doing that conversion lazily such that we never
materialize the entire firrtl Circuit in memory, only 1 module at a
time.
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(#1944)" (#2080)
This reverts commit ed894c61474c8bc73761a6c360ef9d14505d853b.
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* remove DefRegInit, change DefReg API with option defination.
* add error message
* use Option[RegInitIR].
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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DataView is a mechanism for "viewing" Scala objects as a subtype of
`Data`. Often, this is useful for viewing one subtype of `Data`, as
another. One can think about a DataView as a cross between a
customizable cast and an untagged union.
A DataView has a Target type `T`, and a View type `V`. DataView requires
that an implementation of `DataProduct` is available for Target types.
DataProduct is a type class that provides a way to iterate on `Data`
children of objects of implementing types.
If a DataView is provided for a type T to a type V, then the function
.viewAs[V] (of type T => V) is available. The object (of type T) returned
by .viewAs is called a "View" and can be used as both an rvalue and an
lvalue. Unlike when using an .asTypeOf cast, connecting to a "View" will
connect to the associated field or fields of the underlying Target.
DataView also enables .viewAsSupertype which is available for viewing
Bundles as a parent Bundle type. It is similar to .viewAs but requires
a prototype object of the Target type which will be cloned in order to
create the returned View. .viewAsSupertype maps between the
corresponding fields of the parent and child Bundle types.
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* prototype annotating verif constructs
* switch to final class
* name emissions
* moving BaseSim to experimental
* adding name tests
* fixing quotation escapes
* emitting names, but everything has a default name
* only name things with provided/suggested names
* name every BaseSim node
* removing msg, unused imports
* fixing file exist calls
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This PR provides for support for Vec literals. They can be one of two forms
Inferred:
```
Vec.Lit(0x1.U, 0x2.U)
```
or explicit:
```
Vec(2, UInt(4.W)).Lit(0 -> 0x1.U, 1 -> 0x2.U)
```
- Explicit form allows for partial, or sparse, literals.
- Vec literals can be used as Register initializers
- Arbitrary nesting (consistent with type constraints is allowed)
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* Update reported width from div/rem to match FIRRTL results
* Add tests for width of % and / on UInt and SInt
* Add loop-based test for known UInt/SInt op result widths
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers
WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] chiselTests.QueueSpec
[error] examples.VendingMachineGeneratorSpec
[error] chiselTests.HarnessSpec
[error] chiselTests.ConnectSpec
[error] chiselTests.aop.SelectSpec
[error] chiselTests.PopCountSpec
[error] chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3>
```
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Added prefixing and a compiler plugin to improve naming. Only works for Scala 2.12 and above.
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add `check(...)` affordance
* Add assert (renamed from check and fixed)
* Add verification statements
* Move formal to experimental.verification
* Make test use ChiselStage
`generateFirrtl` has been cut from Chisel
* Fix newly introduced style warnings
* Fix some old style warnings for good measure
* Revert "Fix some old style warnings for good measure"
This reverts commit 31d51726c2faa4c277230104bd469ff7ffefc890.
* Cut scalastyle comments
* Cut formal delimiter comments
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* Rename coreMacros to macros
* Rename chiselFrontend to core
Also make each subproject publish with "chisel3-" as a prefix
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