Apply scalafmt

Command:
sbt scalafmtAll

2 files changed, 268 insertions, 183 deletions

diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
index ac784882..2d21a7cb 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
@@ -5,7 +5,7 @@ import chisel3._
 import chisel3.experimental._
 import chisel3.internal.sourceinfo.{NoSourceInfo, SourceInfo, SourceLine, UnlocatableSourceInfo}
 import firrtl.{ir => fir}
-import chisel3.internal.{HasId, castToInt, throwException}
+import chisel3.internal.{castToInt, throwException, HasId}
 
 import scala.annotation.{nowarn, tailrec}
 import scala.collection.immutable.Queue
@@ -21,9 +21,9 @@ private[chisel3] object Converter {
     case PString(str) => (str.replaceAll("%", "%%"), List.empty)
     case format: FirrtlFormat =>
       ("%" + format.specifier, List(format.bits.ref))
-    case Name(data) => (data.ref.name, List.empty)
+    case Name(data)     => (data.ref.name, List.empty)
     case FullName(data) => (data.ref.fullName(ctx), List.empty)
-    case Percent => ("%%", List.empty)
+    case Percent        => ("%%", List.empty)
   }
 
   private def reportInternalError(msg: String): Nothing = {
@@ -53,9 +53,9 @@ private[chisel3] object Converter {
 
   def convert(dir: MemPortDirection): firrtl.MPortDir = dir match {
     case MemPortDirection.INFER => firrtl.MInfer
-    case MemPortDirection.READ => firrtl.MRead
+    case MemPortDirection.READ  => firrtl.MRead
     case MemPortDirection.WRITE => firrtl.MWrite
-    case MemPortDirection.RDWR => firrtl.MReadWrite
+    case MemPortDirection.RDWR  => firrtl.MReadWrite
   }
 
   // TODO
@@ -82,7 +82,8 @@ private[chisel3] object Converter {
       fir.UIntLiteral(n, fir.IntWidth(u.minWidth))
     case ULit(n, w) =>
       fir.UIntLiteral(n, convert(w))
-    case slit @ SLit(n, w) => fir.SIntLiteral(n, convert(w))
+    case slit @ SLit(n, w) =>
+      fir.SIntLiteral(n, convert(w))
       val unsigned = if (n < 0) (BigInt(1) << slit.width.get) + n else n
       val uint = convert(ULit(unsigned, slit.width), ctx, info)
       fir.DoPrim(firrtl.PrimOps.AsSInt, Seq(uint), Seq.empty, fir.UnknownType)
@@ -120,19 +121,43 @@ private[chisel3] object Converter {
     case e @ DefWire(info, id) =>
       Some(fir.DefWire(convert(info), e.name, extractType(id, info)))
     case e @ DefReg(info, id, clock) =>
-      Some(fir.DefRegister(convert(info), e.name, extractType(id, info), convert(clock, ctx, info),
-                           firrtl.Utils.zero, convert(getRef(id, info), ctx, info)))
+      Some(
+        fir.DefRegister(
+          convert(info),
+          e.name,
+          extractType(id, info),
+          convert(clock, ctx, info),
+          firrtl.Utils.zero,
+          convert(getRef(id, info), ctx, info)
+        )
+      )
     case e @ DefRegInit(info, id, clock, reset, init) =>
-      Some(fir.DefRegister(convert(info), e.name, extractType(id, info), convert(clock, ctx, info),
-                           convert(reset, ctx, info), convert(init, ctx, info)))
+      Some(
+        fir.DefRegister(
+          convert(info),
+          e.name,
+          extractType(id, info),
+          convert(clock, ctx, info),
+          convert(reset, ctx, info),
+          convert(init, ctx, info)
+        )
+      )
     case e @ DefMemory(info, id, t, size) =>
       Some(firrtl.CDefMemory(convert(info), e.name, extractType(t, info), size, false))
     case e @ DefSeqMemory(info, id, t, size, ruw) =>
       Some(firrtl.CDefMemory(convert(info), e.name, extractType(t, info), size, true, ruw))
     case e: DefMemPort[_] =>
       val info = e.sourceInfo
-      Some(firrtl.CDefMPort(convert(e.sourceInfo), e.name, fir.UnknownType,
-             e.source.fullName(ctx), Seq(convert(e.index, ctx, info), convert(e.clock, ctx, info)), convert(e.dir)))
+      Some(
+        firrtl.CDefMPort(
+          convert(e.sourceInfo),
+          e.name,
+          fir.UnknownType,
+          e.source.fullName(ctx),
+          Seq(convert(e.index, ctx, info), convert(e.clock, ctx, info)),
+          convert(e.dir)
+        )
+      )
     case Connect(info, loc, exp) =>
       Some(fir.Connect(convert(info), convert(loc, ctx, info), convert(exp, ctx, info)))
     case BulkConnect(info, loc, exp) =>
@@ -147,16 +172,33 @@ private[chisel3] object Converter {
       Some(fir.Stop(convert(info), ret, convert(clock, ctx, info), firrtl.Utils.one, e.name))
     case e @ Printf(_, info, clock, pable) =>
       val (fmt, args) = unpack(pable, ctx)
-      Some(fir.Print(convert(info), fir.StringLit(fmt),
-                     args.map(a => convert(a, ctx, info)), convert(clock, ctx, info), firrtl.Utils.one, e.name))
+      Some(
+        fir.Print(
+          convert(info),
+          fir.StringLit(fmt),
+          args.map(a => convert(a, ctx, info)),
+          convert(clock, ctx, info),
+          firrtl.Utils.one,
+          e.name
+        )
+      )
     case e @ Verification(_, op, info, clk, pred, msg) =>
       val firOp = op match {
         case Formal.Assert => fir.Formal.Assert
         case Formal.Assume => fir.Formal.Assume
-        case Formal.Cover => fir.Formal.Cover
+        case Formal.Cover  => fir.Formal.Cover
       }
-      Some(fir.Verification(firOp, convert(info), convert(clk, ctx, info),
-        convert(pred, ctx, info), firrtl.Utils.one, fir.StringLit(msg), e.name))
+      Some(
+        fir.Verification(
+          firOp,
+          convert(info),
+          convert(clk, ctx, info),
+          convert(pred, ctx, info),
+          firrtl.Utils.one,
+          fir.StringLit(msg),
+          e.name
+        )
+      )
     case _ => None
   }
 
@@ -183,59 +225,60 @@ private[chisel3] object Converter {
     */
   def convert(cmds: Seq[Command], ctx: Component): fir.Statement = {
     @tailrec
-    def rec(acc: Queue[fir.Statement],
-            scope: List[WhenFrame])
-           (cmds: Seq[Command]): Seq[fir.Statement] = {
+    def rec(acc: Queue[fir.Statement], scope: List[WhenFrame])(cmds: Seq[Command]): Seq[fir.Statement] = {
       if (cmds.isEmpty) {
         assert(scope.isEmpty)
         acc
-      } else convertSimpleCommand(cmds.head, ctx) match {
-        // Most Commands map 1:1
-        case Some(stmt) =>
-          rec(acc :+ stmt, scope)(cmds.tail)
-        // When scoping logic does not map 1:1 and requires pushing/popping WhenFrames
-        // Please see WhenFrame for more details
-        case None => cmds.head match {
-          case WhenBegin(info, pred) =>
-            val when = fir.Conditionally(convert(info), convert(pred, ctx, info), fir.EmptyStmt, fir.EmptyStmt)
-            val frame = WhenFrame(when, acc, false)
-            rec(Queue.empty, frame +: scope)(cmds.tail)
-          case WhenEnd(info, depth, _) =>
-            val frame = scope.head
-            val when = if (frame.alt) frame.when.copy(alt = fir.Block(acc))
-                       else frame.when.copy(conseq = fir.Block(acc))
-            // Check if this when has an else
-            cmds.tail.headOption match {
-              case Some(AltBegin(_)) =>
-                assert(!frame.alt, "Internal Error! Unexpected when structure!") // Only 1 else per when
-                rec(Queue.empty, frame.copy(when = when, alt = true) +: scope.tail)(cmds.drop(2))
-              case _ => // Not followed by otherwise
-                // If depth > 0 then we need to close multiple When scopes so we add a new WhenEnd
-                // If we're nested we need to add more WhenEnds to ensure each When scope gets
-                // properly closed
-                val cmdsx = if (depth > 0) WhenEnd(info, depth - 1, false) +: cmds.tail  else cmds.tail
-                rec(frame.outer :+ when, scope.tail)(cmdsx)
+      } else
+        convertSimpleCommand(cmds.head, ctx) match {
+          // Most Commands map 1:1
+          case Some(stmt) =>
+            rec(acc :+ stmt, scope)(cmds.tail)
+          // When scoping logic does not map 1:1 and requires pushing/popping WhenFrames
+          // Please see WhenFrame for more details
+          case None =>
+            cmds.head match {
+              case WhenBegin(info, pred) =>
+                val when = fir.Conditionally(convert(info), convert(pred, ctx, info), fir.EmptyStmt, fir.EmptyStmt)
+                val frame = WhenFrame(when, acc, false)
+                rec(Queue.empty, frame +: scope)(cmds.tail)
+              case WhenEnd(info, depth, _) =>
+                val frame = scope.head
+                val when =
+                  if (frame.alt) frame.when.copy(alt = fir.Block(acc))
+                  else frame.when.copy(conseq = fir.Block(acc))
+                // Check if this when has an else
+                cmds.tail.headOption match {
+                  case Some(AltBegin(_)) =>
+                    assert(!frame.alt, "Internal Error! Unexpected when structure!") // Only 1 else per when
+                    rec(Queue.empty, frame.copy(when = when, alt = true) +: scope.tail)(cmds.drop(2))
+                  case _ => // Not followed by otherwise
+                    // If depth > 0 then we need to close multiple When scopes so we add a new WhenEnd
+                    // If we're nested we need to add more WhenEnds to ensure each When scope gets
+                    // properly closed
+                    val cmdsx = if (depth > 0) WhenEnd(info, depth - 1, false) +: cmds.tail else cmds.tail
+                    rec(frame.outer :+ when, scope.tail)(cmdsx)
+                }
+              case OtherwiseEnd(info, depth) =>
+                val frame = scope.head
+                val when = frame.when.copy(alt = fir.Block(acc))
+                // TODO For some reason depth == 1 indicates the last closing otherwise whereas
+                //  depth == 0 indicates last closing when
+                val cmdsx = if (depth > 1) OtherwiseEnd(info, depth - 1) +: cmds.tail else cmds.tail
+                rec(scope.head.outer :+ when, scope.tail)(cmdsx)
             }
-          case OtherwiseEnd(info, depth) =>
-            val frame = scope.head
-            val when = frame.when.copy(alt = fir.Block(acc))
-            // TODO For some reason depth == 1 indicates the last closing otherwise whereas
-            //  depth == 0 indicates last closing when
-            val cmdsx = if (depth > 1) OtherwiseEnd(info, depth - 1) +: cmds.tail else cmds.tail
-            rec(scope.head.outer :+ when, scope.tail)(cmdsx)
         }
-      }
     }
     fir.Block(rec(Queue.empty, List.empty)(cmds))
   }
 
   def convert(width: Width): fir.Width = width match {
-    case UnknownWidth() => fir.UnknownWidth
+    case UnknownWidth()    => fir.UnknownWidth
     case KnownWidth(value) => fir.IntWidth(value)
   }
 
   def convert(bp: BinaryPoint): fir.Width = bp match {
-    case UnknownBinaryPoint => fir.UnknownWidth
+    case UnknownBinaryPoint      => fir.UnknownWidth
     case KnownBinaryPoint(value) => fir.IntWidth(value)
   }
 
@@ -248,15 +291,15 @@ private[chisel3] object Converter {
   def extractType(data: Data, info: SourceInfo): fir.Type = extractType(data, false, info)
 
   def extractType(data: Data, clearDir: Boolean, info: SourceInfo): fir.Type = data match {
-    case _: Clock => fir.ClockType
+    case _: Clock      => fir.ClockType
     case _: AsyncReset => fir.AsyncResetType
-    case _: ResetType => fir.ResetType
-    case d: EnumType => fir.UIntType(convert(d.width))
-    case d: UInt => fir.UIntType(convert(d.width))
-    case d: SInt => fir.SIntType(convert(d.width))
+    case _: ResetType  => fir.ResetType
+    case d: EnumType   => fir.UIntType(convert(d.width))
+    case d: UInt       => fir.UIntType(convert(d.width))
+    case d: SInt       => fir.SIntType(convert(d.width))
     case d: FixedPoint => fir.FixedType(convert(d.width), convert(d.binaryPoint))
-    case d: Interval => fir.IntervalType(d.range.lowerBound, d.range.upperBound, d.range.firrtlBinaryPoint)
-    case d: Analog => fir.AnalogType(convert(d.width))
+    case d: Interval   => fir.IntervalType(d.range.lowerBound, d.range.upperBound, d.range.firrtlBinaryPoint)
+    case d: Analog     => fir.AnalogType(convert(d.width))
     case d: Vec[_] => fir.VectorType(extractType(d.sample_element, clearDir, info), d.length)
     case d: Record =>
       val childClearDir = clearDir ||
@@ -269,23 +312,23 @@ private[chisel3] object Converter {
           fir.Field(getRef(elt, info).name, fir.Flip, extractType(elt, false, info))
       }
       fir.BundleType(d.elements.toIndexedSeq.reverse.map { case (_, e) => eltField(e) })
-    }
+  }
 
   def convert(name: String, param: Param): fir.Param = param match {
-    case IntParam(value) => fir.IntParam(name, value)
+    case IntParam(value)    => fir.IntParam(name, value)
     case DoubleParam(value) => fir.DoubleParam(name, value)
     case StringParam(value) => fir.StringParam(name, fir.StringLit(value))
-    case RawParam(value) => fir.RawStringParam(name, value)
+    case RawParam(value)    => fir.RawStringParam(name, value)
   }
 
   def convert(port: Port, topDir: SpecifiedDirection = SpecifiedDirection.Unspecified): fir.Port = {
     val resolvedDir = SpecifiedDirection.fromParent(topDir, port.dir)
     val dir = resolvedDir match {
       case SpecifiedDirection.Unspecified | SpecifiedDirection.Output => fir.Output
-      case SpecifiedDirection.Flip | SpecifiedDirection.Input => fir.Input
+      case SpecifiedDirection.Flip | SpecifiedDirection.Input         => fir.Input
     }
     val clearDir = resolvedDir match {
-      case SpecifiedDirection.Input | SpecifiedDirection.Output => true
+      case SpecifiedDirection.Input | SpecifiedDirection.Output     => true
       case SpecifiedDirection.Unspecified | SpecifiedDirection.Flip => false
     }
     val info = UnlocatableSourceInfo // Unfortunately there is no source locator for ports ATM
@@ -297,8 +340,13 @@ private[chisel3] object Converter {
     case ctx @ DefModule(_, name, ports, cmds) =>
       fir.Module(fir.NoInfo, name, ports.map(p => convert(p)), convert(cmds.toList, ctx))
     case ctx @ DefBlackBox(id, name, ports, topDir, params) =>
-      fir.ExtModule(fir.NoInfo, name, ports.map(p => convert(p, topDir)), id.desiredName,
-                    params.map { case (name, p) => convert(name, p) }.toSeq)
+      fir.ExtModule(
+        fir.NoInfo,
+        name,
+        ports.map(p => convert(p, topDir)),
+        id.desiredName,
+        params.map { case (name, p) => convert(name, p) }.toSeq
+      )
   }
 
   def convert(circuit: Circuit): fir.Circuit =
@@ -310,4 +358,3 @@ private[chisel3] object Converter {
     fir.Circuit(fir.NoInfo, lazyModules.map(convert), circuit.name)
   }
 }
-
diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index 68f5f18e..1ee8842f 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -15,7 +15,6 @@ import scala.collection.immutable.NumericRange
 import scala.math.BigDecimal.RoundingMode
 import scala.annotation.nowarn
 
-
 case class PrimOp(name: String) {
   override def toString: String = name
 }
@@ -68,35 +67,36 @@ object PrimOp {
 sealed abstract class Arg {
   def localName: String = name
   def contextualName(ctx: Component): String = name
-  def fullName(ctx: Component): String = contextualName(ctx)
+  def fullName(ctx:       Component): String = contextualName(ctx)
   def name: String
 }
 
 case class Node(id: HasId) extends Arg {
   override def contextualName(ctx: Component): String = id.getOptionRef match {
     case Some(arg) => arg.contextualName(ctx)
-    case None => id.instanceName
+    case None      => id.instanceName
   }
   override def localName: String = id.getOptionRef match {
     case Some(arg) => arg.localName
-    case None => id.instanceName
+    case None      => id.instanceName
   }
   def name: String = id.getOptionRef match {
     case Some(arg) => arg.name
-    case None => id.instanceName
+    case None      => id.instanceName
   }
 }
 
 object Arg {
   def earlyLocalName(id: HasId): String = id.getOptionRef match {
     case Some(Index(Node(imm), Node(value))) => s"${earlyLocalName(imm)}[${earlyLocalName(imm)}]"
-    case Some(Index(Node(imm), arg)) => s"${earlyLocalName(imm)}[${arg.localName}]"
-    case Some(Slot(Node(imm), name)) => s"${earlyLocalName(imm)}.$name"
-    case Some(arg) => arg.name
-    case None => id match {
-      case data: Data => data._computeName(None, Some("?")).get
-      case _ => "?"
-    }
+    case Some(Index(Node(imm), arg))         => s"${earlyLocalName(imm)}[${arg.localName}]"
+    case Some(Slot(Node(imm), name))         => s"${earlyLocalName(imm)}.$name"
+    case Some(arg)                           => arg.name
+    case None =>
+      id match {
+        case data: Data => data._computeName(None, Some("?")).get
+        case _ => "?"
+      }
   }
 }
 
@@ -121,8 +121,10 @@ abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
 
   protected def minWidth: Int
   if (forcedWidth) {
-    require(widthArg.get >= minWidth,
-      s"The literal value ${num} was elaborated with a specified width of ${widthArg.get} bits, but at least ${minWidth} bits are required.")
+    require(
+      widthArg.get >= minWidth,
+      s"The literal value ${num} was elaborated with a specified width of ${widthArg.get} bits, but at least ${minWidth} bits are required."
+    )
   }
 }
 
@@ -131,8 +133,8 @@ case class ILit(n: BigInt) extends Arg {
 }
 
 case class ULit(n: BigInt, w: Width) extends LitArg(n, w) {
-  def name: String = "UInt" + width + "(\"h0" + num.toString(16) + "\")"
-  def minWidth: Int = 1 max n.bitLength
+  def name:     String = "UInt" + width + "(\"h0" + num.toString(16) + "\")"
+  def minWidth: Int = 1.max(n.bitLength)
 
   def cloneWithWidth(newWidth: Width): this.type = {
     ULit(n, newWidth).asInstanceOf[this.type]
@@ -171,8 +173,11 @@ case class IntervalLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends Li
     s"asInterval(${ULit(unsigned, width).name}, ${n}, ${n}, ${binaryPoint.asInstanceOf[KnownBinaryPoint].value})"
   }
   val range: IntervalRange = {
-    new IntervalRange(IntervalRange.getBound(isClosed = true, BigDecimal(n)),
-      IntervalRange.getBound(isClosed = true, BigDecimal(n)), IntervalRange.getRangeWidth(binaryPoint))
+    new IntervalRange(
+      IntervalRange.getBound(isClosed = true, BigDecimal(n)),
+      IntervalRange.getBound(isClosed = true, BigDecimal(n)),
+      IntervalRange.getRangeWidth(binaryPoint)
+    )
   }
   def minWidth: Int = 1 + n.bitLength
 
@@ -182,6 +187,7 @@ case class IntervalLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends Li
 }
 
 case class Ref(name: String) extends Arg
+
 /** Arg for ports of Modules
   * @param mod the module this port belongs to
   * @param name the name of the port
@@ -190,6 +196,7 @@ case class ModuleIO(mod: BaseModule, name: String) extends Arg {
   override def contextualName(ctx: Component): String =
     if (mod eq ctx.id) name else s"${mod.getRef.name}.$name"
 }
+
 /** Ports of cloned modules (CloneModuleAsRecord)
   * @param mod The original module for which these ports are a clone
   * @param name the name of the module instance
@@ -224,22 +231,22 @@ object Width {
 
 sealed abstract class Width {
   type W = Int
-  def min(that: Width): Width = this.op(that, _ min _)
-  def max(that: Width): Width = this.op(that, _ max _)
-  def + (that: Width): Width = this.op(that, _ + _)
-  def + (that: Int): Width = this.op(this, (a, b) => a + that)
-  def shiftRight(that: Int): Width = this.op(this, (a, b) => 0 max (a - that))
+  def min(that:              Width): Width = this.op(that, _ min _)
+  def max(that:              Width): Width = this.op(that, _ max _)
+  def +(that:                Width): Width = this.op(that, _ + _)
+  def +(that:                Int):   Width = this.op(this, (a, b) => a + that)
+  def shiftRight(that:       Int): Width = this.op(this, (a, b) => 0.max(a - that))
   def dynamicShiftLeft(that: Width): Width =
     this.op(that, (a, b) => a + (1 << b) - 1)
 
   def known: Boolean
-  def get: W
+  def get:   W
   protected def op(that: Width, f: (W, W) => W): Width
 }
 
 sealed case class UnknownWidth() extends Width {
   def known: Boolean = false
-  def get: Int = None.get
+  def get:   Int = None.get
   def op(that: Width, f: (W, W) => W): Width = this
   override def toString: String = ""
 }
@@ -247,10 +254,10 @@ sealed case class UnknownWidth() extends Width {
 sealed case class KnownWidth(value: Int) extends Width {
   require(value >= 0)
   def known: Boolean = true
-  def get: Int = value
+  def get:   Int = value
   def op(that: Width, f: (W, W) => W): Width = that match {
     case KnownWidth(x) => KnownWidth(f(value, x))
-    case _ => that
+    case _             => that
   }
   override def toString: String = s"<${value.toString}>"
 }
@@ -262,36 +269,35 @@ object BinaryPoint {
 
 sealed abstract class BinaryPoint {
   type W = Int
-  def max(that: BinaryPoint): BinaryPoint = this.op(that, _ max _)
-  def + (that: BinaryPoint): BinaryPoint = this.op(that, _ + _)
-  def + (that: Int): BinaryPoint = this.op(this, (a, b) => a + that)
-  def shiftRight(that: Int): BinaryPoint = this.op(this, (a, b) => 0 max (a - that))
+  def max(that:              BinaryPoint): BinaryPoint = this.op(that, _ max _)
+  def +(that:                BinaryPoint): BinaryPoint = this.op(that, _ + _)
+  def +(that:                Int):         BinaryPoint = this.op(this, (a, b) => a + that)
+  def shiftRight(that:       Int): BinaryPoint = this.op(this, (a, b) => 0.max(a - that))
   def dynamicShiftLeft(that: BinaryPoint): BinaryPoint =
     this.op(that, (a, b) => a + (1 << b) - 1)
 
   def known: Boolean
-  def get: W
+  def get:   W
   protected def op(that: BinaryPoint, f: (W, W) => W): BinaryPoint
 }
 
 case object UnknownBinaryPoint extends BinaryPoint {
   def known: Boolean = false
-  def get: Int = None.get
+  def get:   Int = None.get
   def op(that: BinaryPoint, f: (W, W) => W): BinaryPoint = this
   override def toString: String = ""
 }
 
 sealed case class KnownBinaryPoint(value: Int) extends BinaryPoint {
   def known: Boolean = true
-  def get: Int = value
+  def get:   Int = value
   def op(that: BinaryPoint, f: (W, W) => W): BinaryPoint = that match {
     case KnownBinaryPoint(x) => KnownBinaryPoint(f(value, x))
-    case _ => that
+    case _                   => that
   }
   override def toString: String = s"<<${value.toString}>>"
 }
 
-
 sealed abstract class MemPortDirection(name: String) {
   override def toString: String = name
 }
@@ -305,17 +311,18 @@ object MemPortDirection {
 sealed trait RangeType {
   def getWidth: Width
 
-  def * (that: IntervalRange): IntervalRange
-  def +& (that: IntervalRange): IntervalRange
-  def -& (that: IntervalRange): IntervalRange
-  def << (that: Int): IntervalRange
-  def >> (that: Int): IntervalRange
-  def << (that: KnownWidth): IntervalRange
-  def >> (that: KnownWidth): IntervalRange
+  def *(that:     IntervalRange): IntervalRange
+  def +&(that:    IntervalRange): IntervalRange
+  def -&(that:    IntervalRange): IntervalRange
+  def <<(that:    Int):           IntervalRange
+  def >>(that:    Int):           IntervalRange
+  def <<(that:    KnownWidth):    IntervalRange
+  def >>(that:    KnownWidth):    IntervalRange
   def merge(that: IntervalRange): IntervalRange
 }
 
 object IntervalRange {
+
   /** Creates an IntervalRange, this is used primarily by the range interpolator macro
     * @param lower               lower bound
     * @param upper               upper bound
@@ -352,7 +359,9 @@ object IntervalRange {
       case KnownWidth(w) =>
         val nearestPowerOf2 = BigInt("1" + ("0" * (w - 1)), 2)
         IntervalRange(
-          firrtlir.Closed(BigDecimal(-nearestPowerOf2)), firrtlir.Closed(BigDecimal(nearestPowerOf2 - 1)), binaryPoint
+          firrtlir.Closed(BigDecimal(-nearestPowerOf2)),
+          firrtlir.Closed(BigDecimal(nearestPowerOf2 - 1)),
+          binaryPoint
         )
       case _ =>
         IntervalRange(firrtlir.UnknownBound, firrtlir.UnknownBound, binaryPoint)
@@ -365,22 +374,19 @@ object IntervalRange {
   }
 
   def getBound(isClosed: Boolean, value: String): firrtlir.Bound = {
-    if(value == "?") {
+    if (value == "?") {
       firrtlir.UnknownBound
-    }
-    else if(isClosed) {
+    } else if (isClosed) {
       firrtlir.Closed(BigDecimal(value))
-    }
-    else {
+    } else {
       firrtlir.Open(BigDecimal(value))
     }
   }
 
   def getBound(isClosed: Boolean, value: BigDecimal): firrtlir.Bound = {
-    if(isClosed) {
+    if (isClosed) {
       firrtlir.Closed(value)
-    }
-    else {
+    } else {
       firrtlir.Open(value)
     }
   }
@@ -394,33 +400,30 @@ object IntervalRange {
   }
 
   def getBinaryPoint(n: Int): firrtlir.Width = {
-    if(n < 0) {
+    if (n < 0) {
       firrtlir.UnknownWidth
-    }
-    else {
+    } else {
       firrtlir.IntWidth(n)
     }
   }
   def getBinaryPoint(n: BinaryPoint): firrtlir.Width = {
     n match {
-      case UnknownBinaryPoint => firrtlir.UnknownWidth
+      case UnknownBinaryPoint  => firrtlir.UnknownWidth
       case KnownBinaryPoint(w) => firrtlir.IntWidth(w)
     }
   }
 
   def getRangeWidth(w: Width): firrtlir.Width = {
-    if(w.known) {
+    if (w.known) {
       firrtlir.IntWidth(w.get)
-    }
-    else {
+    } else {
       firrtlir.UnknownWidth
     }
   }
   def getRangeWidth(binaryPoint: BinaryPoint): firrtlir.Width = {
-    if(binaryPoint.known) {
+    if (binaryPoint.known) {
       firrtlir.IntWidth(binaryPoint.get)
-    }
-    else {
+    } else {
       firrtlir.UnknownWidth
     }
   }
@@ -428,47 +431,46 @@ object IntervalRange {
   def Unknown: IntervalRange = range"[?,?].?"
 }
 
-
 sealed class IntervalRange(
-                            val lowerBound: firrtlir.Bound,
-                            val upperBound: firrtlir.Bound,
-                            private[chisel3] val firrtlBinaryPoint: firrtlir.Width)
-  extends firrtlir.IntervalType(lowerBound, upperBound, firrtlBinaryPoint)
+  val lowerBound:                         firrtlir.Bound,
+  val upperBound:                         firrtlir.Bound,
+  private[chisel3] val firrtlBinaryPoint: firrtlir.Width)
+    extends firrtlir.IntervalType(lowerBound, upperBound, firrtlBinaryPoint)
     with RangeType {
 
   (lowerBound, upperBound) match {
     case (firrtlir.Open(begin), firrtlir.Open(end)) =>
-      if(begin >= end) throw new ChiselException(s"Invalid range with ${serialize}")
+      if (begin >= end) throw new ChiselException(s"Invalid range with ${serialize}")
       binaryPoint match {
         case KnownBinaryPoint(bp) =>
-          if(begin >= end - (BigDecimal(1) / BigDecimal(BigInt(1) << bp))) {
+          if (begin >= end - (BigDecimal(1) / BigDecimal(BigInt(1) << bp))) {
             throw new ChiselException(s"Invalid range with ${serialize}")
           }
         case _ =>
       }
     case (firrtlir.Open(begin), firrtlir.Closed(end)) =>
-      if(begin >= end) throw new ChiselException(s"Invalid range with ${serialize}")
+      if (begin >= end) throw new ChiselException(s"Invalid range with ${serialize}")
     case (firrtlir.Closed(begin), firrtlir.Open(end)) =>
-      if(begin >= end) throw new ChiselException(s"Invalid range with ${serialize}")
+      if (begin >= end) throw new ChiselException(s"Invalid range with ${serialize}")
     case (firrtlir.Closed(begin), firrtlir.Closed(end)) =>
-      if(begin > end) throw new ChiselException(s"Invalid range with ${serialize}")
+      if (begin > end) throw new ChiselException(s"Invalid range with ${serialize}")
     case _ =>
   }
 
   override def toString: String = {
     val binaryPoint = firrtlBinaryPoint match {
       case firrtlir.IntWidth(n) => s"$n"
-      case _ => "?"
+      case _                    => "?"
     }
     val lowerBoundString = lowerBound match {
-      case firrtlir.Closed(l)      => s"[$l"
-      case firrtlir.Open(l)        => s"($l"
-      case firrtlir.UnknownBound   => s"[?"
+      case firrtlir.Closed(l)    => s"[$l"
+      case firrtlir.Open(l)      => s"($l"
+      case firrtlir.UnknownBound => s"[?"
     }
     val upperBoundString = upperBound match {
-      case firrtlir.Closed(l)      => s"$l]"
-      case firrtlir.Open(l)        => s"$l)"
-      case firrtlir.UnknownBound   => s"?]"
+      case firrtlir.Closed(l)    => s"$l]"
+      case firrtlir.Open(l)      => s"$l)"
+      case firrtlir.UnknownBound => s"?]"
     }
     s"""range"$lowerBoundString,$upperBoundString.$binaryPoint""""
   }
@@ -487,8 +489,8 @@ sealed class IntervalRange(
       case Some(inc) =>
         lower match {
           case firrtlir.Closed(n) => Some(n)
-          case firrtlir.Open(n) => Some(n + inc)
-          case _ => None
+          case firrtlir.Open(n)   => Some(n + inc)
+          case _                  => None
         }
       case _ =>
         None
@@ -503,8 +505,8 @@ sealed class IntervalRange(
       case Some(inc) =>
         upper match {
           case firrtlir.Closed(n) => Some(n)
-          case firrtlir.Open(n) => Some(n - inc)
-          case _ => None
+          case firrtlir.Open(n)   => Some(n - inc)
+          case _                  => None
         }
       case _ =>
         None
@@ -528,16 +530,18 @@ sealed class IntervalRange(
 
   override def getWidth: Width = {
     width match {
-      case firrtlir.IntWidth(n) => KnownWidth(n.toInt)
+      case firrtlir.IntWidth(n)  => KnownWidth(n.toInt)
       case firrtlir.UnknownWidth => UnknownWidth()
     }
   }
 
   private def doFirrtlOp(op: firrtlir.PrimOp, that: IntervalRange): IntervalRange = {
-    PrimOps.set_primop_type(
-      firrtlir.DoPrim(op,
-        Seq(firrtlir.Reference("a", this), firrtlir.Reference("b", that)), Nil,firrtlir.UnknownType)
-    ).tpe match {
+    PrimOps
+      .set_primop_type(
+        firrtlir
+          .DoPrim(op, Seq(firrtlir.Reference("a", this), firrtlir.Reference("b", that)), Nil, firrtlir.UnknownType)
+      )
+      .tpe match {
       case i: firrtlir.IntervalType => IntervalRange(i.lower, i.upper, i.point)
       case other => sys.error("BAD!")
     }
@@ -545,24 +549,27 @@ sealed class IntervalRange(
 
   private def doFirrtlDynamicShift(that: UInt, isLeft: Boolean): IntervalRange = {
     val uinttpe = that.widthOption match {
-      case None => firrtlir.UIntType(firrtlir.UnknownWidth)
+      case None    => firrtlir.UIntType(firrtlir.UnknownWidth)
       case Some(w) => firrtlir.UIntType(firrtlir.IntWidth(w))
     }
-    val op = if(isLeft) PrimOps.Dshl else PrimOps.Dshr
-    PrimOps.set_primop_type(
-      firrtlir.DoPrim(op,
-        Seq(firrtlir.Reference("a", this), firrtlir.Reference("b", uinttpe)), Nil,firrtlir.UnknownType)
-    ).tpe match {
+    val op = if (isLeft) PrimOps.Dshl else PrimOps.Dshr
+    PrimOps
+      .set_primop_type(
+        firrtlir
+          .DoPrim(op, Seq(firrtlir.Reference("a", this), firrtlir.Reference("b", uinttpe)), Nil, firrtlir.UnknownType)
+      )
+      .tpe match {
       case i: firrtlir.IntervalType => IntervalRange(i.lower, i.upper, i.point)
       case other => sys.error("BAD!")
     }
   }
 
   private def doFirrtlOp(op: firrtlir.PrimOp, that: Int): IntervalRange = {
-    PrimOps.set_primop_type(
-      firrtlir.DoPrim(op,
-        Seq(firrtlir.Reference("a", this)), Seq(BigInt(that)), firrtlir.UnknownType)
-    ).tpe match {
+    PrimOps
+      .set_primop_type(
+        firrtlir.DoPrim(op, Seq(firrtlir.Reference("a", this)), Seq(BigInt(that)), firrtlir.UnknownType)
+      )
+      .tpe match {
       case i: firrtlir.IntervalType => IntervalRange(i.lower, i.upper, i.point)
       case other => sys.error("BAD!")
     }
@@ -596,7 +603,7 @@ sealed class IntervalRange(
   }
 
   private def adjustBoundValue(value: BigDecimal, binaryPointValue: Int): BigDecimal = {
-    if(binaryPointValue >= 0) {
+    if (binaryPointValue >= 0) {
       val maskFactor = BigDecimal(1 << binaryPointValue)
       val a = (value * maskFactor)
       val b = a.setScale(0, RoundingMode.DOWN)
@@ -611,9 +618,9 @@ sealed class IntervalRange(
     binaryPoint match {
       case KnownBinaryPoint(binaryPointValue) =>
         bound match {
-          case firrtlir.Open(value) => firrtlir.Open(adjustBoundValue(value, binaryPointValue))
+          case firrtlir.Open(value)   => firrtlir.Open(adjustBoundValue(value, binaryPointValue))
           case firrtlir.Closed(value) => firrtlir.Closed(adjustBoundValue(value, binaryPointValue))
-          case _ => bound
+          case _                      => bound
         }
       case _ => firrtlir.UnknownBound
     }
@@ -746,19 +753,22 @@ sealed class IntervalRange(
   override def merge(that: IntervalRange): IntervalRange = {
     val lowest = (this.getLowestPossibleValue, that.getLowestPossibleValue) match {
       case (Some(l1), Some(l2)) =>
-        if(l1 < l2) { this.lower } else { that.lower }
+        if (l1 < l2) { this.lower }
+        else { that.lower }
       case _ =>
         firrtlir.UnknownBound
     }
     val highest = (this.getHighestPossibleValue, that.getHighestPossibleValue) match {
       case (Some(l1), Some(l2)) =>
-        if(l1 >= l2) { this.lower } else { that.lower }
+        if (l1 >= l2) { this.lower }
+        else { that.lower }
       case _ =>
         firrtlir.UnknownBound
     }
     val newBinaryPoint = (this.firrtlBinaryPoint, that.firrtlBinaryPoint) match {
       case (firrtlir.IntWidth(b1), firrtlir.IntWidth(b2)) =>
-        if(b1 > b2) { firrtlir.IntWidth(b1)} else { firrtlir.IntWidth(b2) }
+        if (b1 > b2) { firrtlir.IntWidth(b1) }
+        else { firrtlir.IntWidth(b2) }
       case _ =>
         firrtlir.UnknownWidth
     }
@@ -788,8 +798,21 @@ case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition
 case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition
 case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition
 case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition
-case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt, readUnderWrite: fir.ReadUnderWrite.Value) extends Definition
-case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition
+case class DefSeqMemory(
+  sourceInfo:     SourceInfo,
+  id:             HasId,
+  t:              Data,
+  size:           BigInt,
+  readUnderWrite: fir.ReadUnderWrite.Value)
+    extends Definition
+case class DefMemPort[T <: Data](
+  sourceInfo: SourceInfo,
+  id:         T,
+  source:     Node,
+  dir:        MemPortDirection,
+  index:      Arg,
+  clock:      Arg)
+    extends Definition
 @nowarn("msg=class Port") // delete when Port becomes private
 case class DefInstance(sourceInfo: SourceInfo, id: BaseModule, ports: Seq[Port]) extends Definition
 case class WhenBegin(sourceInfo: SourceInfo, pred: Arg) extends Command
@@ -802,7 +825,10 @@ case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command
 case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
 case class Stop(id: stop.Stop, sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Definition
 // Note this is just deprecated which will cause deprecation warnings, use @nowarn
-@deprecated("This API should never have been public, for Module port reflection, use DataMirror.modulePorts", "Chisel 3.5")
+@deprecated(
+  "This API should never have been public, for Module port reflection, use DataMirror.modulePorts",
+  "Chisel 3.5"
+)
 case class Port(id: Data, dir: SpecifiedDirection)
 case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Definition
 object Formal extends Enumeration {
@@ -810,18 +836,30 @@ object Formal extends Enumeration {
   val Assume = Value("assume")
   val Cover = Value("cover")
 }
-case class Verification[T <: VerificationStatement](id: T, op: Formal.Value, sourceInfo: SourceInfo, clock: Arg,
-                        predicate: Arg, message: String) extends Definition
+case class Verification[T <: VerificationStatement](
+  id:         T,
+  op:         Formal.Value,
+  sourceInfo: SourceInfo,
+  clock:      Arg,
+  predicate:  Arg,
+  message:    String)
+    extends Definition
 @nowarn("msg=class Port") // delete when Port becomes private
 abstract class Component extends Arg {
-  def id: BaseModule
-  def name: String
+  def id:    BaseModule
+  def name:  String
   def ports: Seq[Port]
 }
 @nowarn("msg=class Port") // delete when Port becomes private
 case class DefModule(id: RawModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component
 @nowarn("msg=class Port") // delete when Port becomes private
-case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], topDir: SpecifiedDirection, params: Map[String, Param]) extends Component
+case class DefBlackBox(
+  id:     BaseBlackBox,
+  name:   String,
+  ports:  Seq[Port],
+  topDir: SpecifiedDirection,
+  params: Map[String, Param])
+    extends Component
 
 case class Circuit(name: String, components: Seq[Component], annotations: Seq[ChiselAnnotation], renames: RenameMap) {
   def firrtlAnnotations: Iterable[Annotation] = annotations.flatMap(_.toFirrtl.update(renames))