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authorAlbert Magyar2020-07-20 12:11:44 -0700
committerAlbert Magyar2020-07-21 13:06:53 -0700
commit7e9f424fb7dcd11c894ceb9f6f049fd9eda80632 (patch)
tree1fa15e357d0af7b82316fa2ee659e2e98118488c /core/src/main/scala/chisel3/internal/firrtl
parent4a0e828cfe76e0d3bd6c4a0cc593589fe74ed0ba (diff)
Delete outdated scalastyle configuration comments from source
Diffstat (limited to 'core/src/main/scala/chisel3/internal/firrtl')
-rw-r--r--core/src/main/scala/chisel3/internal/firrtl/Converter.scala12
-rw-r--r--core/src/main/scala/chisel3/internal/firrtl/IR.scala6
2 files changed, 5 insertions, 13 deletions
diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
index 5c1d6935..67d87a68 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
@@ -41,7 +41,7 @@ private[chisel3] object Converter {
// TODO
// * Memoize?
// * Move into the Chisel IR?
- def convert(arg: Arg, ctx: Component): fir.Expression = arg match { // scalastyle:ignore cyclomatic.complexity
+ def convert(arg: Arg, ctx: Component): fir.Expression = arg match {
case Node(id) =>
convert(id.getRef, ctx)
case Ref(name) =>
@@ -53,10 +53,8 @@ private[chisel3] object Converter {
case Index(imm, value) =>
fir.SubAccess(convert(imm, ctx), convert(value, ctx), fir.UnknownType)
case ModuleIO(mod, name) =>
- // scalastyle:off if.brace
if (mod eq ctx.id) fir.Reference(name, fir.UnknownType)
else fir.SubField(fir.Reference(mod.getRef.name, fir.UnknownType), name, fir.UnknownType)
- // scalastyle:on if.brace
case u @ ULit(n, UnknownWidth()) =>
fir.UIntLiteral(n, fir.IntWidth(u.minWidth))
case ULit(n, w) =>
@@ -81,7 +79,7 @@ private[chisel3] object Converter {
}
/** Convert Commands that map 1:1 to Statements */
- def convertSimpleCommand(cmd: Command, ctx: Component): Option[fir.Statement] = cmd match { // scalastyle:ignore cyclomatic.complexity line.size.limit
+ def convertSimpleCommand(cmd: Command, ctx: Component): Option[fir.Statement] = cmd match {
case e: DefPrim[_] =>
val consts = e.args.collect { case ILit(i) => i }
val args = e.args.flatMap {
@@ -151,9 +149,8 @@ private[chisel3] object Converter {
* @param ctx Component (Module) context within which we are translating
* @return FIRRTL Statement that is equivalent to the input cmds
*/
- def convert(cmds: Seq[Command], ctx: Component): fir.Statement = { // scalastyle:ignore cyclomatic.complexity
+ def convert(cmds: Seq[Command], ctx: Component): fir.Statement = {
@tailrec
- // scalastyle:off if.brace
def rec(acc: Queue[fir.Statement],
scope: List[WhenFrame])
(cmds: Seq[Command]): Seq[fir.Statement] = {
@@ -197,7 +194,6 @@ private[chisel3] object Converter {
}
}
}
- // scalastyle:on if.brace
fir.Block(rec(Queue.empty, List.empty)(cmds))
}
@@ -217,7 +213,7 @@ private[chisel3] object Converter {
case d => d.specifiedDirection
}
- def extractType(data: Data, clearDir: Boolean = false): fir.Type = data match { // scalastyle:ignore cyclomatic.complexity line.size.limit
+ def extractType(data: Data, clearDir: Boolean = false): fir.Type = data match {
case _: Clock => fir.ClockType
case _: AsyncReset => fir.AsyncResetType
case _: ResetType => fir.ResetType
diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index d98bebcd..89bc4a63 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -14,7 +14,6 @@ import _root_.firrtl.PrimOps
import scala.collection.immutable.NumericRange
import scala.math.BigDecimal.RoundingMode
-// scalastyle:off number.of.types
case class PrimOp(name: String) {
override def toString: String = name
@@ -95,7 +94,7 @@ abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
protected def minWidth: Int
if (forcedWidth) {
require(widthArg.get >= minWidth,
- s"The literal value ${num} was elaborated with a specified width of ${widthArg.get} bits, but at least ${minWidth} bits are required.") // scalastyle:ignore line.size.limit
+ s"The literal value ${num} was elaborated with a specified width of ${widthArg.get} bits, but at least ${minWidth} bits are required.")
}
}
@@ -359,7 +358,6 @@ object IntervalRange {
}
}
- //scalastyle:off method.name
def Unknown: IntervalRange = range"[?,?].?"
}
@@ -390,7 +388,6 @@ sealed class IntervalRange(
case _ =>
}
- //scalastyle:off cyclomatic.complexity
override def toString: String = {
val binaryPoint = firrtlBinaryPoint match {
case firrtlir.IntWidth(n) => s"$n"
@@ -718,7 +715,6 @@ abstract class Definition extends Command {
def id: HasId
def name: String = id.getRef.name
}
-// scalastyle:off line.size.limit
case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition
case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command
case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition