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* Promote ChiselEnum user APIs from experimental (#2929)
They are commonly used and if we were ever to change them, we will need
to go through a deprecation process anyway.
Note that the EnumAnnotations remain in chisel3.experimental because,
like all Chisel annotation support, they are slated to be deprecated and
removed.
(cherry picked from commit 424e9446f1675fe0168e22bdfbbe85db997376e6)
# Conflicts:
# docs/src/cookbooks/verilog-vs-chisel.md
# docs/src/explanations/chisel-enum.md
* Maintain binary compatbility, use aliases in chisel3 package
* Deprecate the actual classes in chisel3.experimental
* Also fix backport conflicts
Co-authored-by: Jack Koenig <koenig@sifive.com>
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(cherry picked from commit 49feb083c69066988ca0666ea4249a86570e2589)
Co-authored-by: Megan Wachs <megan@sifive.com>
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#2829) (#2831)
* Add Aggregate.elementsIterator and micro-optimize
elementsIterator provides a more efficient API for iterating on the
elements of Aggregates. It is especially useful for Records where
getElements returns a Seq and thus eagerly constructs a new
datastructure which may then just be iterated on anyway.
This new elementsIterator API is then used throughout the codebase where
it makes sense.
Also change Vec.getElements to just return the underlying self instead
of constructing a new Seq.
(cherry picked from commit defa440b349031475daeff4024fad04925cccee6)
# Conflicts:
# core/src/main/scala/chisel3/Aggregate.scala
# core/src/main/scala/chisel3/Module.scala
# core/src/main/scala/chisel3/experimental/Trace.scala
* Move Aggregate.bind inline into Record.bind
Vec overrides bind and does not call the version in Aggregate so the
version in Aggregate is misleading in that its only ever used by
Records. Now there is no version in Aggregate and the actual
functionality and use is more clear.
(cherry picked from commit b054c30ba47026cb2a9b28c696a0a0a58b1e2ee7)
# Conflicts:
# core/src/main/scala/chisel3/Aggregate.scala
* Extract and optimize duplicate checking Record.bind
This replaces an immutable.Map with a single mutable.HashSet and saves
the allocation of # elements Seqs.
(cherry picked from commit 832ea52bc23424bb75b9654422b725a9cafaef40)
# Conflicts:
# core/src/main/scala/chisel3/Aggregate.scala
* Add check for Records that define def elements
(cherry picked from commit a4f223415de19e2a732e0b6a8fe681f706a19a56)
* Resolve backport conflicts
* Make elementsIterator final and package private
* Waive false MiMa failure
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit fce8394bb0ddc9ae0d9c6668e034e483bd6b71c5)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Co-authored-by: Megan Wachs <megan@sifive.com>
(cherry picked from commit 26100a875c69bf56f7442fac82ca9c74ad3596eb)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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(cherry picked from commit f462c9f9307bebf3012da52432c3729cd752321c)
Co-authored-by: Aditya Naik <91489422+adkian-sifive@users.noreply.github.com>
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- Remove line defeating having wire locators
`implicit val noSourceInfo = UnlocatableSourceInfo` from `WireDefault#apply`
- Add test to show locators
(cherry picked from commit f701a9f8151891e3bf9019cd3229cb3f2cd1833b)
Co-authored-by: Chick Markley <chick.markley@sifive.com>
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(cherry picked from commit 67cff8253740f19642006dba7eff58b1e5fa1291)
Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
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* Replace some options with nullable vars (#2658)
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit ac460bfeb16c8e7d0dc00975bb03f73c0fea2103)
# Conflicts:
# core/src/main/scala/chisel3/internal/Builder.scala
* Fix backport conflicts (#2661)
Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
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(cherry picked from commit 11e8cc60d6268301cff352b8a1d7c4d672b5be11)
Co-authored-by: Megan Wachs <megan@sifive.com>
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(cherry picked from commit 7fa0d8bf1cafcdf141046476a100abf021bdcac4)
Co-authored-by: Zachary Yedidia <zyedidia@gmail.com>
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option (#2575) (#2579)
* Added ImplicitInvalidate trait with tests
(cherry picked from commit 1356ced1b89ca35ae0cb1d1ab45227ec1776d5e7)
Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
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(backport #2476) (#2479)
* Capture 1:1 mappings of Aggregates inside of views
This is implemented by including any corresponding Aggregates from the
DataView.mapping in the AggregateViewBinding.childMap (which is now of
type Map[Data, Data]).
This enables dynamically indexing Vecs that are themselves elements of
larger Aggregates in views when the corresponding element of the view is
a Vec of the same type. It also increases the number of cases where a
single Target can represent part of a view.
(cherry picked from commit 1f6b1ca14ccf86918065073c3f6f3626dd83a68e)
* Add FlatIO API for creating ports from Bundles without a prefix
(cherry picked from commit 772a3a1fe3b9372b7c2d7cd2d424b2adcd633cdb)
* [docs] Add FlatIO to the general cookbook
(cherry picked from commit b4159641350f238f0f899b69954142ce8ee11544)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Adds generation of `Bundle.elements` method to the chores done by the compiler plugin
For each `Bundle` find the relevant visible Chisel field members and construct a
hard-coded list of the elements and their names implemented as `_elementsImpl`
For more details: See plugins/README.md
- Should be no change in API
- Handles inheritance and mixins
- Handles Seq[Data]
- Tests in BundleElementSpec
Co-authored-by: chick <chick.markley@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 237200a420581519f29149cbae9b3e968c0d01fc)
Co-authored-by: Chick Markley <chick@qrhino.com>
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Command:
sbt scalafmtAll
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Also clean up deprecation warnings for replacement APIs and add
clarifying ScalaDoc.
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Co-authored-by: Megan Wachs <megan@sifive.com>
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Provides a more intuitive implementation of toString for Data.
Utilizes the fact that the compiler plugin provides names earlier than
Chisel had in the past so we can accurately guess the name of
signals even in the currently elaborating module.
Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
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functions (#2124)
* Migrate nullary funcs to parameterless versions
* Make deprecation message and dummy arguments clear and consistent
Co-authored-by: Megan Wachs <megan@sifive.com>
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DataView is a mechanism for "viewing" Scala objects as a subtype of
`Data`. Often, this is useful for viewing one subtype of `Data`, as
another. One can think about a DataView as a cross between a
customizable cast and an untagged union.
A DataView has a Target type `T`, and a View type `V`. DataView requires
that an implementation of `DataProduct` is available for Target types.
DataProduct is a type class that provides a way to iterate on `Data`
children of objects of implementing types.
If a DataView is provided for a type T to a type V, then the function
.viewAs[V] (of type T => V) is available. The object (of type T) returned
by .viewAs is called a "View" and can be used as both an rvalue and an
lvalue. Unlike when using an .asTypeOf cast, connecting to a "View" will
connect to the associated field or fields of the underlying Target.
DataView also enables .viewAsSupertype which is available for viewing
Bundles as a parent Bundle type. It is similar to .viewAs but requires
a prototype object of the Target type which will be cloned in order to
create the returned View. .viewAsSupertype maps between the
corresponding fields of the parent and child Bundle types.
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* deprecate getPorts with modulePorts.
* add doc to fullModulePorts and update deprecation notes.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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This PR provides for support for Vec literals. They can be one of two forms
Inferred:
```
Vec.Lit(0x1.U, 0x2.U)
```
or explicit:
```
Vec(2, UInt(4.W)).Lit(0 -> 0x1.U, 1 -> 0x2.U)
```
- Explicit form allows for partial, or sparse, literals.
- Vec literals can be used as Register initializers
- Arbitrary nesting (consistent with type constraints is allowed)
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No longer create a pointer from parent to every HasId, only do it by
default for BaseModules and MemBases. Add pointer from parent to Data
upon binding the Data.
* Add MemTypeBinding for port types of Mems
This binding is similar to the SampleElementBinding for Vecs in that
these Data are not truly hardware, but are represented in the FIRRTL IR
and thus need some representation.
* Call _onModuleClose on unbound Records
This maintains some corner-case behavior that is nevertheless relied
upon. It ensures that refs are set for the elements of Records, even if
they are not bound to any real hardware.
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Implemented by folding Element.ref into Data.ref. Element.ref had
special handling for literals, but because Bundles can also be literals,
there were code paths that tried to get the ref of a Bundle literal
which was non-existent. Now, all literals are handled together.
Because FIRRTL does not have support for Bundle literals, Bundle literal
refs are implemented by materializing a Wire.
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* Use Data refs for name prefixing with aggregate elements
Vecs set the refs of their elements upon construction of those elements.
In the past, Records haven't set their elements refs until module close,
but it can be done sooner. Doing it upon binding means that refs will at
least be available for Records used in hardware elements. Since only
bound Data can be connected to anyway, Aggregate elements being
connected to will always have a ref which we can then use for creating
naming prefixes.
* Add tighter correctness checks
* Handle more cases in connection prefixing
Add support for forcing setRef to override a previous setting. This
is only used by BlackBox ports which need to drop their io prefix.
Also add a Try() around Data.bindingToString which sometimes throws
exceptions when being used to .toString a Data in an error message.
* Strip trailing spaces in names in compiler plugin
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Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers
WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] chiselTests.QueueSpec
[error] examples.VendingMachineGeneratorSpec
[error] chiselTests.HarnessSpec
[error] chiselTests.ConnectSpec
[error] chiselTests.aop.SelectSpec
[error] chiselTests.PopCountSpec
[error] chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3>
```
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* Fixed the aspect as parent bug in Data and MonoConnect
* refactored and cleaned up finding an aspect parent
* Added aspect fix to the BiConnect class
* added unit test for manipulating submodules via aspects
* Refactored to move determination of proper parent to Builder and made logic simpler in MonoConnect, Data, and BiConnect
* Removed unused function and provided Scaladoc for retrieveParent
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* Include and check when scoping as part of reg/mem/wire/node bindings
* Allow outdated 'when' behavior of CHIRRTL memory ports with enables
* Extend cross-module / when-visibility checks to all data refs
* Fixes #1512
* Cannot be checked if outside a module context
* E.g. delayed evaluation of printf / assert args
* Add basic test cases for cross-module refs / signals escaping when scopes
* Remove illegal cross-module references from existing tests
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Added prefixing and a compiler plugin to improve naming. Only works for Scala 2.12 and above.
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Rename coreMacros to macros
* Rename chiselFrontend to core
Also make each subproject publish with "chisel3-" as a prefix
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