diff options
| author | mergify[bot] | 2022-11-15 05:28:10 +0000 |
|---|---|---|
| committer | GitHub | 2022-11-15 05:28:10 +0000 |
| commit | b169f6db95f9778cf8968cc1042b7f810f9d8123 (patch) | |
| tree | 68f6fe715ce158f6de2c21c4747a500ce25f6db8 /core/src/main/scala/chisel3/Data.scala | |
| parent | c8046636a25474be4c547c6fe9c6d742ea7b1d13 (diff) | |
fullModulePorts + Opaque Types Fix and Test (#2845) (#2846)
(cherry picked from commit 49feb083c69066988ca0666ea4249a86570e2589)
Co-authored-by: Megan Wachs <megan@sifive.com>
Diffstat (limited to 'core/src/main/scala/chisel3/Data.scala')
| -rw-r--r-- | core/src/main/scala/chisel3/Data.scala | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala index 50093333..dddc0d5d 100644 --- a/core/src/main/scala/chisel3/Data.scala +++ b/core/src/main/scala/chisel3/Data.scala @@ -256,8 +256,13 @@ package experimental { def fullModulePorts(target: BaseModule): Seq[(String, Data)] = { def getPortNames(name: String, data: Data): Seq[(String, Data)] = Seq(name -> data) ++ (data match { case _: Element => Seq() - case r: Record => r.elements.toSeq.flatMap { case (eltName, elt) => getPortNames(s"${name}_${eltName}", elt) } - case v: Vec[_] => v.zipWithIndex.flatMap { case (elt, index) => getPortNames(s"${name}_${index}", elt) } + case r: Record => + r.elements.toSeq.flatMap { + case (eltName, elt) => + if (r._isOpaqueType) { getPortNames(s"${name}", elt) } + else { getPortNames(s"${name}_${eltName}", elt) } + } + case v: Vec[_] => v.zipWithIndex.flatMap { case (elt, index) => getPortNames(s"${name}_${index}", elt) } }) modulePorts(target).flatMap { case (name, data) => |