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path: root/chiselFrontend/src
AgeCommit message (Expand)Author
2016-09-09Convert to NotStrict for internal connection checks.Jim Lawson
2016-09-02Add/cleanup UInt/SInt factory methods.Jim Lawson
2016-09-01Deprecate Vec.fill() offering Vec(Seq.fill()).Jim Lawson
2016-09-01Move connection implicits from Module constructor to connection methods.Jim Lawson
2016-08-30Merge branch 'master' into gsdtJim Lawson
2016-08-30Use correct case for Strict/NotStrict compile options.Jim Lawson
2016-08-29Check module-specific compile options.Jim Lawson
2016-08-29Rename CompileOptions implicit objects.Jim Lawson
2016-08-29Pass compileOptions as an implicit Module parameter.Jim Lawson
2016-08-29Rename individual compile options.Jim Lawson
2016-08-25Use bulkConnect in Vec,fill if any (flattened) element of the Vec has a direc...Jim Lawson
2016-08-24Per Chisel meeting.chick
2016-08-23Swap name of compileOption "assumeNoDirectionIsOutput" to "assumeNoDirectionI...Jim Lawson
2016-08-21provides signal name methods for firrtl annotation and chisel testersDonggyu Kim
2016-08-19Restore immutability of direction overrides.Jim Lawson
2016-08-19Simplify autioIOWrap code in computePorts().Jim Lawson
2016-08-18Add assumeNoDirectionIsOutput.Jim Lawson
2016-08-18Use isFirrtlFlipped() to determine port direction.Jim Lawson
2016-08-18Merge branch 'sdtwigg_connectwrap_renamechisel3' into gsdt_testsJim Lawson
2016-08-17Rocket-chip updates.Jim Lawson
2016-08-17Reduce rocket-chip elaboration errors.Jim Lawson
2016-08-16Add component to signature.Jim Lawson
2016-08-16Provide public SignalID trait to be used to conjure up a signal identifier.Jim Lawson
2016-08-16Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-15Make "def width" a private API; expose isWidthKnown instead (#257)Andrew Waterman
2016-08-12Use compileOptions to determine if Missing...FieldExceptions are thrown.Jim Lawson
2016-08-12Merge branch 'compile_options' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-12Add support for per-Module compilation options.Jim Lawson
2016-08-11Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-09Support Module name overrides with "override def desiredName"Andrew Waterman
2016-08-09Legalize identifier names before printingAndrew Waterman
2016-08-04Deal with directions on Clocks.Jim Lawson
2016-08-03Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-07-31Expose asUInt from DataAndrew Waterman
2016-07-31Fix two deprecation warningsAndrew Waterman
2016-07-28Add missing factory constructors.Jim Lawson
2016-07-27Additional compatibility code.Jim Lawson
2016-07-25Enable current (chisel2-style) compatibility mode.Jim Lawson
2016-07-25Minimize differences with master.Jim Lawson
2016-07-25Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-07-21Introduce chiselCloneType to distinguish from cloneType.Jim Lawson
2016-07-20More literal/width rangling.Jim Lawson
2016-07-20Distinguish between ?Int.Lit and ?Int.widthJim Lawson
2016-07-20Generate better names for nodes (#190)Jack Koenig
2016-07-20Compile ok.Jim Lawson
2016-07-19Fixes for only connectwrap version.Jim Lawson
2016-07-19Merge in "complete" versions of Mem, Reg.Jim Lawson
2016-07-19Fix LitBinding and MultiAssign tests.Jim Lawson
2016-07-19Remove explicit literal binding.Jim Lawson
2016-07-19Incorporate connection logic.Jim Lawson
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