diff options
| author | Andrew Waterman | 2016-07-31 17:05:21 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2016-07-31 17:25:49 -0700 |
| commit | 8b66107bffac270be16196d5a852cf3e6808fb0a (patch) | |
| tree | ef5f97945eb501cd483317d87607244461847f08 /chiselFrontend/src | |
| parent | 54cd58cbb435170dd2ed67dafe1cb1d769a799e8 (diff) | |
Fix two deprecation warnings
Diffstat (limited to 'chiselFrontend/src')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala index 0872ec41..63bcc87f 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala @@ -47,7 +47,7 @@ private[chisel3] object SeqUtils { if (in.tail.isEmpty) { in.head._2 } else { - val masked = for ((s, i) <- in) yield Mux(s, i.toBits, Bits(0)) + val masked = for ((s, i) <- in) yield Mux(s, i.asUInt, UInt(0)) val width = in.map(_._2.width).reduce(_ max _) in.head._2.cloneTypeWidth(width).fromBits(masked.reduceLeft(_|_)) } |
