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authorJim Lawson2016-08-18 13:42:24 -0700
committerJim Lawson2016-08-18 13:42:24 -0700
commitbd6e69c19aef76b6e87f7e328e03d1b93f8a1472 (patch)
treea90764915abc398b7b1cfccdf9f3c2bc2dfe1cce /chiselFrontend/src
parentd18274e307271809db2c27676f1dca40a49c9627 (diff)
Use isFirrtlFlipped() to determine port direction.
Diffstat (limited to 'chiselFrontend/src')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Module.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 450f5b58..24dabcbe 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -119,7 +119,7 @@ extends HasId {
}
// Port definitions need to know input or output at top-level.
// By FIRRTL semantics, 'flipped' becomes an Input
- val direction = if(Data.isFlipped(port)) Direction.Input else Direction.Output
+ val direction = if(Data.isFirrtlFlipped(port)) Direction.Input else Direction.Output
firrtl.Port(port, direction)
}