summaryrefslogtreecommitdiff
path: root/chiselFrontend/src/main/scala/chisel3/internal/firrtl
AgeCommit message (Expand)Author
2019-03-18Split #974 into two PRs - scalastyle updates (#1037)Jim Lawson
2019-01-21Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) M...Richard Lin
2018-10-12Strong enums (#892)Hasan Genc
2018-07-31Ensure names work for bundles and literals. (#853)Jim Lawson
2018-02-28Refactor Annotations (#767)Jack Koenig
2017-08-17Use firrtl elses in elsewhen/otherwise case emission (#510)Albert Magyar
2017-08-11Rename userDir->specifiedDir (#671)Richard Lin
2017-07-28Black box top-level IO fix (#655)Richard Lin
2017-06-26Directions internals mega-refactor (#617)Richard Lin
2017-04-13Module Hierarchy Refactor (#469)Richard Lin
2017-02-08Add Analog typeJack Koenig
2016-12-07Support for creating chisel annotations that are consumed by firrtl (#393)Chick Markley
2016-12-01Fix spelling of "specified". (#392)Jim Lawson
2016-11-21Fix open-open range specifier, remove dead code, restyle testsducky
2016-11-21first attack on creating a range api for chisel3chick
2016-11-18Add support for parameterized BlackBoxesjackkoenig
2016-10-25FixedPoint number support for chisel3 (#328)Chick Markley
2016-09-21Expose FIRRTL asClock constructAndrew Waterman
2016-09-21Make implicit clock name consistent (#288)Andrew Waterman
2016-09-07Add Printable (#270)Jack Koenig
2016-06-20Rename "package", "import", and explicit references to "chisel3".Jim Lawson
2016-06-20Rename chisel3 package.Jim Lawson
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-12 16:53:48 +0000