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authorJim Lawson2016-06-20 11:38:26 -0700
committerJim Lawson2016-06-20 11:38:26 -0700
commit3026dd214f3db3308eaf8f876d0fc03f75c577d3 (patch)
treeb6599b6d4c350a8f5567a15211906ca7812972f1 /chiselFrontend/src/main/scala/chisel3/internal/firrtl
parentd408d73a171535bd7c2ba9d0037c194022b8a62f (diff)
Rename "package", "import", and explicit references to "chisel3".
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/internal/firrtl')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala12
1 files changed, 6 insertions, 6 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 70e9938b..64d7d5fd 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -1,11 +1,11 @@
// See LICENSE for license details.
-package chisel.internal.firrtl
+package chisel3.internal.firrtl
-import chisel._
+import chisel3._
import core._
-import chisel.internal._
-import chisel.internal.sourceinfo.{SourceInfo, NoSourceInfo}
+import chisel3.internal._
+import chisel3.internal.sourceinfo.{SourceInfo, NoSourceInfo}
case class PrimOp(val name: String) {
override def toString: String = name
@@ -55,8 +55,8 @@ case class Node(id: HasId) extends Arg {
}
abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
- private[chisel] def forcedWidth = widthArg.known
- private[chisel] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
+ private[chisel3] def forcedWidth = widthArg.known
+ private[chisel3] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
protected def minWidth: Int
if (forcedWidth) {