Rename "package", "import", and explicit references to "chisel3".

78 files changed, 429 insertions, 429 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 38a42fea..f2774a8d 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -1,15 +1,15 @@
 // See LICENSE for license details.
 
-package chisel.core
+package chisel3.core
 
 import scala.collection.immutable.ListMap
 import scala.collection.mutable.{ArrayBuffer, HashSet, LinkedHashMap}
 import scala.language.experimental.macros
 
-import chisel.internal._
-import chisel.internal.Builder.pushCommand
-import chisel.internal.firrtl._
-import chisel.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, VecTransform, SourceInfoTransform}
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, VecTransform, SourceInfoTransform}
 
 /** An abstract class for data types that solely consist of (are an aggregate
   * of) other Data objects.
@@ -163,8 +163,8 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int)
     Vec(length, gen).asInstanceOf[this.type]
 
   private val t = gen
-  private[chisel] def toType: String = s"${t.toType}[$length]"
-  private[chisel] lazy val flatten: IndexedSeq[Bits] =
+  private[chisel3] def toType: String = s"${t.toType}[$length]"
+  private[chisel3] lazy val flatten: IndexedSeq[Bits] =
     (0 until length).flatMap(i => this.apply(i).flatten)
 
   for ((elt, i) <- self zipWithIndex)
@@ -331,17 +331,17 @@ class Bundle extends Aggregate(NO_DIR) {
     }
     ArrayBuffer(nameMap.toSeq:_*) sortWith {case ((an, a), (bn, b)) => (a._id > b._id) || ((a eq b) && (an > bn))}
   }
-  private[chisel] def toType = {
+  private[chisel3] def toType = {
     def eltPort(elt: Data): String = {
       val flipStr = if (elt.isFlip) "flip " else ""
       s"${flipStr}${elt.getRef.name} : ${elt.toType}"
     }
     s"{${namedElts.reverse.map(e => eltPort(e._2)).mkString(", ")}}"
   }
-  private[chisel] lazy val flatten = namedElts.flatMap(_._2.flatten)
+  private[chisel3] lazy val flatten = namedElts.flatMap(_._2.flatten)
   private[core] def addElt(name: String, elt: Data): Unit =
     namedElts += name -> elt
-  private[chisel] override def _onModuleClose: Unit = // scalastyle:ignore method.name
+  private[chisel3] override def _onModuleClose: Unit = // scalastyle:ignore method.name
     for ((name, elt) <- namedElts) { elt.setRef(this, _namespace.name(name)) }
 
   override def cloneType : this.type = {
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Assert.scala b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala
index 00cb00f4..c4727148 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Assert.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala
@@ -1,14 +1,14 @@
 // See LICENSE for license details.
 
-package chisel.core
+package chisel3.core
 
 import scala.reflect.macros.blackbox.Context
 import scala.language.experimental.macros
 
-import chisel.internal._
-import chisel.internal.Builder.pushCommand
-import chisel.internal.firrtl._
-import chisel.internal.sourceinfo.SourceInfo
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.SourceInfo
 
 object assert { // scalastyle:ignore object.name
   /** Checks for a condition to be valid in the circuit at all times. If the
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 38e71f8d..94d808a4 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -1,15 +1,15 @@
 // See LICENSE for license details.
 
-package chisel.core
+package chisel3.core
 
 import scala.language.experimental.macros
 
-import chisel.internal._
-import chisel.internal.Builder.pushOp
-import chisel.internal.firrtl._
-import chisel.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, SourceInfoTransform, SourceInfoWhiteboxTransform,
+import chisel3.internal._
+import chisel3.internal.Builder.pushOp
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, SourceInfoTransform, SourceInfoWhiteboxTransform,
   UIntTransform, MuxTransform}
-import chisel.internal.firrtl.PrimOp._
+import chisel3.internal.firrtl.PrimOp._
 
 /** Element is a leaf data type: it cannot contain other Data objects. Example
   * uses are for representing primitive data types, like integers and bits.
@@ -25,9 +25,9 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
   // Arguments for: self-checking code (can't do arithmetic on bits)
   // Arguments against: generates down to a FIRRTL UInt anyways
 
-  private[chisel] def fromInt(x: BigInt, w: Int): this.type
+  private[chisel3] def fromInt(x: BigInt, w: Int): this.type
 
-  private[chisel] def flatten: IndexedSeq[Bits] = IndexedSeq(this)
+  private[chisel3] def flatten: IndexedSeq[Bits] = IndexedSeq(this)
 
   def cloneType: this.type = cloneTypeWidth(width)
 
@@ -360,9 +360,9 @@ sealed class UInt private[core] (dir: Direction, width: Width, lit: Option[ULit]
     extends Bits(dir, width, lit) with Num[UInt] {
   private[core] override def cloneTypeWidth(w: Width): this.type =
     new UInt(dir, w).asInstanceOf[this.type]
-  private[chisel] def toType = s"UInt$width"
+  private[chisel3] def toType = s"UInt$width"
 
-  override private[chisel] def fromInt(value: BigInt, width: Int): this.type =
+  override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
     UInt(value, width).asInstanceOf[this.type]
 
   override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
@@ -537,14 +537,14 @@ sealed class SInt private (dir: Direction, width: Width, lit: Option[SLit] = Non
     extends Bits(dir, width, lit) with Num[SInt] {
   private[core] override def cloneTypeWidth(w: Width): this.type =
     new SInt(dir, w).asInstanceOf[this.type]
-  private[chisel] def toType = s"SInt$width"
+  private[chisel3] def toType = s"SInt$width"
 
   override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
     case _: SInt => this connect that
     case _ => this badConnect that
   }
 
-  override private[chisel] def fromInt(value: BigInt, width: Int): this.type =
+  override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
     SInt(value, width).asInstanceOf[this.type]
 
   final def unary_- (): SInt = macro SourceInfoTransform.noArg
@@ -671,7 +671,7 @@ sealed class Bool(dir: Direction, lit: Option[ULit] = None) extends UInt(dir, Wi
     new Bool(dir).asInstanceOf[this.type]
   }
 
-  override private[chisel] def fromInt(value: BigInt, width: Int): this.type = {
+  override private[chisel3] def fromInt(value: BigInt, width: Int): this.type = {
     require((value == 0 || value == 1) && width == 1)
     Bool(value == 1).asInstanceOf[this.type]
   }
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
index 2126ebce..eee8d598 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
@@ -1,10 +1,10 @@
 // See LICENSE for license details.
 
-package chisel.core
+package chisel3.core
 
-import chisel.internal.Builder.pushCommand
-import chisel.internal.firrtl.{ModuleIO, DefInvalid}
-import chisel.internal.sourceinfo.SourceInfo
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl.{ModuleIO, DefInvalid}
+import chisel3.internal.sourceinfo.SourceInfo
 
 /** Defines a black box, which is a module that can be referenced from within
   * Chisel, but is not defined in the emitted Verilog. Useful for connecting
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index cae38144..d5704369 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -1,13 +1,13 @@
 // See LICENSE for license details.
 
-package chisel.core
+package chisel3.core
 
 import scala.language.experimental.macros
 
-import chisel.internal._
-import chisel.internal.Builder.pushCommand
-import chisel.internal.firrtl._
-import chisel.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
 
 sealed abstract class Direction(name: String) {
   override def toString: String = name
@@ -53,9 +53,9 @@ abstract class Data(dirArg: Direction) extends HasId {
   private[core] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     pushCommand(BulkConnect(sourceInfo, this.lref, that.lref))
   private[core] def lref: Node = Node(this)
-  private[chisel] def ref: Arg = if (isLit) litArg.get else lref
+  private[chisel3] def ref: Arg = if (isLit) litArg.get else lref
   private[core] def cloneTypeWidth(width: Width): this.type
-  private[chisel] def toType: String
+  private[chisel3] def toType: String
 
   def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = this badConnect that
 
@@ -78,7 +78,7 @@ abstract class Data(dirArg: Direction) extends HasId {
   // currently don't exist (while this information may be available during
   // FIRRTL emission, it would break directionality querying from Chisel, which
   // does get used).
-  private[chisel] def flatten: IndexedSeq[Bits]
+  private[chisel3] def flatten: IndexedSeq[Bits]
 
   /** Creates an new instance of this type, unpacking the input Bits into
     * structured data.
@@ -145,9 +145,9 @@ object Clock {
 // TODO: Document this.
 sealed class Clock(dirArg: Direction) extends Element(dirArg, Width(1)) {
   def cloneType: this.type = Clock(dirArg).asInstanceOf[this.type]
-  private[chisel] override def flatten: IndexedSeq[Bits] = IndexedSeq()
+  private[chisel3] override def flatten: IndexedSeq[Bits] = IndexedSeq()
   private[core] def cloneTypeWidth(width: Width): this.type = cloneType
-  private[chisel] def toType = "Clock"
+  private[chisel3] def toType = "Clock"
 
   override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
     case _: Clock => this connect that
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
index a2df2910..38f5ef14 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
@@ -1,13 +1,13 @@
 // See LICENSE for license details.
 
-package chisel.core
+package chisel3.core
 
 import scala.language.experimental.macros
 
-import chisel.internal._
-import chisel.internal.Builder.pushCommand
-import chisel.internal.firrtl._
-import chisel.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, MemTransform}
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, MemTransform}
 
 object Mem {
   @deprecated("Mem argument order should be size, t; this will be removed by the official release", "chisel3")
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 1de3efe5..7032e762 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -1,15 +1,15 @@
 // See LICENSE for license details.
 
-package chisel.core
+package chisel3.core
 
 import scala.collection.mutable.{ArrayBuffer, HashSet}
 import scala.language.experimental.macros
 
-import chisel.internal._
-import chisel.internal.Builder.pushCommand
-import chisel.internal.Builder.dynamicContext
-import chisel.internal.firrtl._
-import chisel.internal.sourceinfo.{SourceInfo, InstTransform, UnlocatableSourceInfo}
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.Builder.dynamicContext
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo, InstTransform, UnlocatableSourceInfo}
 
 object Module {
   /** A wrapper method that all Module instantiations must be wrapped in
@@ -53,7 +53,7 @@ extends HasId {
   def this(_clock: Clock, _reset: Bool) = this(Option(_clock), Option(_reset))
 
   private[core] val _namespace = Builder.globalNamespace.child
-  private[chisel] val _commands = ArrayBuffer[Command]()
+  private[chisel3] val _commands = ArrayBuffer[Command]()
   private[core] val _ids = ArrayBuffer[HasId]()
   dynamicContext.currentModule = Some(this)
 
@@ -67,7 +67,7 @@ extends HasId {
   val clock = Clock(INPUT)
   val reset = Bool(INPUT)
 
-  private[chisel] def addId(d: HasId) { _ids += d }
+  private[chisel3] def addId(d: HasId) { _ids += d }
 
   private[core] def ports: Seq[(String,Data)] = Vector(
     ("clk", clock), ("reset", reset), ("io", io)
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
index a7970816..b0a3c955 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
@@ -1,13 +1,13 @@
 // See LICENSE for license details.
 
-package chisel.core
+package chisel3.core
 
 import scala.language.experimental.macros
 
-import chisel.internal._
-import chisel.internal.Builder.pushCommand
-import chisel.internal.firrtl._
-import chisel.internal.sourceinfo.SourceInfo
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.SourceInfo
 
 object printf { // scalastyle:ignore object.name
   /** Prints a message in simulation.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
index 78461334..b0dd3bb1 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
@@ -1,11 +1,11 @@
 // See LICENSE for license details.
 
-package chisel.core
+package chisel3.core
 
-import chisel.internal._
-import chisel.internal.Builder.pushCommand
-import chisel.internal.firrtl._
-import chisel.internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo}
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo}
 
 object Reg {
   private[core] def makeType[T <: Data](t: T = null, next: T = null, init: T = null): T = {
diff --git a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
index e31119a5..91cb9e89 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
@@ -1,12 +1,12 @@
 // See LICENSE for license details.
 
-package chisel.core
+package chisel3.core
 
 import scala.language.experimental.macros
 
-import chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
+import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
 
-private[chisel] object SeqUtils {
+private[chisel3] object SeqUtils {
   /** Equivalent to Cat(r(n-1), ..., r(0)) */
   def asUInt[T <: Bits](in: Seq[T]): UInt = macro SourceInfoTransform.inArg
 
diff --git a/chiselFrontend/src/main/scala/chisel3/core/When.scala b/chiselFrontend/src/main/scala/chisel3/core/When.scala
index 5d484313..196e7903 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/When.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/When.scala
@@ -1,13 +1,13 @@
 // See LICENSE for license details.
 
-package chisel.core
+package chisel3.core
 
 import scala.language.experimental.macros
 
-import chisel.internal._
-import chisel.internal.Builder.pushCommand
-import chisel.internal.firrtl._
-import chisel.internal.sourceinfo.{SourceInfo}
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo}
 
 object when {  // scalastyle:ignore object.name
   /** Create a `when` condition block, where whether a block of logic is
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index 01628105..0e0a88cc 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -1,15 +1,15 @@
 // See LICENSE for license details.
 
-package chisel.internal
+package chisel3.internal
 
 import scala.util.DynamicVariable
 import scala.collection.mutable.{ArrayBuffer, HashMap}
 
-import chisel._
+import chisel3._
 import core._
 import firrtl._
 
-private[chisel] class Namespace(parent: Option[Namespace], keywords: Set[String]) {
+private[chisel3] class Namespace(parent: Option[Namespace], keywords: Set[String]) {
   private val names = collection.mutable.HashMap[String, Long]()
   for (keyword <- keywords)
     names(keyword) = 1
@@ -38,7 +38,7 @@ private[chisel] class Namespace(parent: Option[Namespace], keywords: Set[String]
   def child: Namespace = child(Set())
 }
 
-private[chisel] class IdGen {
+private[chisel3] class IdGen {
   private var counter = -1L
   def next: Long = {
     counter += 1
@@ -46,12 +46,12 @@ private[chisel] class IdGen {
   }
 }
 
-private[chisel] trait HasId {
-  private[chisel] def _onModuleClose {} // scalastyle:ignore method.name
-  private[chisel] val _parent = Builder.dynamicContext.currentModule
+private[chisel3] trait HasId {
+  private[chisel3] def _onModuleClose {} // scalastyle:ignore method.name
+  private[chisel3] val _parent = Builder.dynamicContext.currentModule
   _parent.foreach(_.addId(this))
 
-  private[chisel] val _id = Builder.idGen.next
+  private[chisel3] val _id = Builder.idGen.next
   override def hashCode: Int = _id.toInt
   override def equals(that: Any): Boolean = that match {
     case x: HasId => _id == x._id
@@ -68,12 +68,12 @@ private[chisel] trait HasId {
     for(hook <- postname_hooks) { hook(name) }
     this
   }
-  private[chisel] def addPostnameHook(hook: String=>Unit): Unit = postname_hooks += hook
+  private[chisel3] def addPostnameHook(hook: String=>Unit): Unit = postname_hooks += hook
 
   // Uses a namespace to convert suggestion into a true name
   // Will not do any naming if the reference already assigned.
   // (e.g. tried to suggest a name to part of a Bundle)
-  private[chisel] def forceName(default: =>String, namespace: Namespace): Unit =
+  private[chisel3] def forceName(default: =>String, namespace: Namespace): Unit =
     if(_ref.isEmpty) {
       val candidate_name = suggested_name.getOrElse(default)
       val available_name = namespace.name(candidate_name)
@@ -81,14 +81,14 @@ private[chisel] trait HasId {
     }
 
   private var _ref: Option[Arg] = None
-  private[chisel] def setRef(imm: Arg): Unit = _ref = Some(imm)
-  private[chisel] def setRef(parent: HasId, name: String): Unit = setRef(Slot(Node(parent), name))
-  private[chisel] def setRef(parent: HasId, index: Int): Unit = setRef(Index(Node(parent), ILit(index)))
-  private[chisel] def setRef(parent: HasId, index: UInt): Unit = setRef(Index(Node(parent), index.ref))
-  private[chisel] def getRef: Arg = _ref.get
+  private[chisel3] def setRef(imm: Arg): Unit = _ref = Some(imm)
+  private[chisel3] def setRef(parent: HasId, name: String): Unit = setRef(Slot(Node(parent), name))
+  private[chisel3] def setRef(parent: HasId, index: Int): Unit = setRef(Index(Node(parent), ILit(index)))
+  private[chisel3] def setRef(parent: HasId, index: UInt): Unit = setRef(Index(Node(parent), index.ref))
+  private[chisel3] def getRef: Arg = _ref.get
 }
 
-private[chisel] class DynamicContext {
+private[chisel3] class DynamicContext {
   val idGen = new IdGen
   val globalNamespace = new Namespace(None, Set())
   val components = ArrayBuffer[Component]()
@@ -96,7 +96,7 @@ private[chisel] class DynamicContext {
   val errors = new ErrorLog
 }
 
-private[chisel] object Builder {
+private[chisel3] object Builder {
   // All global mutable state must be referenced via dynamicContextVar!!
   private val dynamicContextVar = new DynamicVariable[Option[DynamicContext]](None)
 
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Error.scala b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala
index f0481dc4..7ae0580f 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Error.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala
@@ -1,20 +1,20 @@
 // See LICENSE for license details.
 
-package chisel.internal
+package chisel3.internal
 
 import scala.collection.mutable.ArrayBuffer
 
-import chisel.core._
+import chisel3.core._
 
 class ChiselException(message: String, cause: Throwable) extends Exception(message, cause)
 
-private[chisel] object throwException {
+private[chisel3] object throwException {
   def apply(s: String, t: Throwable = null): Nothing =
     throw new ChiselException(s, t)
 }
 
 /** Records and reports runtime errors and warnings. */
-private[chisel] class ErrorLog {
+private[chisel3] class ErrorLog {
   def hasErrors: Boolean = errors.exists(_.isFatal)
 
   /** Log an error message */
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala b/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala
index c20bd130..5e3bf33e 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala
@@ -12,7 +12,7 @@
 // writers to append source locator information at the point of a library
 // function invocation.
 
-package chisel.internal.sourceinfo
+package chisel3.internal.sourceinfo
 
 import scala.language.experimental.macros
 import scala.reflect.macros.blackbox.Context
@@ -42,7 +42,7 @@ object SourceInfoMacro {
   def generate_source_info(c: Context): c.Tree = {
     import c.universe._
     val p = c.enclosingPosition
-    q"_root_.chisel.internal.sourceinfo.SourceLine(${p.source.file.name}, ${p.line}, ${p.column})"
+    q"_root_.chisel3.internal.sourceinfo.SourceLine(${p.source.file.name}, ${p.line}, ${p.column})"
   }
 }
 
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 70e9938b..64d7d5fd 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -1,11 +1,11 @@
 // See LICENSE for license details.
 
-package chisel.internal.firrtl
+package chisel3.internal.firrtl
 
-import chisel._
+import chisel3._
 import core._
-import chisel.internal._
-import chisel.internal.sourceinfo.{SourceInfo, NoSourceInfo}
+import chisel3.internal._
+import chisel3.internal.sourceinfo.{SourceInfo, NoSourceInfo}
 
 case class PrimOp(val name: String) {
   override def toString: String = name
@@ -55,8 +55,8 @@ case class Node(id: HasId) extends Arg {
 }
 
 abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
-  private[chisel] def forcedWidth = widthArg.known
-  private[chisel] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
+  private[chisel3] def forcedWidth = widthArg.known
+  private[chisel3] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
 
   protected def minWidth: Int
   if (forcedWidth) {
diff --git a/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
index 10b677b6..ba14b78f 100644
--- a/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
+++ b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
@@ -3,7 +3,7 @@
 // This file transform macro definitions to explicitly add implicit source info to Chisel method
 // calls.
 
-package chisel.internal.sourceinfo
+package chisel3.internal.sourceinfo
 
 import scala.language.experimental.macros
 import scala.reflect.macros.blackbox.Context
@@ -23,7 +23,7 @@ trait SourceInfoTransformMacro {
   val c: Context
   import c.universe._
   def thisObj = c.prefix.tree
-  def implicitSourceInfo = q"implicitly[_root_.chisel.internal.sourceinfo.SourceInfo]"
+  def implicitSourceInfo = q"implicitly[_root_.chisel3.internal.sourceinfo.SourceInfo]"
 }
 
 class WireTransform(val c: Context) extends SourceInfoTransformMacro {
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index ba2b1389..92e948cc 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package chisel
+package chisel3
 
 import scala.sys.process._
 import java.io._
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 56088562..139e9431 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -1,150 +1,150 @@
 // See LICENSE for license details.
 
 // Allows legacy users to continue using Chisel (capital C) package name while
-// moving to the more standard package naming convention chisel (lowercase c).
+// moving to the more standard package naming convention chisel3 (lowercase c).
 
 package object Chisel {
-  type Direction = chisel.core.Direction
-  val INPUT = chisel.core.INPUT
-  val OUTPUT = chisel.core.OUTPUT
-  val NO_DIR = chisel.core.NO_DIR
-
-  type Flipped = chisel.core.Flipped
-  type Data = chisel.core.Data
-  val Wire = chisel.core.Wire
-  val Clock = chisel.core.Clock
-  type Clock = chisel.core.Clock
-
-  type Aggregate = chisel.core.Aggregate
-  val Vec = chisel.core.Vec
-  type Vec[T <: Data] = chisel.core.Vec[T]
-  type VecLike[T <: Data] = chisel.core.VecLike[T]
-  type Bundle = chisel.core.Bundle
-
-  val assert = chisel.core.assert
-
-  type Element = chisel.core.Element
-  type Bits = chisel.core.Bits
-  val Bits = chisel.core.Bits
-  type Num[T <: Data] = chisel.core.Num[T]
-  type UInt = chisel.core.UInt
-  val UInt = chisel.core.UInt
-  type SInt = chisel.core.SInt
-  val SInt = chisel.core.SInt
-  type Bool = chisel.core.Bool
-  val Bool = chisel.core.Bool
-  val Mux = chisel.core.Mux
-
-  type BlackBox = chisel.core.BlackBox
-
-  val Mem = chisel.core.Mem
-  type MemBase[T <: Data] = chisel.core.MemBase[T]
-  type Mem[T <: Data] = chisel.core.Mem[T]
-  val SeqMem = chisel.core.SeqMem
-  type SeqMem[T <: Data] = chisel.core.SeqMem[T]
-
-  val Module = chisel.core.Module
-  type Module = chisel.core.Module
-
-  val printf = chisel.core.printf
-
-  val Reg = chisel.core.Reg
-
-  val when = chisel.core.when
-  type WhenContext = chisel.core.WhenContext
-
-
-  type BackendCompilationUtilities = chisel.BackendCompilationUtilities
-  val Driver = chisel.Driver
-  type FileSystemUtilities = chisel.compatibility.FileSystemUtilities
-  val ImplicitConversions = chisel.util.ImplicitConversions
-  val chiselMain = chisel.compatibility.chiselMain
-  val throwException = chisel.compatibility.throwException
-  val debug = chisel.compatibility.debug
+  type Direction = chisel3.core.Direction
+  val INPUT = chisel3.core.INPUT
+  val OUTPUT = chisel3.core.OUTPUT
+  val NO_DIR = chisel3.core.NO_DIR
+
+  type Flipped = chisel3.core.Flipped
+  type Data = chisel3.core.Data
+  val Wire = chisel3.core.Wire
+  val Clock = chisel3.core.Clock
+  type Clock = chisel3.core.Clock
+
+  type Aggregate = chisel3.core.Aggregate
+  val Vec = chisel3.core.Vec
+  type Vec[T <: Data] = chisel3.core.Vec[T]
+  type VecLike[T <: Data] = chisel3.core.VecLike[T]
+  type Bundle = chisel3.core.Bundle
+
+  val assert = chisel3.core.assert
+
+  type Element = chisel3.core.Element
+  type Bits = chisel3.core.Bits
+  val Bits = chisel3.core.Bits
+  type Num[T <: Data] = chisel3.core.Num[T]
+  type UInt = chisel3.core.UInt
+  val UInt = chisel3.core.UInt
+  type SInt = chisel3.core.SInt
+  val SInt = chisel3.core.SInt
+  type Bool = chisel3.core.Bool
+  val Bool = chisel3.core.Bool
+  val Mux = chisel3.core.Mux
+
+  type BlackBox = chisel3.core.BlackBox
+
+  val Mem = chisel3.core.Mem
+  type MemBase[T <: Data] = chisel3.core.MemBase[T]
+  type Mem[T <: Data] = chisel3.core.Mem[T]
+  val SeqMem = chisel3.core.SeqMem
+  type SeqMem[T <: Data] = chisel3.core.SeqMem[T]
+
+  val Module = chisel3.core.Module
+  type Module = chisel3.core.Module
+
+  val printf = chisel3.core.printf
+
+  val Reg = chisel3.core.Reg
+
+  val when = chisel3.core.when
+  type WhenContext = chisel3.core.WhenContext
+
+
+  type BackendCompilationUtilities = chisel3.BackendCompilationUtilities
+  val Driver = chisel3.Driver
+  type FileSystemUtilities = chisel3.compatibility.FileSystemUtilities
+  val ImplicitConversions = chisel3.util.ImplicitConversions
+  val chiselMain = chisel3.compatibility.chiselMain
+  val throwException = chisel3.compatibility.throwException
+  val debug = chisel3.compatibility.debug
 
   object testers {
-    type BasicTester = chisel.testers.BasicTester
-    val TesterDriver = chisel.testers.TesterDriver
+    type BasicTester = chisel3.testers.BasicTester
+    val TesterDriver = chisel3.testers.TesterDriver
   }
 
 
-  val log2Up = chisel.util.log2Up
-  val log2Ceil = chisel.util.log2Ceil
-  val log2Down = chisel.util.log2Down
-  val log2Floor = chisel.util.log2Floor
-  val isPow2 = chisel.util.isPow2
-
-  val BitPat = chisel.util.BitPat
-  type BitPat = chisel.util.BitPat
-
-  type ArbiterIO[T <: Data] = chisel.util.ArbiterIO[T]
-  type LockingArbiterLike[T <: Data] = chisel.util.LockingArbiterLike[T]
-  type LockingRRArbiter[T <: Data] = chisel.util.LockingRRArbiter[T]
-  type LockingArbiter[T <: Data] = chisel.util.LockingArbiter[T]
-  type RRArbiter[T <: Data] = chisel.util.RRArbiter[T]
-  type Arbiter[T <: Data] = chisel.util.Arbiter[T]
-
-  val FillInterleaved = chisel.util.FillInterleaved
-  val PopCount = chisel.util.PopCount
-  val Fill = chisel.util.Fill
-  val Reverse = chisel.util.Reverse
-
-  val Cat = chisel.util.Cat
-
-  val Log2 = chisel.util.Log2
-
-  val unless = chisel.util.unless
-  type SwitchContext[T <: Bits] = chisel.util.SwitchContext[T]
-  val is = chisel.util.is
-  val switch = chisel.util.switch
-
-  type Counter = chisel.util.Counter
-  val Counter = chisel.util.Counter
-
-  type DecoupledIO[+T <: Data] = chisel.util.DecoupledIO[T]
-  val Decoupled = chisel.util.Decoupled
-  type EnqIO[T <: Data] = chisel.util.EnqIO[T]
-  type DeqIO[T <: Data] = chisel.util.DeqIO[T]
-  type DecoupledIOC[+T <: Data] = chisel.util.DecoupledIOC[T]
-  type QueueIO[T <: Data] = chisel.util.QueueIO[T]
-  type Queue[T <: Data] = chisel.util.Queue[T]
-  val Queue = chisel.util.Queue
-
-  val Enum = chisel.util.Enum
-
-  val LFSR16 = chisel.util.LFSR16
-
-  val ListLookup = chisel.util.ListLookup
-  val Lookup = chisel.util.Lookup
-
-  val Mux1H = chisel.util.Mux1H
-  val PriorityMux = chisel.util.PriorityMux
-  val MuxLookup = chisel.util.MuxLookup
-  val MuxCase = chisel.util.MuxCase
-
-  val OHToUInt = chisel.util.OHToUInt
-  val PriorityEncoder = chisel.util.PriorityEncoder
-  val UIntToOH = chisel.util.UIntToOH
-  val PriorityEncoderOH = chisel.util.PriorityEncoderOH
-
-  val RegNext = chisel.util.RegNext
-  val RegInit = chisel.util.RegInit
-  val RegEnable = chisel.util.RegEnable
-  val ShiftRegister = chisel.util.ShiftRegister
-
-  type ValidIO[+T <: Data] = chisel.util.ValidIO[T]
-  val Valid = chisel.util.Valid
-  val Pipe = chisel.util.Pipe
-  type Pipe[T <: Data] = chisel.util.Pipe[T]
-
-
-  import chisel.internal.firrtl.Width
-  implicit def fromBigIntToLiteral(x: BigInt): chisel.fromBigIntToLiteral =
-    new chisel.fromBigIntToLiteral(x)
-  implicit def fromIntToLiteral(x: Int): chisel.fromIntToLiteral=
-    new chisel.fromIntToLiteral(x)
-  implicit def fromStringToLiteral(x: String): chisel.fromStringToLiteral=
-    new chisel.fromStringToLiteral(x)
-  implicit def fromBooleanToLiteral(x: Boolean): chisel.fromBooleanToLiteral=
-    new chisel.fromBooleanToLiteral(x)
+  val log2Up = chisel3.util.log2Up
+  val log2Ceil = chisel3.util.log2Ceil
+  val log2Down = chisel3.util.log2Down
+  val log2Floor = chisel3.util.log2Floor
+  val isPow2 = chisel3.util.isPow2
+
+  val BitPat = chisel3.util.BitPat
+  type BitPat = chisel3.util.BitPat
+
+  type ArbiterIO[T <: Data] = chisel3.util.ArbiterIO[T]
+  type LockingArbiterLike[T <: Data] = chisel3.util.LockingArbiterLike[T]
+  type LockingRRArbiter[T <: Data] = chisel3.util.LockingRRArbiter[T]
+  type LockingArbiter[T <: Data] = chisel3.util.LockingArbiter[T]
+  type RRArbiter[T <: Data] = chisel3.util.RRArbiter[T]
+  type Arbiter[T <: Data] = chisel3.util.Arbiter[T]
+
+  val FillInterleaved = chisel3.util.FillInterleaved
+  val PopCount = chisel3.util.PopCount
+  val Fill = chisel3.util.Fill
+  val Reverse = chisel3.util.Reverse
+
+  val Cat = chisel3.util.Cat
+
+  val Log2 = chisel3.util.Log2
+
+  val unless = chisel3.util.unless
+  type SwitchContext[T <: Bits] = chisel3.util.SwitchContext[T]
+  val is = chisel3.util.is
+  val switch = chisel3.util.switch
+
+  type Counter = chisel3.util.Counter
+  val Counter = chisel3.util.Counter
+
+  type DecoupledIO[+T <: Data] = chisel3.util.DecoupledIO[T]
+  val Decoupled = chisel3.util.Decoupled
+  type EnqIO[T <: Data] = chisel3.util.EnqIO[T]
+  type DeqIO[T <: Data] = chisel3.util.DeqIO[T]
+  type DecoupledIOC[+T <: Data] = chisel3.util.DecoupledIOC[T]
+  type QueueIO[T <: Data] = chisel3.util.QueueIO[T]
+  type Queue[T <: Data] = chisel3.util.Queue[T]
+  val Queue = chisel3.util.Queue
+
+  val Enum = chisel3.util.Enum
+
+  val LFSR16 = chisel3.util.LFSR16
+
+  val ListLookup = chisel3.util.ListLookup
+  val Lookup = chisel3.util.Lookup
+
+  val Mux1H = chisel3.util.Mux1H
+  val PriorityMux = chisel3.util.PriorityMux
+  val MuxLookup = chisel3.util.MuxLookup
+  val MuxCase = chisel3.util.MuxCase
+
+  val OHToUInt = chisel3.util.OHToUInt
+  val PriorityEncoder = chisel3.util.PriorityEncoder
+  val UIntToOH = chisel3.util.UIntToOH
+  val PriorityEncoderOH = chisel3.util.PriorityEncoderOH
+
+  val RegNext = chisel3.util.RegNext
+  val RegInit = chisel3.util.RegInit
+  val RegEnable = chisel3.util.RegEnable
+  val ShiftRegister = chisel3.util.ShiftRegister
+
+  type ValidIO[+T <: Data] = chisel3.util.ValidIO[T]
+  val Valid = chisel3.util.Valid
+  val Pipe = chisel3.util.Pipe
+  type Pipe[T <: Data] = chisel3.util.Pipe[T]
+
+
+  import chisel3.internal.firrtl.Width
+  implicit def fromBigIntToLiteral(x: BigInt): chisel3.fromBigIntToLiteral =
+    new chisel3.fromBigIntToLiteral(x)
+  implicit def fromIntToLiteral(x: Int): chisel3.fromIntToLiteral=
+    new chisel3.fromIntToLiteral(x)
+  implicit def fromStringToLiteral(x: String): chisel3.fromStringToLiteral=
+    new chisel3.fromStringToLiteral(x)
+  implicit def fromBooleanToLiteral(x: Boolean): chisel3.fromBooleanToLiteral=
+    new chisel3.fromBooleanToLiteral(x)
 }
diff --git a/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala b/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala
index d12e627d..cd47c731 100644
--- a/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala
+++ b/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala
@@ -1,8 +1,8 @@
 // See LICENSE for license details.
 
-package chisel.compatibility
+package chisel3.compatibility
 
-import chisel._
+import chisel3._
 
 @deprecated("FileSystemUtilities doesn't exist in chisel3", "3.0.0")
 trait FileSystemUtilities {
diff --git a/src/main/scala/chisel3/compatibility/Main.scala b/src/main/scala/chisel3/compatibility/Main.scala
index 9072bfcf..a41599a3 100644
--- a/src/main/scala/chisel3/compatibility/Main.scala
+++ b/src/main/scala/chisel3/compatibility/Main.scala
@@ -1,10 +1,10 @@
 // See LICENSE for license details.
 
-package chisel.compatibility
+package chisel3.compatibility
 
 import java.io.File
 
-import chisel._
+import chisel3._
 
 @deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain {
   def apply[T <: Module](args: Array[String], gen: () => T): Unit =
diff --git a/src/main/scala/chisel3/compatibility/debug.scala b/src/main/scala/chisel3/compatibility/debug.scala
index 8850c76b..c3966dae 100644
--- a/src/main/scala/chisel3/compatibility/debug.scala
+++ b/src/main/scala/chisel3/compatibility/debug.scala
@@ -1,6 +1,6 @@
-package chisel.compatibility
+package chisel3.compatibility
 
-import chisel.core._
+import chisel3.core._
 
 @deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3")
 object debug {  // scalastyle:ignore object.name
diff --git a/src/main/scala/chisel3/compatibility/throwException.scala b/src/main/scala/chisel3/compatibility/throwException.scala
index 3b9fd06e..3e8b33e6 100644
--- a/src/main/scala/chisel3/compatibility/throwException.scala
+++ b/src/main/scala/chisel3/compatibility/throwException.scala
@@ -1,8 +1,8 @@
 // See LICENSE for license details.
 
-package chisel.compatibility
+package chisel3.compatibility
 
-import chisel._
+import chisel3._
 
 @deprecated("throwException doesn't exist in Chisel3", "3.0.0")
 @throws(classOf[Exception])
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index e48eb226..08646cf9 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -1,10 +1,10 @@
 // See LICENSE for license details.
 
-package chisel.internal.firrtl
-import chisel._
-import chisel.internal.sourceinfo.{NoSourceInfo, SourceLine}
+package chisel3.internal.firrtl
+import chisel3._
+import chisel3.internal.sourceinfo.{NoSourceInfo, SourceLine}
 
-private[chisel] object Emitter {
+private[chisel3] object Emitter {
   def emit(circuit: Circuit): String = new Emitter(circuit).toString
 }
 
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index f7ed6b13..0b548683 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -1,4 +1,4 @@
-package object chisel {
+package object chisel3 {
   import scala.language.experimental.macros
 
   import internal.firrtl.Width
@@ -6,53 +6,53 @@ package object chisel {
   import util.BitPat
 
 
-  type Direction = chisel.core.Direction
-  val INPUT = chisel.core.INPUT
-  val OUTPUT = chisel.core.OUTPUT
-  val NO_DIR = chisel.core.NO_DIR
-  type Flipped = chisel.core.Flipped
-  type Data = chisel.core.Data
-  val Wire = chisel.core.Wire
-  val Clock = chisel.core.Clock
-  type Clock = chisel.core.Clock
-
-  type Aggregate = chisel.core.Aggregate
-  val Vec = chisel.core.Vec
-  type Vec[T <: Data] = chisel.core.Vec[T]
-  type VecLike[T <: Data] = chisel.core.VecLike[T]
-  type Bundle = chisel.core.Bundle
-
-  val assert = chisel.core.assert
-
-  type Element = chisel.core.Element
-  type Bits = chisel.core.Bits
-  val Bits = chisel.core.Bits
-  type Num[T <: Data] = chisel.core.Num[T]
-  type UInt = chisel.core.UInt
-  val UInt = chisel.core.UInt
-  type SInt = chisel.core.SInt
-  val SInt = chisel.core.SInt
-  type Bool = chisel.core.Bool
-  val Bool = chisel.core.Bool
-  val Mux = chisel.core.Mux
-
-  type BlackBox = chisel.core.BlackBox
-
-  val Mem = chisel.core.Mem
-  type MemBase[T <: Data] = chisel.core.MemBase[T]
-  type Mem[T <: Data] = chisel.core.Mem[T]
-  val SeqMem = chisel.core.SeqMem
-  type SeqMem[T <: Data] = chisel.core.SeqMem[T]
-
-  val Module = chisel.core.Module
-  type Module = chisel.core.Module
-
-  val printf = chisel.core.printf
-
-  val Reg = chisel.core.Reg
-
-  val when = chisel.core.when
-  type WhenContext = chisel.core.WhenContext
+  type Direction = chisel3.core.Direction
+  val INPUT = chisel3.core.INPUT
+  val OUTPUT = chisel3.core.OUTPUT
+  val NO_DIR = chisel3.core.NO_DIR
+  type Flipped = chisel3.core.Flipped
+  type Data = chisel3.core.Data
+  val Wire = chisel3.core.Wire
+  val Clock = chisel3.core.Clock
+  type Clock = chisel3.core.Clock
+
+  type Aggregate = chisel3.core.Aggregate
+  val Vec = chisel3.core.Vec
+  type Vec[T <: Data] = chisel3.core.Vec[T]
+  type VecLike[T <: Data] = chisel3.core.VecLike[T]
+  type Bundle = chisel3.core.Bundle
+
+  val assert = chisel3.core.assert
+
+  type Element = chisel3.core.Element
+  type Bits = chisel3.core.Bits
+  val Bits = chisel3.core.Bits
+  type Num[T <: Data] = chisel3.core.Num[T]
+  type UInt = chisel3.core.UInt
+  val UInt = chisel3.core.UInt
+  type SInt = chisel3.core.SInt
+  val SInt = chisel3.core.SInt
+  type Bool = chisel3.core.Bool
+  val Bool = chisel3.core.Bool
+  val Mux = chisel3.core.Mux
+
+  type BlackBox = chisel3.core.BlackBox
+
+  val Mem = chisel3.core.Mem
+  type MemBase[T <: Data] = chisel3.core.MemBase[T]
+  type Mem[T <: Data] = chisel3.core.Mem[T]
+  val SeqMem = chisel3.core.SeqMem
+  type SeqMem[T <: Data] = chisel3.core.SeqMem[T]
+
+  val Module = chisel3.core.Module
+  type Module = chisel3.core.Module
+
+  val printf = chisel3.core.printf
+
+  val Reg = chisel3.core.Reg
+
+  val when = chisel3.core.when
+  type WhenContext = chisel3.core.WhenContext
 
 
   implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
diff --git a/src/main/scala/chisel3/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala
index 36ff7c52..f91536d5 100644
--- a/src/main/scala/chisel3/testers/BasicTester.scala
+++ b/src/main/scala/chisel3/testers/BasicTester.scala
@@ -1,7 +1,7 @@
 // See LICENSE for license details.
 
-package chisel.testers
-import chisel._
+package chisel3.testers
+import chisel3._
 
 import scala.language.experimental.macros
 
diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala
index 5c0275e0..586fa780 100644
--- a/src/main/scala/chisel3/testers/TesterDriver.scala
+++ b/src/main/scala/chisel3/testers/TesterDriver.scala
@@ -1,8 +1,8 @@
 // See LICENSE for license details.
 
-package chisel.testers
+package chisel3.testers
 
-import chisel._
+import chisel3._
 import scala.io.Source
 import scala.sys.process._
 import java.io._
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index 3723f2a9..eb541977 100644
--- a/src/main/scala/chisel3/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -3,9 +3,9 @@
 /** Arbiters in all shapes and sizes.
   */
 
-package chisel.util
+package chisel3.util
 
-import chisel._
+import chisel3._
 
 /** An I/O bundle for the Arbiter */
 class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index 13bbe1b0..9eb5cf67 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -1,11 +1,11 @@
 // See LICENSE for license details.
 
-package chisel.util
+package chisel3.util
 
 import scala.language.experimental.macros
 
-import chisel._
-import chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
+import chisel3._
+import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
 
 object BitPat {
   /** Parses a bit pattern string into (bits, mask, width).
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index d7d62ea3..ab1ff550 100644
--- a/src/main/scala/chisel3/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -3,10 +3,10 @@
 /** Miscellaneous circuit generators operating on bits.
   */
 
-package chisel.util
+package chisel3.util
 
-import chisel._
-import chisel.core.SeqUtils
+import chisel3._
+import chisel3.core.SeqUtils
 
 object FillInterleaved
 {
diff --git a/src/main/scala/chisel3/util/Cat.scala b/src/main/scala/chisel3/util/Cat.scala
index b47da706..469bf9ab 100644
--- a/src/main/scala/chisel3/util/Cat.scala
+++ b/src/main/scala/chisel3/util/Cat.scala
@@ -1,9 +1,9 @@
 // See LICENSE for license details.
 
-package chisel.util
+package chisel3.util
 
-import chisel._
-import chisel.core.SeqUtils
+import chisel3._
+import chisel3.core.SeqUtils
 
 object Cat {
   /** Combine data elements together
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index c3b94fdb..1174c71c 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -3,9 +3,9 @@
 /** Circuit-land math operations.
   */
 
-package chisel.util
+package chisel3.util
 
-import chisel._
+import chisel3._
 
 /** Compute Log2 with truncation of a UInt in hardware using a Mux Tree
   * An alternative interpretation is it computes the minimum number of bits needed to represent x
diff --git a/src/main/scala/chisel3/util/Conditional.scala b/src/main/scala/chisel3/util/Conditional.scala
index 01c12799..6218feb0 100644
--- a/src/main/scala/chisel3/util/Conditional.scala
+++ b/src/main/scala/chisel3/util/Conditional.scala
@@ -3,14 +3,14 @@
 /** Conditional blocks.
   */
 
-package chisel.util
+package chisel3.util
 
 import scala.language.reflectiveCalls
 import scala.language.experimental.macros
 import scala.reflect.runtime.universe._
 import scala.reflect.macros.blackbox._
 
-import chisel._
+import chisel3._
 
 /** This is identical to [[Chisel.when when]] with the condition inverted */
 object unless {  // scalastyle:ignore object.name
@@ -63,7 +63,7 @@ object switch {  // scalastyle:ignore object.name
     def extractIsStatement(tree: Tree): List[c.universe.Tree] = tree match {
       // TODO: remove when Chisel compatibility package is removed
       case q"Chisel.`package`.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
-      case q"chisel.util.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
+      case q"chisel3.util.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
       case b => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.")
     }
     val q"..$body" = x
diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index 1c0b0203..40615769 100644
--- a/src/main/scala/chisel3/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -1,8 +1,8 @@
 // See LICENSE for license details.
 
-package chisel.util
+package chisel3.util
 
-import chisel._
+import chisel3._
 
 /** A counter module
   * @param n number of counts before the counter resets (or one more than the
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 89b0e39d..f37a5c31 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -3,9 +3,9 @@
 /** Wrappers for ready-valid (Decoupled) interfaces and associated circuit generators using them.
   */
 
-package chisel.util
+package chisel3.util
 
-import chisel._
+import chisel3._
 
 /** An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'*/
 class DecoupledIO[+T <: Data](gen: T) extends Bundle
diff --git a/src/main/scala/chisel3/util/Enum.scala b/src/main/scala/chisel3/util/Enum.scala
index 8babcd23..4ecc243b 100644
--- a/src/main/scala/chisel3/util/Enum.scala
+++ b/src/main/scala/chisel3/util/Enum.scala
@@ -3,9 +3,9 @@
 /** Enum generators, allowing circuit constants to have more meaningful names.
   */
 
-package chisel.util
+package chisel3.util
 
-import chisel._
+import chisel3._
 
 object Enum {
   /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */
diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
index 846c0cbd..4d816a19 100644
--- a/src/main/scala/chisel3/util/ImplicitConversions.scala
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
@@ -1,8 +1,8 @@
 // See LICENSE for license details.
 
-package chisel.util
+package chisel3.util
 
-import chisel._
+import chisel3._
 
 object ImplicitConversions {
   implicit def intToUInt(x: Int): UInt = UInt(x)
diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala
index f70630bf..a30c276f 100644
--- a/src/main/scala/chisel3/util/LFSR.scala
+++ b/src/main/scala/chisel3/util/LFSR.scala
@@ -3,9 +3,9 @@
 /** LFSRs in all shapes and sizes.
   */
 
-package chisel.util
+package chisel3.util
 
-import chisel._
+import chisel3._
 
 // scalastyle:off magic.number
 /** linear feedback shift register
diff --git a/src/main/scala/chisel3/util/Lookup.scala b/src/main/scala/chisel3/util/Lookup.scala
index d32d9aec..9e909c0c 100644
--- a/src/main/scala/chisel3/util/Lookup.scala
+++ b/src/main/scala/chisel3/util/Lookup.scala
@@ -1,8 +1,8 @@
 // See LICENSE for license details.
 
-package chisel.util
+package chisel3.util
 
-import chisel._
+import chisel3._
 
 object ListLookup {
   def apply[T <: Data](addr: UInt, default: List[T], mapping: Array[(BitPat, List[T])]): List[T] = {
diff --git a/src/main/scala/chisel3/util/Math.scala b/src/main/scala/chisel3/util/Math.scala
index 69464d15..73665f0f 100644
--- a/src/main/scala/chisel3/util/Math.scala
+++ b/src/main/scala/chisel3/util/Math.scala
@@ -3,9 +3,9 @@
 /** Scala-land math helper functions, like logs.
   */
 
-package chisel.util
+package chisel3.util
 
-import chisel._
+import chisel3._
 
 /** Compute the log2 rounded up with min value of 1 */
 object log2Up {
diff --git a/src/main/scala/chisel3/util/Mux.scala b/src/main/scala/chisel3/util/Mux.scala
index 6f074a7e..07a34f9b 100644
--- a/src/main/scala/chisel3/util/Mux.scala
+++ b/src/main/scala/chisel3/util/Mux.scala
@@ -3,10 +3,10 @@
 /** Mux circuit generators.
   */
 
-package chisel.util
+package chisel3.util
 
-import chisel._
-import chisel.core.SeqUtils
+import chisel3._
+import chisel3.core.SeqUtils
 
 /** Builds a Mux tree out of the input signal vector using a one hot encoded
   select signal. Returns the output of the Mux tree.
diff --git a/src/main/scala/chisel3/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala
index ef21c65d..820c72d6 100644
--- a/src/main/scala/chisel3/util/OneHot.scala
+++ b/src/main/scala/chisel3/util/OneHot.scala
@@ -3,9 +3,9 @@
 /** Circuit generators for working with one-hot representations.
   */
 
-package chisel.util
+package chisel3.util
 
-import chisel._
+import chisel3._
 
 /** Converts from One Hot Encoding to a UInt indicating which bit is active
   * This is the inverse of [[Chisel.UIntToOH UIntToOH]]*/
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index 1b40646d..81de4754 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -3,9 +3,9 @@
 /** Variations and helpers for registers.
   */
 
-package chisel.util
+package chisel3.util
 
-import chisel._
+import chisel3._
 
 object RegNext {
 
diff --git a/src/main/scala/chisel3/util/TransitName.scala b/src/main/scala/chisel3/util/TransitName.scala
index 04e1995b..f36f926f 100644
--- a/src/main/scala/chisel3/util/TransitName.scala
+++ b/src/main/scala/chisel3/util/TransitName.scala
@@ -1,6 +1,6 @@
-package chisel.util
+package chisel3.util
 
-import chisel._
+import chisel3._
 import internal.HasId
 
 object TransitName {
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 56ac9abb..78187ff6 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -3,9 +3,9 @@
 /** Wrappers for valid interfaces and associated circuit generators using them.
   */
 
-package chisel.util
+package chisel3.util
 
-import chisel._
+import chisel3._
 
 /** An I/O Bundle containing data and a signal determining if it is valid */
 class ValidIO[+T <: Data](gen2: T) extends Bundle
diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index eb8617b2..3fed2bd4 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -3,9 +3,9 @@
 package chiselTests
 
 import org.scalatest._
-import chisel._
-import chisel.testers.BasicTester
-import chisel.util._
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class FailingAssertTester() extends BasicTester {
   assert(Bool(false))
diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala
index 0c1d4d74..08999a1b 100644
--- a/src/test/scala/chiselTests/BitwiseOps.scala
+++ b/src/test/scala/chiselTests/BitwiseOps.scala
@@ -2,10 +2,10 @@
 
 package chiselTests
 
-import chisel._
+import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
-import chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester {
   val mask = (1 << w) - 1
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index b77550c1..fdc5970e 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -5,9 +5,9 @@ package chiselTests
 import java.io.File
 import org.scalatest._
 
-import chisel._
-import chisel.testers.BasicTester
-import chisel.util._
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class BlackBoxInverter extends BlackBox {
   val io = new Bundle() {
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 36dbb365..e5e9fb1a 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -1,10 +1,10 @@
 // See LICENSE for license details.
 
 package chiselTests
-import chisel._
+import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
-import chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class Coord extends Bundle {
   val x = UInt(width = 32)
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index 9c66b0db..d335bdf6 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -6,8 +6,8 @@ import java.io.File
 import org.scalatest._
 import org.scalatest.prop._
 import org.scalacheck._
-import chisel._
-import chisel.testers._
+import chisel3._
+import chisel3.testers._
 
 /** Common utility functions for Chisel unit tests. */
 trait ChiselRunners extends Assertions {
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index 53a6a67d..304fbcf5 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -5,9 +5,9 @@ package chiselTests
 import org.scalatest._
 import org.scalatest.prop._
 
-import chisel._
-import chisel.testers.BasicTester
-import chisel.util._
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class Complex[T <: Data](val re: T, val im: T) extends Bundle {
   override def cloneType: this.type =
diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala
index 963c1c92..69d8a44a 100644
--- a/src/test/scala/chiselTests/Counter.scala
+++ b/src/test/scala/chiselTests/Counter.scala
@@ -5,9 +5,9 @@ package chiselTests
 import org.scalatest._
 import org.scalatest.prop._
 
-import chisel._
-import chisel.testers.BasicTester
-import chisel.util._
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class CountTester(max: Int) extends BasicTester {
   val cnt = Counter(max)
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index 33980955..5586561b 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -6,9 +6,9 @@ import org.scalatest._
 import org.scalatest.prop._
 import org.scalacheck._
 
-import chisel._
-import chisel.testers.BasicTester
-import chisel.util._
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class Decoder(bitpats: List[String]) extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala
index 95160140..09891647 100644
--- a/src/test/scala/chiselTests/DeqIOSpec.scala
+++ b/src/test/scala/chiselTests/DeqIOSpec.scala
@@ -2,9 +2,9 @@
 
 package chiselTests
 
-import chisel._
-import chisel.testers.BasicTester
-import chisel.util._
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 /**
   * Created by chick on 2/8/16.
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 3ed543aa..8b84f844 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -2,10 +2,10 @@
 
 package chiselTests
 
-import chisel._
+import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
-import chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class DirectionHaver extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 30fc2486..7db20fc1 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -1,8 +1,8 @@
 // See LICENSE for license details.
 
 package chiselTests
-import chisel._
-import chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class EnableShiftRegister extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index 77452db6..60a70cc8 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -2,8 +2,8 @@
 
 package chiselTests
 
-import chisel._
-import chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 import org.scalatest._
 import org.scalatest.prop._
 
diff --git a/src/test/scala/chiselTests/Harness.scala b/src/test/scala/chiselTests/Harness.scala
index 805e2de9..83f60391 100644
--- a/src/test/scala/chiselTests/Harness.scala
+++ b/src/test/scala/chiselTests/Harness.scala
@@ -2,13 +2,13 @@
 
 package chiselTests
 
-import chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 import org.scalatest._
 import org.scalatest.prop._
 import java.io.File
 
 class HarnessSpec extends ChiselPropSpec
-  with chisel.BackendCompilationUtilities {
+  with chisel3.BackendCompilationUtilities {
 
   def makeTrivialVerilog: (File => File) = makeHarness((prefix: String) => s"""
 module ${prefix};
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index b3e69884..a1699441 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -2,9 +2,9 @@
 
 package chiselTests
 
-import chisel._
-import chisel.testers.BasicTester
-import chisel.util._
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class LFSR16 extends Module {
   val io = new Bundle {
@@ -36,7 +36,7 @@ class LFSR16Tester(c: LFSR16) extends Tester(c) {
 }
 */
 
-//TODO: Use chisel.util version instead?
+//TODO: Use chisel3.util version instead?
 
 class LFSRSpec extends ChiselPropSpec {
 
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index b48d2881..679b894c 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -2,8 +2,8 @@
 
 package chiselTests
 
-import chisel._
-import chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class MemorySearch extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 64b00fab..23788b72 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -2,7 +2,7 @@
 
 package chiselTests
 
-import chisel._
+import chisel3._
 
 class SimpleIO extends Bundle {
   val in  = UInt(INPUT,  32)
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index 5e223f91..831e323f 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -2,10 +2,10 @@
 
 package chiselTests
 
-import chisel._
+import chisel3._
 import org.scalatest._
 import org.scalatest.prop._
-import chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class MulLookup(val w: Int) extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index 152e6723..c22a5e30 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -4,9 +4,9 @@ package chiselTests
 
 import org.scalatest._
 
-import chisel._
-import chisel.testers.BasicTester
-import chisel.util._
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class LastAssignTester() extends BasicTester {
   val cnt = Counter(2)
diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala
index ab3b6860..fa691b43 100644
--- a/src/test/scala/chiselTests/OptionBundle.scala
+++ b/src/test/scala/chiselTests/OptionBundle.scala
@@ -3,8 +3,8 @@
 package chiselTests
 
 import org.scalatest._
-import chisel._
-import chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class OptionBundle(hasIn: Boolean) extends Bundle {
   val in = if (hasIn) {
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
index 03496649..3fb0f955 100644
--- a/src/test/scala/chiselTests/Padding.scala
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -2,7 +2,7 @@
 
 package chiselTests
 
-import chisel._
+import chisel3._
 
 class Padder extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala
index e2629224..4859759e 100644
--- a/src/test/scala/chiselTests/ParameterizedModule.scala
+++ b/src/test/scala/chiselTests/ParameterizedModule.scala
@@ -3,8 +3,8 @@
 package chiselTests
 
 import org.scalatest._
-import chisel._
-import chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class ParameterizedModule(invert: Boolean) extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala
index b5e1e66e..c872fde4 100644
--- a/src/test/scala/chiselTests/Printf.scala
+++ b/src/test/scala/chiselTests/Printf.scala
@@ -3,8 +3,8 @@
 package chiselTests
 
 import org.scalatest._
-import chisel._
-import chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class SinglePrintfTester() extends BasicTester {
   val x = UInt(254)
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 8954c3ef..fc2cbf9d 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -3,8 +3,8 @@
 package chiselTests
 
 import org.scalatest._
-import chisel._
-import chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class RegSpec extends ChiselFlatSpec {
   "A Reg" should "throw an exception if not given any parameters" in {
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 741e9896..f5e61115 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -2,8 +2,8 @@
 
 package chiselTests
 
-import chisel._
-import chisel.util._
+import chisel3._
+import chisel3.util._
 
 class Risc extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index 07111af6..6cd013f1 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -2,8 +2,8 @@
 
 package chiselTests
 
-import chisel._
-import chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class SIntOps extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index 0ce228de..cbd9f3e3 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -4,8 +4,8 @@ package chiselTests
 
 import scala.collection.mutable.Stack
 
-import chisel._
-import chisel.util._
+import chisel3._
+import chisel3.util._
 
 class ChiselStack(val depth: Int) extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/Stop.scala b/src/test/scala/chiselTests/Stop.scala
index d57eb7c6..4afb077a 100644
--- a/src/test/scala/chiselTests/Stop.scala
+++ b/src/test/scala/chiselTests/Stop.scala
@@ -3,8 +3,8 @@
 package chiselTests
 
 import org.scalatest._
-import chisel._
-import chisel.testers.BasicTester
+import chisel3._
+import chisel3.testers.BasicTester
 
 class StopTester() extends BasicTester {
   stop()
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index 2049d8bb..d84cd85e 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -5,9 +5,9 @@ package chiselTests
 import org.scalatest._
 import org.scalatest.prop._
 
-import chisel._
-import chisel.testers.BasicTester
-import chisel.util._
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class Tbl(w: Int, n: Int) extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index 50290fab..2f3e9368 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -2,9 +2,9 @@
 
 package chiselTests
 
-import chisel._
-import chisel.testers.BasicTester
-import chisel.util._
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 /** Extend BasicTester with a simple circuit and finish method.  TesterDriver will call the
   * finish method after the FinishTester's constructor has completed, which will alter the
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index 8b2a31fd..c5069fc4 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -2,9 +2,9 @@
 
 package chiselTests
 
-import chisel._
+import chisel3._
 import org.scalatest._
-import chisel.testers.BasicTester
+import chisel3.testers.BasicTester
 
 class UIntOps extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 35a0c8bc..7dd80a13 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -5,9 +5,9 @@ package chiselTests
 import org.scalatest._
 import org.scalatest.prop._
 
-import chisel._
-import chisel.testers.BasicTester
-import chisel.util._
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class ValueTester(w: Int, values: List[Int]) extends BasicTester {
   val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error?
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index a1282071..07779faa 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -2,9 +2,9 @@
 
 package chiselTests
 
-import chisel._
-import chisel.testers.BasicTester
-import chisel.util._
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 /**
   * This test used to fail when assignment statements were
diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala
index 0d621e6a..f03cb881 100644
--- a/src/test/scala/chiselTests/VendingMachine.scala
+++ b/src/test/scala/chiselTests/VendingMachine.scala
@@ -2,8 +2,8 @@
 
 package chiselTests
 
-import chisel._
-import chisel.util._
+import chisel3._
+import chisel3.util._
 
 class VendingMachine extends Module {
   val io = new Bundle {
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index 1c9c3bc5..5f3d3e61 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -4,9 +4,9 @@ package chiselTests
 
 import org.scalatest._
 
-import chisel._
-import chisel.testers.BasicTester
-import chisel.util._
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
 
 class WhenTester() extends BasicTester {
   val cnt = Counter(4)