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authorJim Lawson2016-06-20 11:08:46 -0700
committerJim Lawson2016-06-20 11:08:46 -0700
commitd408d73a171535bd7c2ba9d0037c194022b8a62f (patch)
tree81885a99ec56e89532bc3fa338f22b163dcc4d1f
parentb5a534914795d9d17f4dfe623525f1b804e4c60f (diff)
Rename chisel3 package.
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala (renamed from chiselFrontend/src/main/scala/chisel/core/Aggregate.scala)0
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Assert.scala (renamed from chiselFrontend/src/main/scala/chisel/core/Assert.scala)0
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Bits.scala (renamed from chiselFrontend/src/main/scala/chisel/core/Bits.scala)0
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala (renamed from chiselFrontend/src/main/scala/chisel/core/BlackBox.scala)0
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Data.scala (renamed from chiselFrontend/src/main/scala/chisel/core/Data.scala)0
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Mem.scala (renamed from chiselFrontend/src/main/scala/chisel/core/Mem.scala)0
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Module.scala (renamed from chiselFrontend/src/main/scala/chisel/core/Module.scala)0
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Printf.scala (renamed from chiselFrontend/src/main/scala/chisel/core/Printf.scala)0
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Reg.scala (renamed from chiselFrontend/src/main/scala/chisel/core/Reg.scala)0
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala (renamed from chiselFrontend/src/main/scala/chisel/core/SeqUtils.scala)0
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/When.scala (renamed from chiselFrontend/src/main/scala/chisel/core/When.scala)0
-rw-r--r--chiselFrontend/src/main/scala/chisel3/internal/Builder.scala (renamed from chiselFrontend/src/main/scala/chisel/internal/Builder.scala)0
-rw-r--r--chiselFrontend/src/main/scala/chisel3/internal/Error.scala (renamed from chiselFrontend/src/main/scala/chisel/internal/Error.scala)0
-rw-r--r--chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala (renamed from chiselFrontend/src/main/scala/chisel/internal/SourceInfo.scala)0
-rw-r--r--chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala (renamed from chiselFrontend/src/main/scala/chisel/internal/firrtl/IR.scala)0
-rw-r--r--coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala (renamed from coreMacros/src/main/scala/chisel/internal/sourceinfo/SourceInfoTransform.scala)0
-rw-r--r--src/main/scala/chisel3/Driver.scala (renamed from src/main/scala/chisel/Driver.scala)0
-rw-r--r--src/main/scala/chisel3/compatibility.scala (renamed from src/main/scala/chisel/compatibility.scala)0
-rw-r--r--src/main/scala/chisel3/compatibility/FileSystemUtilities.scala (renamed from src/main/scala/chisel/compatibility/FileSystemUtilities.scala)0
-rw-r--r--src/main/scala/chisel3/compatibility/Main.scala (renamed from src/main/scala/chisel/compatibility/Main.scala)0
-rw-r--r--src/main/scala/chisel3/compatibility/debug.scala (renamed from src/main/scala/chisel/compatibility/debug.scala)0
-rw-r--r--src/main/scala/chisel3/compatibility/throwException.scala (renamed from src/main/scala/chisel/compatibility/throwException.scala)0
-rw-r--r--src/main/scala/chisel3/internal/firrtl/Emitter.scala (renamed from src/main/scala/chisel/internal/firrtl/Emitter.scala)0
-rw-r--r--src/main/scala/chisel3/package.scala (renamed from src/main/scala/chisel/package.scala)0
-rw-r--r--src/main/scala/chisel3/testers/BasicTester.scala (renamed from src/main/scala/chisel/testers/BasicTester.scala)0
-rw-r--r--src/main/scala/chisel3/testers/TesterDriver.scala (renamed from src/main/scala/chisel/testers/TesterDriver.scala)0
-rw-r--r--src/main/scala/chisel3/util/Arbiter.scala (renamed from src/main/scala/chisel/util/Arbiter.scala)0
-rw-r--r--src/main/scala/chisel3/util/BitPat.scala (renamed from src/main/scala/chisel/util/BitPat.scala)0
-rw-r--r--src/main/scala/chisel3/util/Bitwise.scala (renamed from src/main/scala/chisel/util/Bitwise.scala)0
-rw-r--r--src/main/scala/chisel3/util/Cat.scala (renamed from src/main/scala/chisel/util/Cat.scala)0
-rw-r--r--src/main/scala/chisel3/util/CircuitMath.scala (renamed from src/main/scala/chisel/util/CircuitMath.scala)0
-rw-r--r--src/main/scala/chisel3/util/Conditional.scala (renamed from src/main/scala/chisel/util/Conditional.scala)0
-rw-r--r--src/main/scala/chisel3/util/Counter.scala (renamed from src/main/scala/chisel/util/Counter.scala)0
-rw-r--r--src/main/scala/chisel3/util/Decoupled.scala (renamed from src/main/scala/chisel/util/Decoupled.scala)0
-rw-r--r--src/main/scala/chisel3/util/Enum.scala (renamed from src/main/scala/chisel/util/Enum.scala)0
-rw-r--r--src/main/scala/chisel3/util/ImplicitConversions.scala (renamed from src/main/scala/chisel/util/ImplicitConversions.scala)0
-rw-r--r--src/main/scala/chisel3/util/LFSR.scala (renamed from src/main/scala/chisel/util/LFSR.scala)0
-rw-r--r--src/main/scala/chisel3/util/Lookup.scala (renamed from src/main/scala/chisel/util/Lookup.scala)0
-rw-r--r--src/main/scala/chisel3/util/Math.scala (renamed from src/main/scala/chisel/util/Math.scala)0
-rw-r--r--src/main/scala/chisel3/util/Mux.scala (renamed from src/main/scala/chisel/util/Mux.scala)0
-rw-r--r--src/main/scala/chisel3/util/OneHot.scala (renamed from src/main/scala/chisel/util/OneHot.scala)0
-rw-r--r--src/main/scala/chisel3/util/Reg.scala (renamed from src/main/scala/chisel/util/Reg.scala)0
-rw-r--r--src/main/scala/chisel3/util/TransitName.scala (renamed from src/main/scala/chisel/util/TransitName.scala)0
-rw-r--r--src/main/scala/chisel3/util/Valid.scala (renamed from src/main/scala/chisel/util/Valid.scala)0
44 files changed, 0 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 38a42fea..38a42fea 100644
--- a/chiselFrontend/src/main/scala/chisel/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
diff --git a/chiselFrontend/src/main/scala/chisel/core/Assert.scala b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala
index 00cb00f4..00cb00f4 100644
--- a/chiselFrontend/src/main/scala/chisel/core/Assert.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala
diff --git a/chiselFrontend/src/main/scala/chisel/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 38e71f8d..38e71f8d 100644
--- a/chiselFrontend/src/main/scala/chisel/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
diff --git a/chiselFrontend/src/main/scala/chisel/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
index 2126ebce..2126ebce 100644
--- a/chiselFrontend/src/main/scala/chisel/core/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
diff --git a/chiselFrontend/src/main/scala/chisel/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index cae38144..cae38144 100644
--- a/chiselFrontend/src/main/scala/chisel/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
diff --git a/chiselFrontend/src/main/scala/chisel/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
index a2df2910..a2df2910 100644
--- a/chiselFrontend/src/main/scala/chisel/core/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
diff --git a/chiselFrontend/src/main/scala/chisel/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 1de3efe5..1de3efe5 100644
--- a/chiselFrontend/src/main/scala/chisel/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
diff --git a/chiselFrontend/src/main/scala/chisel/core/Printf.scala b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
index a7970816..a7970816 100644
--- a/chiselFrontend/src/main/scala/chisel/core/Printf.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
diff --git a/chiselFrontend/src/main/scala/chisel/core/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
index 78461334..78461334 100644
--- a/chiselFrontend/src/main/scala/chisel/core/Reg.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
diff --git a/chiselFrontend/src/main/scala/chisel/core/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
index e31119a5..e31119a5 100644
--- a/chiselFrontend/src/main/scala/chisel/core/SeqUtils.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
diff --git a/chiselFrontend/src/main/scala/chisel/core/When.scala b/chiselFrontend/src/main/scala/chisel3/core/When.scala
index 5d484313..5d484313 100644
--- a/chiselFrontend/src/main/scala/chisel/core/When.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/When.scala
diff --git a/chiselFrontend/src/main/scala/chisel/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index 01628105..01628105 100644
--- a/chiselFrontend/src/main/scala/chisel/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
diff --git a/chiselFrontend/src/main/scala/chisel/internal/Error.scala b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala
index f0481dc4..f0481dc4 100644
--- a/chiselFrontend/src/main/scala/chisel/internal/Error.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala
diff --git a/chiselFrontend/src/main/scala/chisel/internal/SourceInfo.scala b/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala
index c20bd130..c20bd130 100644
--- a/chiselFrontend/src/main/scala/chisel/internal/SourceInfo.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala
diff --git a/chiselFrontend/src/main/scala/chisel/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 70e9938b..70e9938b 100644
--- a/chiselFrontend/src/main/scala/chisel/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
diff --git a/coreMacros/src/main/scala/chisel/internal/sourceinfo/SourceInfoTransform.scala b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
index 10b677b6..10b677b6 100644
--- a/coreMacros/src/main/scala/chisel/internal/sourceinfo/SourceInfoTransform.scala
+++ b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
diff --git a/src/main/scala/chisel/Driver.scala b/src/main/scala/chisel3/Driver.scala
index ba2b1389..ba2b1389 100644
--- a/src/main/scala/chisel/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
diff --git a/src/main/scala/chisel/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 56088562..56088562 100644
--- a/src/main/scala/chisel/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
diff --git a/src/main/scala/chisel/compatibility/FileSystemUtilities.scala b/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala
index d12e627d..d12e627d 100644
--- a/src/main/scala/chisel/compatibility/FileSystemUtilities.scala
+++ b/src/main/scala/chisel3/compatibility/FileSystemUtilities.scala
diff --git a/src/main/scala/chisel/compatibility/Main.scala b/src/main/scala/chisel3/compatibility/Main.scala
index 9072bfcf..9072bfcf 100644
--- a/src/main/scala/chisel/compatibility/Main.scala
+++ b/src/main/scala/chisel3/compatibility/Main.scala
diff --git a/src/main/scala/chisel/compatibility/debug.scala b/src/main/scala/chisel3/compatibility/debug.scala
index 8850c76b..8850c76b 100644
--- a/src/main/scala/chisel/compatibility/debug.scala
+++ b/src/main/scala/chisel3/compatibility/debug.scala
diff --git a/src/main/scala/chisel/compatibility/throwException.scala b/src/main/scala/chisel3/compatibility/throwException.scala
index 3b9fd06e..3b9fd06e 100644
--- a/src/main/scala/chisel/compatibility/throwException.scala
+++ b/src/main/scala/chisel3/compatibility/throwException.scala
diff --git a/src/main/scala/chisel/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index e48eb226..e48eb226 100644
--- a/src/main/scala/chisel/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
diff --git a/src/main/scala/chisel/package.scala b/src/main/scala/chisel3/package.scala
index f7ed6b13..f7ed6b13 100644
--- a/src/main/scala/chisel/package.scala
+++ b/src/main/scala/chisel3/package.scala
diff --git a/src/main/scala/chisel/testers/BasicTester.scala b/src/main/scala/chisel3/testers/BasicTester.scala
index 36ff7c52..36ff7c52 100644
--- a/src/main/scala/chisel/testers/BasicTester.scala
+++ b/src/main/scala/chisel3/testers/BasicTester.scala
diff --git a/src/main/scala/chisel/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala
index 5c0275e0..5c0275e0 100644
--- a/src/main/scala/chisel/testers/TesterDriver.scala
+++ b/src/main/scala/chisel3/testers/TesterDriver.scala
diff --git a/src/main/scala/chisel/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index 3723f2a9..3723f2a9 100644
--- a/src/main/scala/chisel/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
diff --git a/src/main/scala/chisel/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index 13bbe1b0..13bbe1b0 100644
--- a/src/main/scala/chisel/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
diff --git a/src/main/scala/chisel/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index d7d62ea3..d7d62ea3 100644
--- a/src/main/scala/chisel/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
diff --git a/src/main/scala/chisel/util/Cat.scala b/src/main/scala/chisel3/util/Cat.scala
index b47da706..b47da706 100644
--- a/src/main/scala/chisel/util/Cat.scala
+++ b/src/main/scala/chisel3/util/Cat.scala
diff --git a/src/main/scala/chisel/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index c3b94fdb..c3b94fdb 100644
--- a/src/main/scala/chisel/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
diff --git a/src/main/scala/chisel/util/Conditional.scala b/src/main/scala/chisel3/util/Conditional.scala
index 01c12799..01c12799 100644
--- a/src/main/scala/chisel/util/Conditional.scala
+++ b/src/main/scala/chisel3/util/Conditional.scala
diff --git a/src/main/scala/chisel/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index 1c0b0203..1c0b0203 100644
--- a/src/main/scala/chisel/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
diff --git a/src/main/scala/chisel/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 89b0e39d..89b0e39d 100644
--- a/src/main/scala/chisel/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
diff --git a/src/main/scala/chisel/util/Enum.scala b/src/main/scala/chisel3/util/Enum.scala
index 8babcd23..8babcd23 100644
--- a/src/main/scala/chisel/util/Enum.scala
+++ b/src/main/scala/chisel3/util/Enum.scala
diff --git a/src/main/scala/chisel/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
index 846c0cbd..846c0cbd 100644
--- a/src/main/scala/chisel/util/ImplicitConversions.scala
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
diff --git a/src/main/scala/chisel/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala
index f70630bf..f70630bf 100644
--- a/src/main/scala/chisel/util/LFSR.scala
+++ b/src/main/scala/chisel3/util/LFSR.scala
diff --git a/src/main/scala/chisel/util/Lookup.scala b/src/main/scala/chisel3/util/Lookup.scala
index d32d9aec..d32d9aec 100644
--- a/src/main/scala/chisel/util/Lookup.scala
+++ b/src/main/scala/chisel3/util/Lookup.scala
diff --git a/src/main/scala/chisel/util/Math.scala b/src/main/scala/chisel3/util/Math.scala
index 69464d15..69464d15 100644
--- a/src/main/scala/chisel/util/Math.scala
+++ b/src/main/scala/chisel3/util/Math.scala
diff --git a/src/main/scala/chisel/util/Mux.scala b/src/main/scala/chisel3/util/Mux.scala
index 6f074a7e..6f074a7e 100644
--- a/src/main/scala/chisel/util/Mux.scala
+++ b/src/main/scala/chisel3/util/Mux.scala
diff --git a/src/main/scala/chisel/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala
index ef21c65d..ef21c65d 100644
--- a/src/main/scala/chisel/util/OneHot.scala
+++ b/src/main/scala/chisel3/util/OneHot.scala
diff --git a/src/main/scala/chisel/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index 1b40646d..1b40646d 100644
--- a/src/main/scala/chisel/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
diff --git a/src/main/scala/chisel/util/TransitName.scala b/src/main/scala/chisel3/util/TransitName.scala
index 04e1995b..04e1995b 100644
--- a/src/main/scala/chisel/util/TransitName.scala
+++ b/src/main/scala/chisel3/util/TransitName.scala
diff --git a/src/main/scala/chisel/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 56ac9abb..56ac9abb 100644
--- a/src/main/scala/chisel/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala