diff options
| author | Andrew Waterman | 2016-09-21 16:16:25 -0700 |
|---|---|---|
| committer | GitHub | 2016-09-21 16:16:25 -0700 |
| commit | b18e98ba2d058c7dd24f96f005486b70c856aeca (patch) | |
| tree | 568c644051035a81f17f6a8e70938ff55ee21cb7 /chiselFrontend/src/main/scala/chisel3/internal/firrtl | |
| parent | a2cb95bfe9e9c30b73284e97048fa0187ab0ee1d (diff) | |
Expose FIRRTL asClock construct
Additionally, fix Clock.asUInt (previously, it threw an esoteric exception), and add a simple test of both.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/internal/firrtl')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index e39b007e..0641686c 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -42,6 +42,7 @@ object PrimOp { val ConvertOp = PrimOp("cvt") val AsUIntOp = PrimOp("asUInt") val AsSIntOp = PrimOp("asSInt") + val AsClockOp = PrimOp("asClock") } abstract class Arg { |